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| document no. u11316ej4v1ud00 (4th edition) date published january 2003 n cp(k) pd784038, 784038y subseries 16-bit single-chip microcontrollers hardware pd784031 pd784031y pd784031(a) pd784035 pd784035y pd784035(a) pd784036 pd784036y pd784036(a) pd784037 pd784037y pd784038 pd784038y pd78p4038 pd78p4038y user's manual printed in japan
2 user? manual u11316ej4v1ud [memo] 3 user? manual u11316ej4v1ud notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. eeprom, fip, and iebus are trademarks of nec electronics corporation. ms-dos, windows, and windows nt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. ibm dos, pc/at and pc dos are trademarks of international business machines corporation. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. ethernet is a trademark of xerox corporation. osf/motif is a trademark of open software foundation, inc. tron is an abbreviation of the realtime operating system nucleus. itron is an abbreviation of industrial tron. 4 user? manual u11316ej4v1ud purchase of nec electronics i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. the information in this document is current as of september, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer s equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. 5 user s manual u11316ej4v1ud regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 fax: 021-6841-1137 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 fax: 6250-3583 j02.11 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 ?sucursal en espa?a madrid, spain tel: 091-504 27 87 fax: 091-504 28 60 v ? lizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 ?succursale fran?aise ?filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 ?branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 ?tyskland filial taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 ?united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: 6 user s manual u11316ej4v1ud major revisions in this edition (1/2) page description throughout addition of the following special grade products to the target products pd784031gc(a)-3b9, 784035gc(a)- -3b9, 784036gc(a)- -3b9 deletion of the following packages pd784031gc-3b9, 784031gk-be9, 784035gc- -3b9, 784035gk- -be9, 784036gc- -3b9, 784036gk- -be9, 784037gc- -3b9, 784037gk- -be9, 784038gc- -3b9, 784038gk- -be9, 78p4038gc-3b9, 78p4038gc- -3b9, 78p4038gc- -8bt, 78p4038gk-be9, 78p4038gk- -be9, 78p4038kk-t pd784031ygc-3b9, 784031ygk-be9, 784035ygc- -3b9, 784035ygk- -be9, 784036ygc- -3b9, 784036ygk- -be9, 784037ygc- -3b9, 784037ygk- -be9, 784038ygc- -3b9, 784038ygk- -be9, 78p4038ygc-3b9, 78p4038ygc- -3b9, 78p4038ygc- -8bt, 78p4038ygk-be9, 78p4038ygk- -be9, 78p4038ykk-t addition of the following packages pd784031gk-9eu, 784035gk- -9eu, 784036gk- -9eu, 784037gk- -9eu, 784038gk- -9eu, 78p4038gk-9eu pd784031ygk-9eu, 784035ygk- -9eu, 784036ygk- -9eu, 784037ygk- -9eu, 784038ygk- -9eu, 78p4038ygk-9eu chapter 1 general p.39 update of 78k/iv series product development diagram p.41 addition and deletion of products in 1.2 ordering information and quality grades p.53 addition of 1.7 differences between standard-grade products and special-grade products chapter 8 timer/counter 0 p.245 addition of caution on compare register cr00 match interrupt to 8.9 cautions chapter 9 timer/counter 1 p.283 addition of caution on compare register cr10 match interrupt to 9.8 cautions chapter 10 timer/counter 2 p.357 addition of caution on compare register cr20 match interrupt to 10.10 cautions chapter 14 a/d converter p.390 modification of description in figure 14-3 a/d converter mode register (adm) format chapter 17 asynchronous serial interface/3-wire serial i/o p.445 addition of caution on successive reception in 3-wire serial i/o mode to 17.5 cautions 7 user s manual u11316ej4v1ud major revisions in this edition (2/2) page description chapter 18 3-wire/2-wire serial i/o mode pp.452, 453 modification of figure 18-6 3-wire serial i/o mode timing 18.6 cautions p.460 addition of caution on transmit data write in 3-wire serial i/o mode p.460 addition of caution on serial clock count operation in 3-wire serial i/o mode p.461 addition of caution on serial clock output in 3-wire serial i/o mode p.462 addition of caution on successive reception in 3-wire serial i/o mode chapter 21 edge detection function p.498 addition of description to 21.2 edge detection for pins p20, p25 and p26 p.684 addition of chapter 28 electrical specifications p.711 addition of chapter 29 package drawings p.714 addition of chapter 30 recommended soldering conditions appendix a differences with pd784026 subseries p.718 addition of description in table a-1 differences with pd784026 subseries p.719 modification of description in appendix b development tools p.734 modification of description in appendix c embedded software the mark shows major revised points. 8 user s manual u11316ej4v1ud preface intended readership this manual is intended for user engineers who understand the functions of the pd784038, 784038y subseries and wish to design application systems using these subseries. the following are the target products in the pd784038, 784038y subseries. standard grade: pd784031, 784035, 784036, 784037, 784038, 78p4038, 784031y, 784035y, 784036y, 784037y, 784038y, 78p4038y special grade: pd784031(a) ,784035(a), 784036(a) purpose the purpose of this manual is to give users an understanding of the various hardware functions of the pd784038, 784038y subseries. organization the pd784038, 784038y subseries user s manual is divided into two volumes hardware (this manual) and instruction. hardware instruction pin functions cpu functions internal block functions addressing interrupts instruction set other on-chip peripheral functions electrical specifications certain operating precautions apply to these products. these precautions are stated at the relevant points in the text of each chapter, and are also summarized at the end of each chapter. be sure to read them. 9 user s manual u11316ej4v1ud how to read this manual readers are required to have a general knowledge of electrical and logic circuits and microcontrollers. unless otherwise specified the pd784038 in the pd784038 subseries is treated as the representative model of the mask rom models, the pd784031 is treated as the representative model of the rom-less model, and the pd78p4038 is treated as the representative model of the prom models. if there are functional differences the function of each model is described individually. even in this case, the pd784038 subseries is treated as the representative model. if you use the pd784038y subseries, take the pd784031, 784035, 784036, 784037, 784038, and 78p4038 as the pd784031y, 784035y, 784036y, 784037y, 784038y, and 78p4038y, respectively. the application examples presented in this manual are for the ?tandard?quality models in general-purpose electronic systems. if you wish to use the applications presented in this manual for electronic systems that require ?pecial?quality models, thoroughly study the parts and circuits to be actually used, and their quality grade. ? v dd and v ss pins this product is highly immune to noise and its power supply pins are classified into v dd and v ss , as follows. if there is no need to classify the power supply pins, v dd is used as the representative pin name. positive power supply and gnd of ports: v dd0 , v ss0 positive power supply and gnd of function blocks other than ports: v dd1 , v ss1 ? for a general understanding of the functions: read in accordance with the contents . ? to find out about differences from the pd784026 subseries: see appendix a differences with pd784026 subseries . ? if the device operates strangely after debugging: cautions are summarized at the end of each chapter, so refer to the cautions for the relevant function. ? to check the details of a register when the register name is known: use appendix d register index . ? for the details of the instruction functions: refer to the separate 78k/iv series instruction user? manual (u10905e) . ? to find out about the electrical characteristics: refer to chapter 28 electrical specifications . ? to find out about application examples of each function: refer to application note separately available. 10 user s manual u11316ej4v1ud differences between pd784038 subseries and pd784038y subseries the functions of the pd784038 subseries and pd784038y subseries are the same except the clocked serial interface. caution the clocked serial interface is described in the following two chapters: chapter 18 3-/2-wire serial i/o mode chapter 19 i 2 c bus mode ( pd784038y subseries only) also refer to the general explanation on the serial interface in chapter 16. legend significance in data notation : higher digit on left, lower digit on right active-low notation : (line above pin or signal name) note : description of note in the text caution : item to be especially noted remark : supplementary information numeric notations : binary ................. b or decimal .............. hexadecimal ....... h register notation 7 b edc 6 1 5 0 4 3 a 2 1 1 0 0 write operation read operation 0 or 1 is written. the operation is not affected by either value. 0 must be written 1 must be written a value is written according to the function to be used. a value is read according to the operating status. 0 or 1 is read. 0 is read. 1 is read. where the bit number is marked with a circle, the bit name is reserved for nec electronics assembler and is defined as an sfr variable by the #pragma sfr directive for c compiler. code combinations marked ?etting prohibited?in the register notations in the text must not be written. easily confused characters : 0 (zero), o (letter o) : 1 (one), l (lower-case letter l), i (upper-case letter i) 11 user s manual u11316ej4v1ud related documents the related documents in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd784038, 784038y subseries user s manual - hardware this manual 78k/iv series application note - software fundamentals u10095e 78k/iv series user's manual - instructions u10905e documents related to development tools (user? manuals) document name document no. ra78k4 assembler package operation u15254e language u15255e structured assembler preprocessor u11743e cc78k4 c compiler operation u15557e language u15556e sm78k series ver. 2.30 or later system simulator operation (windows based) u15373e external part user open interface specification u15802e id78k series integrated debugger ver. 2.30 or later operation (windows based) u15185e rx78k4 real-time os fundamentals u10603e installation u10604e project manager ver 3.12 or later (windows based) u14610e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. 12 user s manual u11316ej4v1ud documents related to development hardware tools (user? manuals) document name document no. ie-78k4-ns in-circuit emulator u13356e ie-784038-ns-em1 emulation board u13760e ie-784000-r in-circuit emulator u12903e ie-784038-r-em1 emulation board u11383e documents related to prom writing (user? manuals) document name document no. pg-1500 prom programmer u11940e pg-1500 controller pc-9800 series (ms-dos)-based eeu-1291 ibm pc series (pc dos)-based u10540e other related documents document name document no. semiconductor selection guide - products & packages - x13769e semiconductor device mounting technology manual c10535e quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. 13 user? manual u11316ej4v1ud contents chapter 1 general ............................................................................................................... 38 1.1 features .................................................................................................................... .. 40 1.2 ordering information and quality grades ........................................... 41 1.2.1 ordering information ........................................................................................................ 41 1.2.2 quality grades ................................................................................................................. 43 1.3 pin configuration (top view) .......................................................................... 45 1.3.1 normal operating mode .................................................................................................. 45 1.3.2 prom programming mode (v pp +5 v/+12.5 v, reset = l) .................................... 48 1.4 application system configuration example (ppc) ............................. 49 1.5 block diagram ......................................................................................................... 50 1.6 list of functions .................................................................................................. 51 1.7 differences between standard-grade products and special-grade products ....................................................... 53 1.8 major differences with pd784026 subseries .......................................... 53 chapter 2 pin functions .................................................................................................... 54 2.1 pin function tables ............................................................................................. 54 2.1.1 normal operating mode .................................................................................................. 54 2.1.2 prom programming mode ( pd78p4038 only: v pp +5 v/+12.5 v, reset = l) ... 57 2.2 pin functions ............................................................................................................ 58 2.2.1 normal operating mode .................................................................................................. 58 2.2.2 prom programming mode ( pd78p4038) .................................................................... 65 2.3 input/output circuits and connection of unused pins .................. 66 2.4 cautions ....................................................................................................................... 69 chapter 3 cpu architecture ........................................................................................... 70 3.1 memory space .......................................................................................................... 70 3.2 internal rom area ............................................................................................... 77 3.3 base area .................................................................................................................. .78 3.3.1 vector table area ............................................................................................................ 78 3.3.2 callt instruction table area ......................................................................................... 79 3.3.3 callf instruction entry area ......................................................................................... 79 3.4 internal data area .............................................................................................. 80 3.4.1 internal ram area ........................................................................................................... 80 3.4.2 special function register (sfr) area ........................................................................... 82 3.4.3 external sfr area ........................................................................................................... 82 3.5 external memory space .................................................................................... 83 3.6 pd78p4038 memory mapping ............................................................................. 83 3.7 control registers ................................................................................................ 84 3.7.1 program counter (pc) ..................................................................................................... 84 3.7.2 program status word (psw) .......................................................................................... 84 3.7.3 use of rss bit ................................................................................................................. 87 3.7.4 stack pointer (sp) ........................................................................................................... 89 3.8 general registers ................................................................................................ 92 14 user? manual u11316ej4v1ud 3.8.1 configuration .................................................................................................................... 92 3.8.2 functions .......................................................................................................................... 94 3.9 special function registers (sfrs) .............................................................. 97 3.10 cautions ....................................................................................................................... 102 chapter 4 clock generator ........................................................................................... 104 4.1 configuration and function ........................................................................... 104 4.2 control registers ................................................................................................ 106 4.2.1 standby control register (stbc) ................................................................................... 106 4.2.2 oscillation stabilization time specification register (osts) ....................................... 107 4.3 clock generator operation ........................................................................... 108 4.3.1 clock oscillator ................................................................................................................ 108 4.3.2 divider .............................................................................................................................. 1 08 4.4 cautions ....................................................................................................................... 109 4.4.1 when an external clock is input .................................................................................... 109 4.4.2 when crystal/ceramic oscillation is used ..................................................................... 110 chapter 5 port functions ................................................................................................ 113 5.1 digital input/output ports .............................................................................. 113 5.2 port 0 ..................................................................................................................... ...... 115 5.2.1 hardware configuration ................................................................................................... 115 5.2.2 i/o mode/control mode setting ...................................................................................... 116 5.2.3 operating status .............................................................................................................. 116 5.2.4 internal pull-up resistors ................................................................................................ 118 5.2.5 transistor drive ................................................................................................................ 119 5.3 port 1 ..................................................................................................................... ...... 120 5.3.1 hardware configuration ................................................................................................... 121 5.3.2 i/o mode/control mode setting ...................................................................................... 126 5.3.3 operating status .............................................................................................................. 127 5.3.4 internal pull-up resistors ................................................................................................ 129 5.3.5 direct led drive .............................................................................................................. 130 5.4 port 2 ..................................................................................................................... ...... 131 5.4.1 hardware configuration ................................................................................................... 132 5.4.2 input mode/control mode setting ................................................................................... 134 5.4.3 operating status .............................................................................................................. 134 5.4.4 internal pull-up resistors ................................................................................................ 134 5.5 port 3 ..................................................................................................................... ...... 136 5.5.1 hardware configuration ................................................................................................... 137 5.5.2 i/o mode/control mode setting ...................................................................................... 141 5.5.3 operating status .............................................................................................................. 142 5.5.4 internal pull-up resistors ................................................................................................ 144 5.6 port 4 ..................................................................................................................... ...... 145 5.6.1 hardware configuration ................................................................................................... 145 5.6.2 i/o mode/control mode setting ...................................................................................... 147 5.6.3 operating status .............................................................................................................. 148 5.6.4 internal pull-up resistors ................................................................................................ 150 5.6.5 direct led drive .............................................................................................................. 151 5.7 port 5 ..................................................................................................................... ...... 151 15 user? manual u11316ej4v1ud 5.7.1 hardware configuration ................................................................................................... 151 5.7.2 i/o mode/control mode setting ...................................................................................... 153 5.7.3 operating status .............................................................................................................. 154 5.7.4 internal pull-up resistors ................................................................................................ 156 5.7.5 direct led drive .............................................................................................................. 157 5.8 port 6 ..................................................................................................................... ...... 158 5.8.1 hardware configuration ................................................................................................... 160 5.8.2 i/o mode/control mode setting ...................................................................................... 164 5.8.3 operating status .............................................................................................................. 165 5.8.4 internal pull-up resistors ................................................................................................ 167 5.9 port 7 ..................................................................................................................... ...... 168 5.9.1 hardware configuration ................................................................................................... 168 5.9.2 i/o mode/control mode setting ...................................................................................... 169 5.9.3 operating status .............................................................................................................. 169 5.9.4 internal pull-up resistors ................................................................................................ 170 5.9.5 caution ............................................................................................................................. 17 0 5.10 port output check function ......................................................................... 171 5.11 cautions ....................................................................................................................... 172 chapter 6 real-time output function ....................................................................... 173 6.1 configuration and function ........................................................................... 173 6.2 real-time output port control register (rtpc) ................................ 175 6.3 real-time output port accesses .................................................................. 176 6.4 operation .................................................................................................................... 178 6.5 example of use ....................................................................................................... 181 6.6 cautions ....................................................................................................................... 183 chapter 7 outline of timer/counter .......................................................................... 184 chapter 8 timer/counter 0 ............................................................................................... 186 8.1 functions .................................................................................................................... 186 8.2 configuration ........................................................................................................... 189 8.3 timer/counter 0 control registers ........................................................... 193 8.4 16-bit timer register 0 (tm0) operation ................................................... 198 8.4.1 basic operation ............................................................................................................... 198 8.4.2 clear operation ................................................................................................................ 200 8.5 external event counter function ............................................................. 202 8.6 compare register and capture register operation ...................... 205 8.6.1 compare operations ....................................................................................................... 205 8.6.2 capture operations ......................................................................................................... 207 8.7 basic operation of output control circuit ....................................... 208 8.7.1 basic operation ............................................................................................................... 210 8.7.2 toggle output .................................................................................................................. 210 8.7.3 pwm output ..................................................................................................................... 211 8.7.4 ppg output ...................................................................................................................... 217 8.7.5 software triggered one-shot pulse output ................................................................... 223 8.8 examples of use .................................................................................................... 224 8.8.1 operation as interval timer (1) ....................................................................................... 224 16 user? manual u11316ej4v1ud 8.8.2 operation as interval timer (2) ....................................................................................... 226 8.8.3 pulse width measurement operation ............................................................................. 228 8.8.4 operation as pwm output .............................................................................................. 230 8.8.5 operation as ppg output ............................................................................................... 234 8.8.6 example of software triggered one-shot pulse output ............................................... 238 8.9 cautions ....................................................................................................................... 241 chapter 9 timer/counter 1 ............................................................................................... 246 9.1 functions .................................................................................................................... 246 9.2 configuration ........................................................................................................... 248 9.3 timer/counter 1 control registers ........................................................... 252 9.4 timer register 1 (tm1) operation ................................................................ 256 9.4.1 basic operation ............................................................................................................... 256 9.4.2 clear operation ................................................................................................................ 259 9.5 external event counter function ............................................................. 261 9.6 compare register, capture/compare register, and capture register operation ........................................................................... 264 9.6.1 compare operations ....................................................................................................... 264 9.6.2 capture operations ......................................................................................................... 266 9.7 examples of use .................................................................................................... 270 9.7.1 operation as interval timer (1) ....................................................................................... 270 9.7.2 operation as interval timer (2) ....................................................................................... 273 9.7.3 pulse width measurement operation ............................................................................. 275 9.8 cautions ....................................................................................................................... 278 chapter 10 timer/counter 2 .............................................................................................. 284 10.1 functions .................................................................................................................... 284 10.2 configuration ........................................................................................................... 287 10.3 timer/counter 2 control registers ........................................................... 291 10.4 timer register 2 (tm2) operation ................................................................ 296 10.4.1 basic operation ............................................................................................................... 296 10.4.2 clear operation ................................................................................................................ 299 10.5 external event counter function ............................................................. 301 10.6 one-shot timer function ................................................................................... 304 10.7 compare register, capture/compare register, and capture register operation ........................................................................... 305 10.7.1 compare operations ....................................................................................................... 305 10.7.2 capture operations ......................................................................................................... 307 10.8 basic operation of output control circuit ....................................... 312 10.8.1 basic operation ............................................................................................................... 314 10.8.2 toggle output .................................................................................................................. 314 10.8.3 pwm output ..................................................................................................................... 316 10.8.4 ppg output ...................................................................................................................... 323 10.9 examples of use .................................................................................................... 330 10.9.1 operation as interval timer (1) ....................................................................................... 330 10.9.2 operation as interval timer (2) ....................................................................................... 333 10.9.3 pulse width measurement operation ............................................................................. 336 10.9.4 operation as pwm output .............................................................................................. 339 17 user? manual u11316ej4v1ud 10.9.5 operation as ppg output ............................................................................................... 343 10.9.6 operation as external event counter ............................................................................. 347 10.9.7 operation as one-shot timer ......................................................................................... 349 10.10 cautions ....................................................................................................................... 352 chapter 11 timer 3 .................................................................................................................. 358 11.1 function ....................................................................................................................... 358 11.2 configuration ........................................................................................................... 359 11.3 timer 3 control registers .............................................................................. 361 11.4 timer register 3 (tm3) operation ................................................................ 363 11.4.1 basic operation ............................................................................................................... 363 11.4.2 clear operation ................................................................................................................ 366 11.5 compare register operation .......................................................................... 368 11.6 example of use ....................................................................................................... 369 11.7 cautions ....................................................................................................................... 371 chapter 12 watchdog timer function ....................................................................... 373 12.1 configuration ........................................................................................................... 373 12.2 watchdog timer mode register (wdm) ..................................................... 374 12.3 operation .................................................................................................................... 376 12.3.1 count operation ............................................................................................................... 376 12.3.2 interrupt priorities ............................................................................................................ 376 12.4 cautions ....................................................................................................................... 377 12.4.1 general cautions on use of watchdog timer ............................................................... 377 12.4.2 cautions on pd784038 subseries watchdog timer ................................................... 377 chapter 13 pwm output unit ........................................................................................... 378 13.1 pwm output unit configuration ................................................................... 378 13.2 pwm output unit control registers ........................................................ 379 13.2.1 pwm control register (pwmc) ...................................................................................... 379 13.2.2 pwm prescaler register (pwpr) .................................................................................. 380 13.2.3 pwm modulo registers (pwm0, pwm1) ....................................................................... 380 13.3 pwm output unit operation ............................................................................ 381 13.3.1 basic pwm output operation ......................................................................................... 381 13.3.2 pwm pulse output enabling/disabling .......................................................................... 382 13.3.3 pwm pulse active level specification ........................................................................... 382 13.3.4 pwm pulse width rewrite cycle specification ............................................................. 383 13.4 caution ......................................................................................................................... 384 chapter 14 a/d converter ................................................................................................. 385 14.1 configuration ........................................................................................................... 385 14.2 a/d converter mode register (adm) .......................................................... 389 14.3 operation .................................................................................................................... 392 14.3.1 basic a/d converter operation ....................................................................................... 392 14.3.2 select mode ..................................................................................................................... 396 14.3.3 scan mode ....................................................................................................................... 397 14.3.4 a/d conversion operation start by software ................................................................ 399 14.3.5 a/d conversion operation start by hardware ............................................................... 401 18 user? manual u11316ej4v1ud 14.4 external circuit of a/d converter ........................................................... 404 14.5 cautions ....................................................................................................................... 404 chapter 15 d/a converter ................................................................................................. 406 15.1 configuration ........................................................................................................... 406 15.2 d/a converter mode register (dam) .......................................................... 407 15.3 d/a converter operation .................................................................................. 408 15.3.1 basic operation ............................................................................................................... 408 15.3.2 d/a converter standby operation .................................................................................. 408 15.4 cautions ....................................................................................................................... 409 chapter 16 outline of serial interface ................................................................. 410 chapter 17 asynchronous serial interface/3-wire serial i/o .................... 412 17.1 switching between asynchronous serial interface mode and 3-wire serial i/o mode .............................................................................. 413 17.2 asynchronous serial interface mode ..................................................... 414 17.2.1 configuration in asynchronous serial interface mode .................................................. 414 17.2.2 asynchronous serial interface control registers .......................................................... 417 17.2.3 data format ..................................................................................................................... 421 17.2.4 parity types and operations ........................................................................................... 422 17.2.5 transmission .................................................................................................................... 423 17.2.6 reception ......................................................................................................................... 424 17.2.7 receive errors ................................................................................................................. 425 17.3 3-wire serial i/o mode ........................................................................................ 427 17.3.1 configuration in 3-wire serial i/o mode ........................................................................ 427 17.3.2 clocked serial interface mode registers (csim1, csim2) ........................................... 430 17.3.3 basic operation timing ................................................................................................... 431 17.3.4 operation when transmission only is enabled ............................................................ 433 17.3.5 operation when reception only is enabled .................................................................. 433 17.3.6 operation when transmission/reception is enabled ................................................... 434 17.3.7 corrective action in case of slippage of serial clock and shift operations ............... 435 17.4 baud rate generator ......................................................................................... 435 17.4.1 baud rate generator configuration ............................................................................... 435 17.4.2 baud rate generator control register (brgc, brgc2) ............................................. 437 17.4.3 baud rate generator operation ..................................................................................... 439 17.4.4 baud rate setting in asynchronous serial interface mode .......................................... 441 17.5 cautions ....................................................................................................................... 444 chapter 18 3-wire/2-wire serial i/o mode ................................................................. 446 18.1 functions .................................................................................................................... 446 18.2 configuration ........................................................................................................... 446 18.3 control registers ................................................................................................ 449 18.3.1 clocked serial interface mode register (csim) ............................................................ 449 18.3.2 prescaler mode register for serial clock (sprm) ........................................................ 450 18.3.3 i 2 c bus control register (iicc) ...................................................................................... 451 18.4 3-wire serial i/o mode ........................................................................................ 451 18.4.1 basic operation timing ................................................................................................... 452 19 user? manual u11316ej4v1ud 18.4.2 operation when transmission only is enabled ............................................................ 454 18.4.3 operation when reception only is enabled .................................................................. 454 18.4.4 operation when transmission/reception is enabled ................................................... 455 18.4.5 corrective action in case of slippage of serial clock and shift operations ............... 455 18.5 2-wire serial i/o mode ........................................................................................ 456 18.5.1 basic operation timing ................................................................................................... 457 18.5.2 operation when transmission only is enabled ............................................................ 458 18.5.3 operation when reception only is enabled .................................................................. 458 18.5.4 operation when transmission/reception is enabled ................................................... 459 18.5.5 corrective action in case of slippage of serial clock and shift operations ............... 459 18.6 cautions ....................................................................................................................... 460 chapter 19 i 2 c bus mode ( pd784038y subseries only) ............................................. 463 19.1 outline of functions .......................................................................................... 463 19.2 configuration ........................................................................................................... 464 19.3 control register .................................................................................................. 466 19.3.1 clocked serial interface mode register (csim) ............................................................ 466 19.3.2 i 2 c bus control register (iicc) ...................................................................................... 466 19.3.3 prescaler mode system for serial clock (sprm) ......................................................... 469 19.3.4 slave address register (sva) ........................................................................................ 470 19.4 i 2 c bus mode function ........................................................................................ 471 19.4.1 pin configuration ............................................................................................................. 471 19.4.2 functions .......................................................................................................................... 472 19.5 definition and control method of the i 2 c bus ................................. 473 19.5.1 start condition ................................................................................................................. 473 19.5.2 addresses ......................................................................................................................... 474 19.5.3 transfer direction specification ...................................................................................... 475 19.5.4 acknowledge signal (ack) ............................................................................................. 476 19.5.5 stop condition ................................................................................................................. 477 19.5.6 wait signal (wait) .......................................................................................................... 478 19.5.7 interrupt request (intcsi) generation timing and wait control ................................ 480 19.5.8 interrupt request generation timing ............................................................................. 481 19.5.9 detection method of address match .............................................................................. 481 19.5.10 error detection ................................................................................................................. 481 19.6 timing chart .............................................................................................................. 481 19.7 signal and flags ................................................................................................... 488 chapter 20 clock output function ............................................................................ 489 20.1 configuration ........................................................................................................... 489 20.2 clock output mode register (clom) ......................................................... 491 20.3 operation .................................................................................................................... 492 20.3.1 clock output .................................................................................................................... 492 20.3.2 one-bit output port ......................................................................................................... 493 20.3.3 operation in standby mode ............................................................................................ 493 20.4 cautions ....................................................................................................................... 493 chapter 21 edge detection function ......................................................................... 494 21.1 edge detection function control registers ...................................... 494 20 user? manual u11316ej4v1ud 21.1.1 external interrupt mode registers (intm0, intm1) ...................................................... 494 21.1.2 sampling clock selection register (scs0) ................................................................... 497 21.2 edge detection for pins p20, p25 and p26 ............................................ 498 21.3 edge detection for pin p21 ............................................................................ 499 21.4 edge detection for pins p22 to p24 ......................................................... 500 21.5 cautions ....................................................................................................................... 501 chapter 22 interrupt functions ................................................................................... 502 22.1 interrupt request sources ............................................................................ 502 22.1.1 software interrupts .......................................................................................................... 504 22.1.2 operand error interrupts ................................................................................................. 504 22.1.3 non-maskable interrupts ................................................................................................. 504 22.1.4 maskable interrupts ......................................................................................................... 504 22.2 interrupt service modes .................................................................................. 505 22.2.1 vectored interrupt service ............................................................................................... 505 22.2.2 macro service .................................................................................................................. 505 22.2.3 context switching ............................................................................................................ 505 22.3 interrupt service control registers ...................................................... 506 22.3.1 interrupt control registers .............................................................................................. 508 22.3.2 interrupt mask registers (mk0/mk1l) ........................................................................... 512 22.3.3 in-service priority register (ispr) ................................................................................. 513 22.3.4 interrupt mode control register (imc) ........................................................................... 514 22.3.5 watchdog timer mode register (wdm) ........................................................................ 515 22.3.6 program status word (psw) .......................................................................................... 516 22.4 software interrupt acknowledgment operations ........................... 516 22.4.1 brk instruction software interrupt acknowledgment operation .................................. 516 22.4.2 brkcs instruction software interrupt (software context switching) acknowledgment operation ............................................................................................ 517 22.5 operand error interrupt acknowledgment operation ................ 518 22.6 non-maskable interrupt acknowledgment operation .................... 519 22.7 maskable interrupt acknowledgment operation ............................. 523 22.7.1 vectored interruption ....................................................................................................... 525 22.7.2 context switching ............................................................................................................ 525 22.7.3 maskable interrupt priority levels .................................................................................. 527 22.8 macro service function .................................................................................... 533 22.8.1 outline of macro service function ................................................................................. 533 22.8.2 types of macro service ................................................................................................... 533 22.8.3 basic macro service operation ...................................................................................... 536 22.8.4 operation at end of macro service ................................................................................ 537 22.8.5 macro service control registers .................................................................................... 540 22.8.6 macro service type a ..................................................................................................... 543 22.8.7 macro service type b ..................................................................................................... 548 22.8.8 macro service type c ..................................................................................................... 552 22.8.9 counter mode .................................................................................................................. 565 22.9 when interrupt requests and macro service are temporarily held pending ................................................................................ 567 22.10 instructions whose execution is temporarily suspended by an interrupt or macro service ................................... 569 21 user? manual u11316ej4v1ud 22.11 interrupt and macro service operation timing ................................ 569 22.11.1 interrupt acknowledge processing time ........................................................................ 570 22.11.2 processing time of macro service ................................................................................. 571 22.12 restoring interrupt function to initial state .................................. 572 22.13 cautions ....................................................................................................................... 573 chapter 23 local bus interface function ............................................................. 575 23.1 memory extension function ............................................................................ 575 23.1.1 memory extension mode register (mm) ........................................................................ 575 23.1.2 memory map with external memory extension .............................................................. 577 23.1.3 basic operation of local bus interface .......................................................................... 587 23.2 wait function ........................................................................................................... 588 23.2.1 wait function control registers ..................................................................................... 588 23.2.2 address waits .................................................................................................................. 591 23.2.3 access waits .................................................................................................................... 594 23.3 pseudo-static ram refresh function ........................................................ 601 23.3.1 control registers ............................................................................................................. 602 23.3.2 operations ........................................................................................................................ 603 23.4 bus hold function ................................................................................................. 607 23.4.1 hold mode register (hldm) ........................................................................................... 607 23.4.2 operation .......................................................................................................................... 608 23.5 cautions ....................................................................................................................... 609 chapter 24 standby function ......................................................................................... 610 24.1 configuration and function ........................................................................... 610 24.2 control registers ................................................................................................ 612 24.2.1 standby control register (stbc) ................................................................................... 612 24.2.2 oscillation stabilization time specification register (osts) ....................................... 614 24.3 halt mode ................................................................................................................... 615 24.3.1 halt mode setting and operating states ..................................................................... 615 24.3.2 halt mode release ....................................................................................................... 615 24.4 stop mode .................................................................................................................. 623 24.4.1 stop mode setting and operating states .................................................................... 623 24.4.2 stop mode release ....................................................................................................... 624 24.5 idle mode .................................................................................................................... 629 24.5.1 idle mode setting and operating states ...................................................................... 629 24.5.2 idle mode release ......................................................................................................... 630 24.6 check items when stop mode/idle mode is used .............................. 634 24.7 cautions ....................................................................................................................... 636 chapter 25 reset function ............................................................................................... 637 25.1 reset function ........................................................................................................ 637 25.2 caution ......................................................................................................................... 642 chapter 26 pd78p4038 programming ........................................................................... 643 26.1 operating modes .................................................................................................... 643 26.2 prom write procedure ....................................................................................... 645 26.3 prom reading procedure .................................................................................. 649 22 user? manual u11316ej4v1ud 26.4 screening of one-time prom product ...................................................... 649 26.5 cautions ....................................................................................................................... 649 chapter 27 instruction operations ............................................................................. 650 27.1 legend ........................................................................................................................... 650 27.2 list of operations ................................................................................................ 653 27.3 instructions listed by type of addressing ......................................... 678 chapter 28 electrical specifications ........................................................................ 684 chapter 29 package drawings ....................................................................................... 711 chapter 30 recommended soldering conditions ................................................. 714 appendix a differences with pd784026 subseries ............................................. 716 appendix b development tools ...................................................................................... 719 b.1 language processing software ................................................................... 722 b.2 prom writing tools ............................................................................................. 724 b.3 debugging tools .................................................................................................... 725 b.3.1 hardware .......................................................................................................................... 725 b.3.2 software ........................................................................................................................... 727 b.4 cautions on designing target system ..................................................... 728 b.5 conversion socket (ev-9200gc-80) and conversion adapter (tgk-080sdw) ........................................................................................... 731 appendix c embedded software ...................................................................................... 734 appendix d register index ................................................................................................. 735 d.1 register index (register name) ........................................................................ 735 d.2 register index (register symbol) ................................................................... 737 appendix e revision history .............................................................................................. 739 23 user? manual u11316ej4v1ud 2-1 pin input/output circuits ...................................................................................................... 68 3-1 pd784031 memory map .................................................................................................... 72 3-2 pd784035 memory map .................................................................................................... 73 3-3 pd784036 memory map .................................................................................................... 74 3-4 pd784037 memory map .................................................................................................... 75 3-5 pd784038 memory map .................................................................................................... 76 3-6 internal ram memory map .................................................................................................. 81 3-7 internal memory size switching register (ims) format .................................................... 83 3-8 program counter (pc) format ............................................................................................ 84 3-9 program status word (psw) format .................................................................................. 84 3-10 stack pointer (sp) format ................................................................................................... 89 3-11 data saved to stack area ................................................................................................... 90 3-12 data restored from stack area .......................................................................................... 91 3-13 general-purpose register format ...................................................................................... 92 3-14 general-purpose register addresses ................................................................................. 93 4-1 clock generator block diagram .......................................................................................... 104 4-2 clock oscillator external circuitry ....................................................................................... 105 4-3 standby control register (stbc) format .......................................................................... 106 4-4 oscillation stabilization time specification register (osts) format ............................... 107 4-5 signal extraction with external clock input ........................................................................ 109 4-6 cautions on resonator connection .................................................................................... 110 4-7 incorrect example of resonator connection ...................................................................... 111 5-1 port configuration ................................................................................................................ 113 5-2 port 0 block diagram ........................................................................................................... 115 5-3 port 0 mode register (pm0) format ................................................................................... 116 5-4 port specified as output port .............................................................................................. 116 5-5 port specified as input port ................................................................................................. 117 5-6 pull-up resistor option register (puo) format ................................................................ 118 5-7 pull-up resistor specification (port 0) ............................................................................... 118 5-8 example of transistor drive ................................................................................................ 119 5-9 block diagram of p10 and p11 (port 1) ............................................................................. 121 5-10 block diagram of p12 (port 1) ............................................................................................ 122 5-11 block diagram of p13 (port 1) ............................................................................................ 123 5-12 block diagram of p14 (port 1) ............................................................................................ 124 5-13 block diagram of p15 to p17 (port 1) ................................................................................ 125 5-14 port 1 mode register (pm1) format ................................................................................... 126 5-15 port 1 mode control register (pmc1) format ................................................................... 126 5-16 port specified as output port .............................................................................................. 127 5-17 port specified as input port ................................................................................................. 127 5-18 control specification ............................................................................................................ 128 list of figures (1/12) figure no. title page 24 user? manual u11316ej4v1ud 5-19 pull-up resistor option register (puo) format ................................................................ 129 5-20 pull-up resistor specification (port 1) ............................................................................... 129 5-21 example of direct led drive ............................................................................................... 130 5-22 block diagram of p20 to p24, p26 and p27 (port 2) ........................................................ 132 5-23 block diagram of p25 (port 2) ............................................................................................ 133 5-24 port specified as input port ................................................................................................. 134 5-25 pull-up resistor option register (puo) format ................................................................ 134 5-26 pull-up specification (port 2) .............................................................................................. 135 5-27 block diagram of p30 (port 3) ............................................................................................ 137 5-28 block diagram of p31 and p34 to p37 (port 3) ................................................................. 138 5-29 block diagram of p32 (port 3) ............................................................................................ 139 5-30 block diagram of p33 (port 3) ............................................................................................ 140 5-31 port 3 mode register (pm3) format ................................................................................... 141 5-32 port 3 mode control register (pmc3) format ................................................................... 141 5-33 port specified as output port .............................................................................................. 142 5-34 port specified as input port ................................................................................................. 142 5-35 control specification ............................................................................................................ 143 5-36 pull-up resistor option register (puo) format ................................................................ 144 5-37 pull-up specification (port 3) .............................................................................................. 144 5-38 port 4 block diagram ........................................................................................................... 146 5-39 port 4 mode register (pm4) format ................................................................................... 147 5-40 port specified as output port .............................................................................................. 148 5-41 port specified as input port ................................................................................................. 149 5-42 pull-up resistor option register (puo) format ................................................................ 150 5-43 pull-up specification (port 4) .............................................................................................. 150 5-44 example of direct led drive ............................................................................................... 151 5-45 port 5 block diagram ........................................................................................................... 152 5-46 port 5 mode register (pm5) format ................................................................................... 153 5-47 port specified as output port .............................................................................................. 154 5-48 port specified as input port ................................................................................................. 155 5-49 pull-up resistor option register (puo) format ................................................................ 156 5-50 pull-up specification (port 5) .............................................................................................. 156 5-51 example of direct led drive ............................................................................................... 157 5-52 block diagram of p60 to p63 (port 6) ................................................................................ 160 5-53 block diagram of p64 and p65 (port 6) ............................................................................. 161 5-54 block diagram of p66 (port 6) ............................................................................................ 162 5-55 block diagram of p67 (port 6) ............................................................................................ 163 5-56 port 6 mode register (pm6) format ................................................................................... 165 5-57 port specified as output port .............................................................................................. 165 5-58 port specified as input port ................................................................................................. 166 5-59 pull-up resistor option register (puo) format ................................................................ 167 5-60 pull-up specification (port 6) .............................................................................................. 167 list of figures (2/12) figure no. title page 25 user? manual u11316ej4v1ud 5-61 port 7 block diagram ........................................................................................................... 168 5-62 port 7 mode register (pm7) format ................................................................................... 169 5-63 port specified as output port .............................................................................................. 169 5-64 port specified as input port ................................................................................................. 170 6-1 real-time output port block diagram ................................................................................ 174 6-2 real-time output port control register (rtpc) format .................................................. 175 6-3 port 0 buffer register (p0h, p0l) configuration ............................................................... 176 6-4 real-time output port operation timing ........................................................................... 179 6-5 real-time output port operation timing (2-channel independent control example) .... 180 6-6 real-time output port operation timing ........................................................................... 181 6-7 real-time output function control register settings ....................................................... 182 6-8 real-time output function setting procedure ................................................................... 182 6-9 interrupt request servicing when real-time output function is used ........................... 183 7-1 timer/counter block diagram ............................................................................................. 185 8-1 timer/counter 0 block diagram .......................................................................................... 190 8-2 timer control register 0 (tmc0) format ........................................................................... 193 8-3 prescaler mode register 0 (prm0) format ....................................................................... 194 8-4 capture/compare control register 0 (crc0) format ....................................................... 195 8-5 timer output control register (toc) format .................................................................... 196 8-6 one-shot pulse output control register (ospc) format ................................................. 197 8-7 basic operation of timer register 0 (tm0) ........................................................................ 199 8-8 tm0 clearance by match with compare register (cr01) ................................................ 200 8-9 clear operation when ce0 bit is cleared (0) .................................................................... 201 8-10 timer/counter 0 external event count timing ................................................................... 202 8-11 example of the case where the external event counter does not distinguish between one valid edge input and no valid edge input .............................. 203 8-12 methods of enabling the external event counter to distinguish no valid edge input .... 204 8-13 compare operation .............................................................................................................. 205 8-14 tm0 clearance after match detection ................................................................................ 206 8-15 capture operation ................................................................................................................ 207 8-16 toggle output operation ..................................................................................................... 210 8-17 pwm pulse output ............................................................................................................... 211 8-18 example of pwm output using tm0 .................................................................................. 212 8-19 example of pwm output when cr00 = ffffh ................................................................ 213 8-20 example of compare register (cr00) rewrite .................................................................. 214 8-21 example of 100% duty with pwm output ......................................................................... 215 8-22 when timer/counter 0 is stopped during pwm signal output ........................................ 216 8-23 example of ppg output using tm0 ................................................................................... 217 8-24 example of ppg output when cr00 = cr01 ................................................................... 218 8-25 example of compare register (cr00) rewrite ................................................................ 219 list of figures (3/12) figure no. title page 26 user? manual u11316ej4v1ud 8-26 example of 100% duty with ppg output .......................................................................... 220 8-27 example of extended ppg output cycle ........................................................................... 221 8-28 when timer/counter 0 is stopped during ppg signal output ......................................... 222 8-29 example of software triggered one-shot pulse output ................................................... 223 8-30 interval timer operation (1) timing .................................................................................... 224 8-31 control register settings for interval timer operation (1) ................................................ 225 8-32 interval timer operation (1) setting procedure ................................................................. 225 8-33 interval timer operation (1) interrupt request servicing .................................................. 225 8-34 interval timer operation (2) timing .................................................................................... 226 8-35 control register settings for interval timer operation (2) ................................................ 227 8-36 interval timer operation (2) setting procedure ................................................................. 227 8-37 pulse width measurement timing ...................................................................................... 228 8-38 control register settings for pulse width measurement .................................................. 229 8-39 pulse width measurement setting procedure .................................................................... 229 8-40 interrupt request servicing that calculates pulse width .................................................. 230 8-41 example of timer/counter 0 pwm signal output .............................................................. 230 8-42 control register settings for pwm output operation ....................................................... 231 8-43 pwm output setting procedure .......................................................................................... 232 8-44 changing pwm output duty ............................................................................................... 233 8-45 example of timer/counter 0 ppg signal output ............................................................... 234 8-46 control register settings for ppg output operation ......................................................... 235 8-47 ppg output setting procedure ........................................................................................... 236 8-48 changing ppg output duty ................................................................................................ 237 8-49 example of timer/counter 0 one-shot pulse output ........................................................ 238 8-50 control register settings for one-shot pulse output ....................................................... 239 8-51 one-shot pulse output setting procedure ......................................................................... 240 8-52 operation when counting is started .................................................................................. 242 8-53 example of the case where the external event counter does not distinguish between one valid edge input and no valid edge input ................................................. 243 8-54 to distinguish whether one or no valid edge has been input with external event counter ................................................................................................ 244 9-1 timer/counter 1 block diagram .......................................................................................... 249 9-2 timer control register 1 (tmc1) format ........................................................................... 252 9-3 prescaler mode register 1 (prm1) format ....................................................................... 253 9-4 capture/compare control register 1 (crc1) format ....................................................... 254 9-5 example of generation of unnecessary interrupt request by compare register ........... 255 9-6 basic operation in 8-bit operating mode (bw1 = 0) ......................................................... 257 9-7 basic operation in 16-bit operating mode (bw1 = 1) ....................................................... 258 9-8 tm1 clearance by match with compare register (cr10, cr11) .................................... 259 9-9 tm1 clearance after capture operation ............................................................................ 259 9-10 clear operation when ce1 bit is cleared (0) .................................................................... 260 9-11 timer/counter 1 external event count timing ................................................................... 261 list of figures (4/12) figure no. title page 27 user? manual u11316ej4v1ud 9-12 example of the case where the external event counter does not distinguish between one valid edge input and no valid edge input ................................................. 262 9-13 methods of enabling the external event counter to distinguish no valid edge input .... 263 9-14 compare operation in 8-bit operating mode ..................................................................... 264 9-15 compare operation in 16-bit operating mode ................................................................... 265 9-16 tm1 clearance after match detection ................................................................................ 265 9-17 capture operation in 8-bit operating mode ....................................................................... 266 9-18 capture operation in 16-bit operating mode ..................................................................... 267 9-19 tm1 clearance after capture operation ............................................................................ 268 9-20 example of generation of unnecessary interrupt request by compare register ........... 269 9-21 interval timer operation (1) timing .................................................................................... 270 9-22 control register settings for interval timer operation (1) ................................................ 271 9-23 interval timer operation (1) setting procedure ................................................................. 272 9-24 interval timer operation (1) interrupt request servicing .................................................. 272 9-25 interval timer operation (2) timing (when cr11 is used as compare register) .......... 273 9-26 control register settings for interval timer operation (2) ................................................ 274 9-27 interval timer operation (2) setting procedure ................................................................. 274 9-28 pulse width measurement timing (when cr11 is used as capture register) .............. 275 9-29 control register settings for pulse width measurement .................................................. 276 9-30 pulse width measurement setting procedure .................................................................... 277 9-31 interrupt request servicing that calculates pulse width .................................................. 277 9-32 operation when counting is started .................................................................................. 279 9-33 example of the case where the external event counter does not distinguish between one valid edge input and no valid edge input ................................................. 280 9-34 to distinguish whether one or no valid edge has been input with external event counter ................................................................................................ 281 9-35 example of generation of unnecessary interrupt request by compare register ........... 282 10-1 timer/counter 2 block diagram .......................................................................................... 288 10-2 timer control register 1 (tmc1) format ........................................................................... 291 10-3 prescaler mode register 1 (prm1) format ....................................................................... 292 10-4 capture/compare control register 2 (crc2) format ....................................................... 293 10-5 example of generation of unnecessary interrupt request by compare register ........... 294 10-6 timer output control register (toc) format .................................................................... 295 10-7 basic operation in 8-bit operating mode (bw2 = 0) ......................................................... 297 10-8 basic operation in 16-bit operating mode (bw2 = 1) ....................................................... 298 10-9 tm2 clearance by match with compare register (cr20/cr21) ..................................... 299 10-10 tm2 clearance after capture operation ............................................................................ 299 10-11 clear operation when ce2 bit is cleared (to 0) ............................................................... 300 10-12 timer/counter 2 external event count timing ................................................................... 301 10-13 example of the case where the external event counter does not distinguish between one valid edge input and no valid edge input .............................. 302 10-14 methods of enabling the external event counter to distinguish no valid edge input .... 303 list of figures (5/12) figure no. title page 28 user? manual u11316ej4v1ud 10-15 one-shot timer operation .................................................................................................. 304 10-16 compare operation in 8-bit operating mode ..................................................................... 305 10-17 compare operation in 16-bit operating mode ................................................................... 306 10-18 tm2 clearance after match detection ................................................................................ 307 10-19 capture operation in 8-bit operating mode ....................................................................... 308 10-20 capture operation in 16-bit operating mode ..................................................................... 309 10-21 tm2 clearance after capture operation ............................................................................ 310 10-22 example of generation of unnecessary interrupt request by compare register ........... 311 10-23 toggle output operation ..................................................................................................... 314 10-24 pwm pulse output (bw2 = 0) ............................................................................................ 317 10-25 pwm pulse output (bw2 = 1) ............................................................................................ 318 10-26 example of pwm output using tm2w ............................................................................... 319 10-27 example of pwm output when cr20w = ffffh ............................................................ 319 10-28 example of compare register (cr20w) rewrite .............................................................. 320 10-29 example of 100% duty with pwm output ......................................................................... 321 10-30 when timer/counter 2 is stopped during pwm signal output ........................................ 322 10-31 example of ppg output using tm2 ................................................................................... 324 10-32 example of ppg output when cr20 = cr21 ................................................................... 325 10-33 example of compare register rewrite ............................................................................... 326 10-34 example of 100% duty with ppg output .......................................................................... 327 10-35 example of extended ppg output cycle ........................................................................... 328 10-36 when timer/counter 2 is stopped during ppg signal output ......................................... 329 10-37 interval timer operation (1) timing .................................................................................... 330 10-38 control register settings for interval timer operation (1) ................................................ 331 10-39 interval timer operation (1) setting procedure ................................................................. 332 10-40 interval timer operation (1) interrupt request servicing .................................................. 332 10-41 interval timer operation (2) timing .................................................................................... 333 10-42 control register settings for interval timer operation (2) ................................................ 334 10-43 interval timer operation (2) setting procedure ................................................................. 335 10-44 pulse width measurement timing ...................................................................................... 336 10-45 control register settings for pulse width measurement .................................................. 337 10-46 pulse width measurement setting procedure .................................................................... 338 10-47 interrupt request servicing that calculates pulse width .................................................. 338 10-48 example of timer/counter 2 pwm signal output .............................................................. 339 10-49 control register settings for pwm output operation ....................................................... 340 10-50 pwm output setting procedure .......................................................................................... 341 10-51 changing pwm output duty ............................................................................................... 342 10-52 example of timer/counter 2 ppg signal output ............................................................... 343 10-53 control register settings for ppg output operation ......................................................... 344 10-54 ppg output setting procedure ........................................................................................... 345 10-55 changing ppg output duty ................................................................................................ 346 10-56 external event counter operation (single edge) .............................................................. 347 10-57 control register settings for external event counter operation ...................................... 348 list of figures (6/12) figure no. title page 29 user? manual u11316ej4v1ud 10-58 external event counter operation setting procedure ....................................................... 348 10-59 one-shot timer operation .................................................................................................. 349 10-60 control register settings for one-shot timer operation .................................................. 350 10-61 one-shot timer operation setting procedure ................................................................... 351 10-62 one-shot timer operation start procedure from second time onward ......................... 351 10-63 operation when counting is started .................................................................................. 353 10-64 example where whether one or no valid edge has been input cannot be distinguished with external event counter ...................................................... 354 10-65 to distinguish whether one or no valid edge has been input with external event counter ................................................................................................ 355 10-66 example of generation of unnecessary interrupt request by compare register ........... 356 11-1 timer 3 block diagram ........................................................................................................ 359 11-2 timer control register 0 (tmc0) format ........................................................................... 361 11-3 prescaler mode register 0 (prm0) format ....................................................................... 362 11-4 basic operation in 8-bit operating mode (bw3 = 0) ......................................................... 364 11-5 basic operation in 16-bit operating mode (bw3 = 1) ....................................................... 365 11-6 tm3 clearance by match with compare register (cr30) ................................................ 366 11-7 clear operation when ce3 bit is cleared (to 0) ............................................................... 367 11-8 compare operation .............................................................................................................. 368 11-9 interval timer operation timing .......................................................................................... 369 11-10 control register settings for interval timer operation ...................................................... 370 11-11 interval timer operation setting procedure ....................................................................... 370 11-12 operation when count starts ............................................................................................. 372 12-1 watchdog timer block diagram .......................................................................................... 373 12-2 watchdog timer mode register (wdm) format ................................................................ 375 13-1 pwm output unit configuration .......................................................................................... 378 13-2 pwm control register (pwmc) format ............................................................................. 379 13-3 pwm prescaler register (pwpr) format .......................................................................... 380 13-4 basic pwm output operation ............................................................................................. 381 13-5 pwm output active level setting ....................................................................................... 382 13-6 pwm output timing example 1 (pwm pulse width rewrite cycle = 2 12 /f pwmc ) ............ 383 13-7 pwm output timing example 2 (pwm pulse width rewrite cycle = 2 8 /f pwmc ) .............. 384 14-1 a/d converter block diagram ............................................................................................. 386 14-2 example of capacitor connection on a/d converter pins ................................................ 387 14-3 a/d converter mode register (adm) format ..................................................................... 390 14-4 basic a/d converter operation ........................................................................................... 393 14-5 relationship between analog input voltage and a/d conversion result ........................ 394 14-6 select mode operation timing ............................................................................................ 396 14-7 scan mode 0 operation timing ........................................................................................... 397 list of figures (7/12) figure no. title page 30 user? manual u11316ej4v1ud 14-8 scan mode 1 operation timing ........................................................................................... 398 14-9 software start select mode a/d conversion operation .................................................... 399 14-10 software start scan mode a/d conversion operation ...................................................... 400 14-11 hardware start select mode a/d conversion operation ................................................... 402 14-12 hardware start scan mode a/d conversion operation ..................................................... 403 14-13 example of capacitor connection on a/d converter pins ................................................ 405 15-1 d/a converter block diagram ............................................................................................. 406 15-2 d/a converter mode register (dam) format ..................................................................... 407 15-3 example of connecting capacitors to reference voltage input pins of d/a converter .. 408 15-4 example of buffer amp insertion ........................................................................................ 409 16-1 example of serial interface ................................................................................................. 411 17-1 switching between asynchronous serial interface mode and 3-wire serial i/o mode ... 413 17-2 asynchronous serial interface block diagram ................................................................... 415 17-3 format of asynchronous serial interface mode register (asim) and asynchronous serial interface mode register 2 (asim2) ................................................. 418 17-4 format of asynchronous serial interface status register (asis) and asynchronous serial interface status register 2 (asis2) ................................................ 420 17-5 asynchronous serial interface transmit/receive data format ......................................... 421 17-6 asynchronous serial interface transmission completion interrupt timing ...................... 423 17-7 asynchronous serial interface reception completion interrupt timing ........................... 424 17-8 receive error timing ........................................................................................................... 425 17-9 example of 3-wire serial i/o system configuration .......................................................... 427 17-10 3-wire serial i/o mode block diagram ............................................................................... 428 17-11 format of clocked serial interface mode register 1 (csim1) and clocked serial interface mode register 2 (csim2) ........................................................... 430 17-12 3-wire serial i/o mode timing ............................................................................................ 431 17-13 example of connection to 2-wire serial i/o ....................................................................... 432 17-14 baud rate generator block diagram ................................................................................. 436 17-15 baud rate generator control register (brgc) format and baud rate generator control register 2 (brgc2) format .............................................. 438 18-1 block diagram of clocked serial interface (in 3-wire/2-wire serial mode) ....................... 447 18-2 clocked serial interface mode register (csim) format ................................................... 449 18-3 format of prescaler mode register (sprm) for serial clock ........................................... 450 18-4 format of i 2 c bus control register (iicc) ......................................................................... 451 18-5 example of 3-wire serial i/o system configuration .......................................................... 451 18-6 3-wire serial i/o mode timing ............................................................................................ 452 18-7 example of configuration of 2-wire serial i/o system ...................................................... 456 18-8 timing in 2-wire serial i/o mode ........................................................................................ 457 list of figures (8/12) figure no. title page 31 user? manual u11316ej4v1ud 19-1 example of serial bus configuration using i 2 c bus ......................................................... 463 19-2 block diagram of clock-synchronous serial interface (in i 2 c bus mode) ....................... 464 19-3 clocked serial interface mode register (csim) format ................................................... 466 19-4 i 2 c bus control register (iicc) format ............................................................................. 467 19-5 prescaler mode register for serial clock (sprm) format ............................................... 469 19-6 slave address register (sva) format ............................................................................... 470 19-7 pin configuration .................................................................................................................. 471 19-8 serial data transfer timing on i 2 c bus ............................................................................. 473 19-9 start condition ...................................................................................................................... 473 19-10 address ............................................................................................................................... .. 474 19-11 transfer direction specification .......................................................................................... 475 19-12 acknowledge signal ............................................................................................................. 476 19-13 stop condition ...................................................................................................................... 477 19-14 wait signal ........................................................................................................................... 478 19-15 example of communication from master to slave (with 9-clock wait selected for both master and slave. slave: wup = 0) ........................ 482 19-16 example of communication from slave to master (when selecting the 9th clock wait both master and slave) .............................................. 485 20-1 clock output function configuration .................................................................................. 489 20-2 clock output mode register (clom) format .................................................................... 491 20-3 clock output operation timing ........................................................................................... 492 20-4 one-bit output port operation ............................................................................................ 493 21-1 external interrupt mode register 0 (intm0) format ......................................................... 495 21-2 external interrupt mode register 1 (intm1) format ......................................................... 496 21-3 sampling clock selection register (scs0) format ........................................................... 497 21-4 edge detection for pins p20, p25 and p26 ....................................................................... 498 21-5 p21 pin edge detection ....................................................................................................... 499 21-6 edge detection for pins p22 to p24 ................................................................................... 500 22-1 interrupt control registers ( icn) ..................................................................................... 509 22-2 interrupt mask register (mk0, mk1l) format .................................................................... 512 22-3 in-service priority register (ispr) format ......................................................................... 513 22-4 interrupt mode control register (imc) format ................................................................... 514 22-5 watchdog timer mode register (wdm) format ................................................................ 515 22-6 program status word (pswl) format ............................................................................... 516 22-7 context switching operation by execution of a brkcs instruction ................................. 517 22-8 return from brkcs instruction software interrupt (retcsb instruction operation) ..... 518 22-9 non-maskable interrupt request acknowledgment operations ........................................ 520 22-10 interrupt acknowledgment processing algorithm ............................................................... 524 22-11 context switching operation by generation of an interrupt request ............................... 525 22-12 return from interrupt that uses context switching by means of retcs instruction ...... 526 list of figures (9/12) figure no. title page 32 user? manual u11316ej4v1ud 22-13 examples of servicing when another interrupt request is generated during interrupt service ....................................................................................................... 528 22-14 examples of servicing of simultaneously generated interrupts ....................................... 531 22-15 differences in level 3 interrupt acknowledgment according to imc register setting .... 532 22-16 differences between vectored interrupt and macro service processing .......................... 533 22-17 macro service processing sequence ................................................................................. 536 22-18 operation at end of macro service when vcie = 0 .......................................................... 538 22-19 operation at end of macro service when vcie = 1 .......................................................... 539 22-20 macro service control word format .................................................................................. 540 22-21 macro service mode register format ................................................................................ 541 22-22 macro service data transfer processing flow (type a) ................................................... 544 22-23 type a macro service channel ........................................................................................... 546 22-24 asynchronous serial reception .......................................................................................... 547 22-25 macro service data transfer processing flow (type b) ................................................... 549 22-26 type b macro service channel ........................................................................................... 550 22-27 parallel data input synchronized with external interrupts ................................................ 551 22-28 parallel data input timing ................................................................................................... 552 22-29 macro service data transfer processing flow (type c) .................................................. 553 22-30 type c macro service channel .......................................................................................... 555 22-31 stepping motor open loop control by real-time output port ......................................... 557 22-32 data transfer control timing .............................................................................................. 558 22-33 single-phase excitation of 4-phase stepping motor ......................................................... 560 22-34 1-2-phase excitation of 4-phase stepping motor .............................................................. 560 22-35 automatic addition control + ring control block diagram 1 (when output timing varies with 1-2-phase excitation) ................................................... 561 22-36 automatic addition control + ring control timing diagram 1 (when output timing varies with 1-2-phase excitation) ................................................... 562 22-37 automatic addition control + ring control block diagram 2 (1-2-phase excitation constant-velocity operation) .......................................................... 563 22-38 automatic addition control + ring control timing diagram 2 (1-2-phase excitation constant-velocity operation) .......................................................... 564 22-39 macro service data transfer processing flow (counter mode) ....................................... 565 22-40 counter mode ....................................................................................................................... 566 22-41 counting number of edges ................................................................................................. 566 22-42 interrupt request generation and acknowledgment (unit: clock = 1/f clk ) ...................... 569 23-1 memory extension mode register (mm) format ................................................................ 576 23-2 pd784035 memory map .................................................................................................... 577 23-3 pd784036 memory map .................................................................................................... 579 23-4 pd784037 memory map .................................................................................................... 581 23-5 pd784038 memory map .................................................................................................... 583 23-6 pd784031 memory map .................................................................................................... 585 23-7 read timing ......................................................................................................................... 587 list of figures (10/12) figure no. title page 33 user? manual u11316ej4v1ud 23-8 write timing ......................................................................................................................... 587 23-9 memory extension mode register (mm) format ................................................................ 588 23-10 programmable wait control register (pwc1/pwc2) format ........................................... 590 23-11 address wait function read/write timing ......................................................................... 591 23-12 wait control spaces ............................................................................................................ 595 23-13 access wait function read timing .................................................................................... 596 23-14 access wait function write timing .................................................................................... 598 23-15 timing with external wait signal ......................................................................................... 600 23-16 refresh mode register (rfm) format ............................................................................... 602 23-17 refresh area specification register (rfa) format ........................................................... 603 23-18 pulse refresh operation in internal memory access ........................................................ 604 23-19 refresh pulse output operation ......................................................................................... 605 23-20 timing for return from self-refresh operation .................................................................. 606 23-21 hold mode register (hldm) format .................................................................................. 607 23-22 hold mode timing ................................................................................................................ 609 24-1 standby mode transition diagram ...................................................................................... 610 24-2 standby function block diagram ........................................................................................ 611 24-3 standby control register (stbc) format .......................................................................... 613 24-4 oscillation stabilization time specification register (osts) format ............................... 614 24-5 operation after halt mode release .................................................................................. 617 24-6 operation after stop mode release ................................................................................. 625 24-7 stop mode release by nmi input ..................................................................................... 627 24-8 stop mode release by intp4/intp5 input ..................................................................... 628 24-9 operation after idle mode release ................................................................................... 631 24-10 example of address/data bus processing ......................................................................... 635 25-1 reset signal acknowledgment ............................................................................................ 637 25-2 power-on reset operation ................................................................................................. 638 25-3 reset input timing ............................................................................................................... 641 26-1 page program mode flowchart ........................................................................................... 645 26-2 page program mode timing ................................................................................................ 646 26-3 byte program mode flowchart ............................................................................................ 647 26-4 byte program mode timing ................................................................................................. 648 26-5 prom read timing ............................................................................................................. 649 28-1 power supply voltage and clock cycle time .................................................................... 685 b-1 development tool configuration ......................................................................................... 720 b-2 distance between in-circuit emulator and conversion socket ......................................... 728 b-3 target system connection conditions (1) .......................................................................... 729 b-4 target system connection conditions (2) .......................................................................... 730 list of figures (11/12) figure no. title page 34 user? manual u11316ej4v1ud list of figures (12/12) figure no. title page b-5 package drawing of ev-9200gc-80 (reference) .............................................................. 731 b-6 recommended board installation pattern of ev-9200gc-80 (reference) ....................... 732 b-7 tgk-080sdw package drawing (reference) .................................................................... 733 35 user? manual u11316ej4v1ud 2-1 port 1 operating modes ....................................................................................................... 58 2-2 port 2 operating modes ....................................................................................................... 59 2-3 port 3 operating modes (n = 0 to 7) ................................................................................... 60 2-4 port 6 operating modes ....................................................................................................... 62 2-5 pin input/output circuit types and recommended connection when not used ........... 66 3-1 vector table ......................................................................................................................... 79 3-2 internal ram area ................................................................................................................ 80 3-3 register bank selection ...................................................................................................... 86 3-4 correspondence between function names and absolute names .................................... 96 3-5 list of special function registers (sfrs) .......................................................................... 98 3-6 limits of reading timer register ........................................................................................ 103 4-1 time required to change division ratio ........................................................................... 108 5-1 port functions ...................................................................................................................... 114 5-2 number of input/output ports ............................................................................................. 114 5-3 port 1 operating modes ....................................................................................................... 120 5-4 method of setting p10 & p11 pwm signal output function ............................................ 126 5-5 port 2 operating modes ....................................................................................................... 131 5-6 port 3 operating modes ....................................................................................................... 136 5-7 port 4 operating modes ....................................................................................................... 145 5-8 port 4 operating modes ....................................................................................................... 147 5-9 port 5 operating modes ....................................................................................................... 151 5-10 port 5 operating modes ....................................................................................................... 153 5-11 port 6 operating modes ....................................................................................................... 158 5-12 p60 to p65 control pin specification .................................................................................. 159 5-13 port 6 operating modes ....................................................................................................... 164 5-14 p60 to p65 control pin specification .................................................................................. 164 6-1 operations when port 0 and port 0 buffer registers (p0h, p0l) are manipulated ........ 176 6-2 real-time output port output triggers (when p0mh = p0ml = 1) ................................ 178 8-1 timer/counter 0 interval time ............................................................................................. 186 8-2 timer/counter 0 programmable square-wave output setting range ............................. 187 8-3 timer/counter 0 pulse width measurement range ........................................................... 188 8-4 timer/counter 0 pulse width measurement time ............................................................. 189 8-5 limits of reading timer register ........................................................................................ 191 8-6 timer output (to0/to1) operations .................................................................................. 209 8-7 to0, to1 toggle output (f xx = 32 mhz) ............................................................................ 211 8-8 to0, to1 pwm cycle (f xx = 32 mhz) ................................................................................ 212 8-9 to0 ppg output (f xx = 32 mhz) ......................................................................................... 218 8-10 limits of reading timer register ........................................................................................ 243 list of tables (1/3) table no. title page 36 user? manual u11316ej4v1ud 9-1 timer/counter 1 intervals .................................................................................................... 246 9-2 timer/counter 1 pulse width measurement range ........................................................... 247 9-3 timer/counter 1 pulse width measurement time ............................................................. 248 9-4 limits of reading timer register ........................................................................................ 250 9-5 maximum input frequency and minimum input pulse width that can be counted as events ............................................................................................................... 261 9-6 limits of reading timer register ........................................................................................ 279 10-1 timer/counter 2 intervals .................................................................................................... 284 10-2 timer/counter 2 programmable square-wave output setting range ............................. 285 10-3 timer/counter 2 pulse width measurement range ........................................................... 286 10-4 clocks enabled to be input to timer/counter 2 ................................................................. 286 10-5 limits of reading timer register ........................................................................................ 289 10-6 timer output (to2/to3) operations .................................................................................. 313 10-7 to2/to3 toggle output (f xx = 32 mhz) ............................................................................. 315 10-8 to2/to3 pwm cycle (f xx = 32 mhz, bw2 = 0) ................................................................ 317 10-9 to2/to3 pwm cycle (f xx = 32 mhz, bw2 = 1) ................................................................ 318 10-10 to2 ppg output (f xx = 32 mhz) ......................................................................................... 324 10-11 limits of reading timer register ........................................................................................ 354 11-1 timer 3 intervals .................................................................................................................. 358 11-2 limits of reading timer register ........................................................................................ 360 11-3 limits of reading timer register ........................................................................................ 372 14-1 a/d conversion time ........................................................................................................... 395 17-1 differences between uart/ioe1 and uart2/ioe2 names ............................................ 412 17-2 receive error causes .......................................................................................................... 425 17-3 baud rate setting methods ................................................................................................. 441 17-4 examples of brgc settings when baud rate generator is used .................................. 442 17-5 examples of settings when external baud rate input (asck) is used .......................... 443 19-1 intcsi generation timing and wait control ..................................................................... 480 19-2 relationship between signals and flags ............................................................................ 488 21-1 pins p20 to p26 and use of detected edge ...................................................................... 494 22-1 interrupt request service modes ........................................................................................ 502 22-2 interrupt request sources ................................................................................................... 502 22-3 control registers .................................................................................................................. 506 22-4 interrupt control register flags corresponding to interrupt sources ............................... 507 22-5 multiple interrupt servicing .................................................................................................. 527 22-6 interrupts for which macro service can be used .............................................................. 534 list of tables (2/3) table no. title page 37 user? manual u11316ej4v1ud 22-7 interrupt acknowledge processing time ............................................................................ 570 22-8 macro service processing time .......................................................................................... 571 23-1 system clock frequency and refresh pulse output cycle when pseudo-static ram is used ................................................................................................. 603 24-1 operating states in halt mode ......................................................................................... 615 24-2 halt mode release and operations after release .......................................................... 616 24-3 halt mode release by maskable interrupt request ........................................................ 622 24-4 operating states in stop mode ......................................................................................... 623 24-5 stop mode release and operations after release ......................................................... 624 24-6 operating states in idle mode .......................................................................................... 629 24-7 idle mode release and operations after release ........................................................... 630 25-1 pin statuses during reset input and after reset release ............................................... 638 25-2 hardware states after reset ............................................................................................... 639 26-1 prom programming operating modes .............................................................................. 643 27-1 list of instructions by 8-bit addressing .............................................................................. 678 27-2 list of instructions by 16-bit addressing ............................................................................ 680 27-3 list of instructions by 24-bit addressing ............................................................................ 682 27-4 list of instructions by bit manipulation instruction addressing ......................................... 682 27-5 list of instructions by call/return instruction / branch instruction addressing ................ 683 30-1 surface mounting type soldering conditions .................................................................... 714 a-1 differences with pd784026 subseries ............................................................................. 716 list of tables (3/3) table no. title page 38 user? manual u11316ej4v1ud chapter 1 general the pd784038 subseries comprises 78k/iv series products that can perform input/output directly with analog signals. the 78k/iv series comprises 16-bit single-chip microcontrollers equipped with a high-performance cpu that has a function such as accessing a 1-mbyte memory space. the pd784038 subseries is upward-compatible with the 78k/ii series, and has pin compatibility with pd78234 subseries of the 78k/ii series. the pd784038 incorporates 128-kbyte mask rom and 4,352-byte ram, plus high-performance timer/counters, an 8-bit a/d converter, 8-bit d/a converter, pwm output function, two independent serial interface channels, etc. the pd784031 is a rom-less model of the pd784038 but is provided with ram of 2,048 bytes. the pd784035 is based on the pd784038 but is provided with 48 kbytes of mask rom and 2,048 bytes of ram. the pd784036 is based on the pd784038 but is provided with 64 kbytes of mask rom and 2,048 bytes of ram. the pd784037 is based on the pd784038 but is provided with 96 kbytes of mask rom and 3,584 bytes of ram. the pd78p4038 replaces the mask rom of the pd784038 with prom. the pd784038y subseries is based on the pd784038 subseries but is provided with an i 2 c bus control function. the relation among these models is as shown below. these models can be used in the following fields: < pd784038 subseries> < pd784038y subseries> lbp cellular phone auto-focus camera cordless telephone ppc audio/visual systems printer electronic typewriter air conditioner electronic musical instruments cellular phone pd78p4038y pd78p4038 pd784038y pd784038 pd784037y pd784037 pd784036y pd784036 pd784035y pd784035 prom ram 128 k 4,352 rom ram 128 k 4,352 rom ram 96 k 3,584 rom ram 64 k 2,048 rom ram 48 k 2,048 prom models mask rom models pd784031y pd784031 rom ram none 2,048 rom-less models chapter 1 general 39 user? manual u11316ej4v1ud 78k/iv series product development diagram pd784026 pd784956a pd784908 pd784915 pd784928 pd784928y pd784046 pd784054 pd784216a pd784216ay pd784038 pd784038y pd784225y pd784225 pd784218ay pd784218a enhanced a/d converter, 16-bit timer, and power management enhanced internal memory capacity pin-compatible with the pd784026 supports i 2 c bus supports multimaster i 2 c bus 80-pin, rom correction added supports multimaster i 2 c bus enhanced internal memory capacity, rom correction added 100-pin, enhanced i/o and internal memory capacity on-chip 10-bit a/d converter for dc inverter control on-chip iebus tm controller software servo control on-chip analog circuit for vcrs enhanced timer supports multimaster i 2 c bus enhanced functions of the pd784915 standard models assp models supports multimaster i 2 c bus : products in mass-production pd784976a on-chip vfd controller/driver pd784938a enhanced functions of the pd784908, enhanced internal memory capacity, rom correction added. remark vfd (vacuum florescent display) is referred to as fip tm (florescent indicator panel) in some documents, but the functions of the two are the same. chapter 1 general 40 user s manual u11316ej4v1ud 1.1 features ? 78k/iv series ? pin-compatible with pd78234 subseries and pd784026 subseries ? internal memory of pd78234 subseries and pd784026 subseries expanded ? high-speed instruction execution minimum instruction execution time (32-mhz operation): 125 ns ? instruction set suitable for control applications ? data memory extension function (1-mbyte memory space: 2 bank specification pointers) ? interrupt controller (4-level priority system) vectored interrupt service/macro service/context switching ? standby functions: halt/stop/idle modes ? internal memory: rom mask rom : 128 kbytes ( pd784038) 96 kbytes ( pd784037) 64 kbytes ( pd784036) 48 kbytes ( pd784035) not provided ( pd784031) prom : 128 kbytes ( pd78p4038) ram : 4,352 bytes ( pd784038, 78p4038) 3,584 bytes ( pd784037) 2,048 bytes ( pd784031, 784035, 784036) ? i/o pins pd784035, 784036, 784037, 784038, 78p4038 : 64 software programmable pull-up : 54 inputs direct led drive capability : 24 outputs direct transistor drive capability : 8 outputs pd784031: 46 software programmable pull-up : 34 inputs direct led drive capability : 8 outputs direct transistor drive capability : 8 outputs ? serial interface uart/ioe (3-wire serial i/o): 2 channels (with on-chip baud rate generator) csi (3-wire serial i/o, 2-wire serial i/o, i 2 c bus note ): 1 channel note pd784038y subseries only ? real-time output ports (combination with timer/counter allows independent control of 2-system stepping motors) ? a/d converter (8-bit resolution 8 channels) ? d/a converter (8-bit resolution 2 channels) ? pwm outputs (12-bit resolution 2 channels) ? high-performance timer/counter timer/counter (16 bits) 3 units timer (16 bits) 1 unit ? watchdog timer: 1 channel ? clock output function: f clk , f clk /2, f clk /4, f clk /8, f clk /16 can be selected (other than pd784031) chapter 1 general 41 user s manual u11316ej4v1ud 1.2 ordering information and quality grades 1.2.1 ordering information (1) pd784038 subseries part number package internal rom pd784031gc-8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) none pd784031gk-9eu 80-pin plastic tqfp (fine pitch) (12 x 12) none pd784031gc(a)-3b9 80-pin plastic qfp (14 x 14, 2.7 mm thickness) none pd784035gc- -8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) mask rom pd784035gk- -9eu 80-pin plastic tqfp (fine pitch) (12 x 12) mask rom pd784035gc(a)- -3b9 80-pin plastic qfp (14 x 14, 2.7 mm thickness) mask rom pd784036gc- -8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) mask rom pd784036gk- -9eu 80-pin plastic tqfp (fine pitch) (12 x 12) mask rom pd784036gc(a)- -3b9 80-pin plastic qfp (14 x 14, 2.7 mm thickness) mask rom pd784037gc- -8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) mask rom pd784037gk- -9eu 80-pin plastic tqfp (fine pitch) (12 x 12) mask rom pd784038gc- -8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) mask rom pd784038gk- -9eu 80-pin plastic tqfp (fine pitch) (12 x 12) mask rom pd78p4038gc-8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) one-time prom pd78p4038gk-9eu 80-pin plastic tqfp (fine pitch) (12 x 12) one-time prom remark indicates rom code suffix. chapter 1 general 42 user s manual u11316ej4v1ud (2) pd784038y subseries part number package internal rom pd784031ygc-8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) none pd784031ygk-9eu 80-pin plastic tqfp (fine pitch) (12 x 12) none pd784035ygc- -8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) mask rom pd784035ygk- -9eu 80-pin plastic tqfp (fine pitch) (12 x 12) mask rom pd784036ygc- -8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) mask rom pd784036ygk- -9eu 80-pin plastic tqfp (fine pitch) (12 x 12) mask rom pd784037ygc- -8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) mask rom pd784037ygk- -9eu 80-pin plastic tqfp (fine pitch) (12 x 12) mask rom pd784038ygc- -8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) mask rom pd784038ygk- -9eu 80-pin plastic tqfp (fine pitch) (12 x 12) mask rom pd78p4038ygc-8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) one-time prom pd78p4038ygk-9eu 80-pin plastic tqfp (fine pitch) (12 x 12) one-time prom remark indicates rom code suffix. chapter 1 general 43 user? manual u11316ej4v1ud 1.2.2 quality grades (1) pd784038 subseries part number package quality grades pd784031gc-8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) standard pd784031gk-9eu 80-pin plastic tqfp (fine pitch) (12 x 12) standard pd784031gc(a)-3b9 80-pin plastic qfp (14 x 14, 2.7 mm thickness) special pd784035gc- -8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) standard pd784035gk- -9eu 80-pin plastic tqfp (fine pitch) (12 x 12) standard pd784035gc(a)- -3b9 80-pin plastic qfp (14 x 14, 2.7 mm thickness) special pd784036gc- -8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) standard pd784036gk- -9eu 80-pin plastic tqfp (fine pitch) (12 x 12) standard pd784036gc(a)- -3b9 80-pin plastic qfp (14 x 14, 2.7 mm thickness) special pd784037gc- -8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) standard pd784037gk- -9eu 80-pin plastic tqfp (fine pitch) (12 x 12) standard pd784038gc- -8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) standard pd784038gk- -9eu 80-pin plastic tqfp (fine pitch) (12 x 12) standard pd78p4038gc-8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) standard pd78p4038gk-9eu 80-pin plastic tqfp (fine pitch) (12 x 12) standard please refer to the document "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation for the specification of the quality grades of the devices and their recommended applications. remark indicates rom code suffix. chapter 1 general 44 user s manual u11316ej4v1ud (2) pd784038y subseries part number package quality grades pd784031ygc-8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) standard pd784031ygk-9eu 80-pin plastic tqfp (fine pitch) (12 x 12) standard pd784035ygc- -8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) standard pd784035ygk- -9eu 80-pin plastic tqfp (fine pitch) (12 x 12) standard pd784036ygc- -8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) standard pd784036ygk- -9eu 80-pin plastic tqfp (fine pitch) (12 x 12) standard pd784037ygc- -8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) standard pd784037ygk- -9eu 80-pin plastic tqfp (fine pitch) (12 x 12) standard pd784038ygc- -8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) standard pd784038ygk- -9eu 80-pin plastic tqfp (fine pitch) (12 x 12) standard pd78p4038ygc-8bt 80-pin plastic qfp (14 x 14, 1.4 mm thickness) standard pd78p4038ygk-9eu 80-pin plastic tqfp (fine pitch) (12 x 12) standard remark indicates rom code suffix. chapter 1 general 45 user s manual u11316ej4v1ud 1.3 pin configuration (top view) 1.3.1 normal operating mode 80-pin plastic qfp (14 x 14, 2.7 mm thickness) pd784031gc(a)-3b9, 784035gc(a)- -3b9, 784036gc(a)- -3b9 80-pin plastic qfp (14 x 14, 1.4 mm thickness) pd784031gc-8bt, 784035gc- -8bt, 784036gc- -8bt, 784037gc- -8bt, 784038gc- -8bt, 78p4038gc-8bt, 784031ygc-8bt, 784035ygc- -8bt, 784036ygc- -8bt, 784037ygc- -8bt, 784038ygc- -8bt, 78p4038ygc-8bt 80-pin plastic tqfp (fine pitch)(12 x 12) pd784031gk-9eu, 784035gk- -9eu,784036gk- -9eu,784037gk- -9eu, 784038gk- -9eu, 78p4038gk-9eu, 784031ygk-9eu, 784035ygk- -9eu, 784036ygk- -9eu, 784037ygk- -9eu, 784038ygk- -9eu, 78p4038ygk-9eu chapter 1 general 46 user s manual u11316ej4v1ud p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 v dd0 p17 p16 p15 p14/txd2/so2 p13/rxd2/si2 p11/pwm1 p10/pwm0 v ss0 astb/clkout p40/ad0 p41/ad1 p42/ad2 p33/so0/sda p34/to0 p35/to1 p36/to2 p37/to3 v dd1 x2 x1 v ss1 p00 p01 p02 p03 p04 p05 p06 p07 p12/asck2/sck2 test note 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 p32/sck0/scl reset p67/refrq/hldak p31/txd/so1 p30/rxd/si1 p27/si0 p26/intp5 p24/intp3 p23/intp2/ci p22/intp1 p21/intp0 p20/nmi av ref3 ano1 ano0 av ref1 av dd p77/ani7 p76/ani6 p75/ani5 p63/a19 p62/a18 p61/a17 p57/a15 p56/a14 p55/a13 p54/a12 p53/a11 p52/a10 p51/a9 p50/a8 p47/ad7 p46/ad6 p45/ad5 p44/ad4 av ref2 p25/intp4/asck/sck1 p66/wait/hldrq p60/a16 p43/ad3 p65/wr p64/rd av ss 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 note connect the test pin directly to v ss0 . caution with the chapter 1 general 47 user s manual u11316ej4v1ud p00 to p07 : port 0 p10 to p17 : port 1 p20 to p27 : port 2 p30 to p37 : port 3 p40 to p47 : port 4 p50 to p57 : port 5 p60 to p67 : port 6 p70 to p77 : port 7 to0 to to3 : timer output ci : clock input rxd, rxd2 : receive data txd, txd2 : transmit data sck0 to sck2 : serial clock scl : serial clock asck, asck2 : asynchronous serial clock sda : serial data si0 to si2 : serial input so0 to so2 : serial output pwm0, pwm1 : pulse width modulation output nmi : non-maskable interrupt intp0 to intp5 : interrupt from peripherals ad0 to ad7 : address/data bus a8 to a19 : address bus rd : read strobe wr : write strobe wait : wait hldrq : hold request hldak : hold acknowledge clkout : clock out astb : address strobe refrq : refresh request reset : reset x1, x2 : crystal ani0 to ani7 : analog input ano0, ano1 : analog output av ref1 to av ref3 : reference voltage av dd : analog power supply av ss : analog ground v dd0 , v dd1 : power supply v ss0 , v ss1 : ground test : test chapter 1 general 48 user? manual u11316ej4v1ud 1.3.2 prom programming mode (v pp +5 v/+12.5 v, reset = l) ? 80-pin plastic qfp (14 14, 1.4 mm thick) pd78p4038gc-8bt, 78p4038ygc-8bt ? 80-pin plastic tqfp (fine pitch) (12 12) pd78p4038gk-9eu, 78p4038ygk-9eu open v dd (l) open v ss open a0 a1 a2 open v dd open (l) v ss d0 d1 d2 d3 d4 d5 d6 d7 v pp 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (l) reset (l) open v ss v ss open v dd open (l) a15 a14 a13 a12 a11 a10 a16 a8 a7 a6 a5 a4 pgm a3 ce oe v ss 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 a9 caution l : connect to v ss individually via a 10 k ? pull-down resistor. v ss : connect to ground. open : do not make any connection. reset : drive low. v pp : programming power supply pgm : program reset : reset oe : output enable a0 to a16 : address bus v dd : power supply d0 to d7 : data bus v ss : ground ce : chip enable chapter 1 general 49 user s manual u11316ej4v1ud 1.4 application system configuration example (ppc) serial communication paper transport detection fixing heater temperature lamp brightness copy density adjustment lever copy density correction lever reset circuit reset ani3 ani2 ani1 ani0 intp0 txd rxd p11 p15 p16 p17 sck1 si1 so1 p04 p06 p07 p66 pwm0 p00 to p03 p33 p34 p35 p36 p37 driver paper detection paper feed detection paper out detection document base (scanner) position detection control panel high-voltage control circuit fixing heater control circuit lamp regulator drum, toner transfer charge fixing roller document illumination lamp discharge lamp (dc, stepping) main motor m document base (scanner) stop clutch document base (scanner) advance clutch resist shutter clutch manual paper feed clutch cassette paper feed clutch solenoids pd784038 sl sl sl sl sl chapter 1 general 50 user s manual u11316ej4v1ud 1.5 block diagram rxd/si1 txd/so1 asck/sck1 rxd2/si2 txd2/so2 asck2/sck2 sck0/scl so0/sda si0 astb/clkout note 2 ad0 to ad7 a8 to a15 a16 to a19 rd wr wait/hldrq refrq/hldak p00 to p07 p10 to p17 p20 to p27 p30 to p37 p40 to p47 note 2 p50 to p57 note 2 p60 to p67 note 2 p70 to p77 reset test uart/ioe2 baud-rate generator uart/ioe1 baud-rate generator clocked note 1 serial interface clock output bus i/f port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 system control rom 78k/iv cpu core ram watchdog timer nmi intp0 to intp5 intp3 to0 to1 intp0 intp1 intp2/ci to2 to3 p00 to p03 p04 to p07 pwm0 pwm1 ano0 ano1 av ref2 av ref3 ani0 to ani7 av dd av ref1 av ss intp5 programmable interrupt controller timer/counter 0 (16 bits) timer/counter 1 (16 bits) timer/counter 2 (16 bits) timer 3 (16 bits) real-time output port pwm d/a converter a/d converter x1 x2 v dd0 , v dd1 v ss0 , v ss1 notes 1. the pd784038y subseries supports the i 2 c bus mode. 2. when the pd784031, clkout, p40 to p47, p50 to p57, p64, and p65 cannot be used. remark the capacities of the internal rom and ram differ depending on the model. chapter 1 general 51 user s manual u11316ej4v1ud 1.6 list of functions (1/2) part number pd784031 pd784035 pd784036 pd784037 pd784038 pd78p4038 item pd784031y pd784035y pd784036y pd784037y pd784038y pd78p4038y number of basic instructions 113 (mnemonics) general-purpose register 8 bits 16 registers 8 banks, or 16 bits 8 registers 8 banks (memory mapping) minimum instruction execution time 125 ns (at 32 mhz operation) internal rom none 48 kbytes 64 kbytes 96 kbytes 128 kbytes 128 kbytes memory (mask rom) (mask rom) (mask rom) (mask rom) (one-time prom) ram 2,048 bytes 3,584 bytes 4,352 bytes memory space 1 mbyte with program and data memories combined i/o port total 46 lines 64 lines input 8 lines i/o 34 lines 56 lines output 4 lines 0 line pins with pin with pull-up resistor 32 pins 54 pins ancillary led direct drive output 8 pins 24 pins functions transistor direct drive 8 pins real-time output port 4 bits 2, or 8 bits 1 timer/counter timer/counter 0 (16 bits) : timer register 1 pulse output capture register 1 toggle output compare register 2 pwm/ppg output one-shot pulse output timer/counter 1 (8/16 bits): timer register 1 pulse output capture register 1 real-time output (4 bits 2) capture/compare register 1 compare register 1 timer/counter 2 (8/16 bits): timer register 1 pulse output capture register 1 toggle output capture/compare register 1 pwm/ppg output compare register 1 timer 3 (8/16 bits) : timer register 1 compare register 1 pwm output 12-bit resolution 2 channels serial interface uart/ioe (3-wire serial i/o): 2 channels (with baud rate generator) csi (3-wire serial i/o, 2-wire serial i/o, i 2 c bus note 2 ): 1 channel a/d converter 8-bit resolution 8 channels d/a converter 8-bit resolution 2 channels notes 1. the pins with ancillary functions are included in the i/o pins. 2. pd784038y subseries only. note 1 chapter 1 general 52 user s manual u11316ej4v1ud (2/2) part number pd784031 pd784035 pd784036 pd784037 pd784038 pd78p4038 item pd784031y pd784035y pd784036y pd784037y pd784038y pd78p4038y clock output selectable from f clk , f clk /2, f clk /4, f clk /8, f clk /16 (also can be used as 1-bit output port) watchdog timer 1 channel standby halt/stop/idle mode interrupt ( pd784038 subseries) hardware causes 23 (internal: 16, external: 7 (sampling clock variable input: 1)) software brk instruction, brkcs instruction, operand error non-maskable internal : 1, external : 1 maskable internal : 15, external: 6 4 levels of programmable priority 3 processing types: vector interrupt/macro service/context switching interrupt ( pd784038y subseries) hardware causes 24 (internal: 17, external: 7 (sampling clock variable input: 1)) software brk instruction, brkcs instruction, operand error non-maskable internal : 1, external : 1 maskable internal : 16, external: 6 4 levels of programmable priority 3 processing types: vector interrupt/macro service/context switching supply voltage v dd = 2.7 to 5.5 v package 80-pin plastic qfp (14 14, 2.7 mm thick) note 80-pin plastic qfp (14 14, 1.4 mm thick) 80-pin plastic tqfp (fine pitch) (12 12) note pd784031(a), 784035(a), and 784036(a) only chapter 1 general 53 user s manual u11316ej4v1ud 1.7 differences between standard-grade products and special-grade products part number pd784031(a), pd784035(a), pd784036(a) pd784031, pd784035, pd784036 item quality grade special standard package 80-pin plastic qfp (14 x 14, 2.7 mm thick) 80-pin plastic qfp (14 x 14, 1.4 mm thick) 80-pin plastic tqfp (fine pitch, 12 x 12) 1.8 major differences with item series name pd784038 subseries pd784038y subseries pd784026 subseries minimum instruction execution time 125 ns (32-mhz operation) 160 ns (25-mhz operation) serial interface uart/ioe (3-wire serial i/o) 2 channels csi 1 channel csi 1 channel csi 1 channel 3-wire serial i/o 3-wire serial i/o 3-wire serial i/o 2-wire serial i/o 2-wire serial i/o sbi i 2 c bus interrupts 23 + brk instruction 24 + brk instruction 23 + brk instruction (internal: 16, external: 7) (internal: 17, external: 7) (internal: 16, external: 7) packages 80-pin plastic qfp (14 14, 2.7 mm thick) note 80-pin plastic qfp 80-pin plastic qfp (14 14, 1.4 mm thick) (14 14, 2.7 mm thick) 80-pin plastic tqfp (fine-pitch) (12 12) 80-pin plastic tqfp (fine-pitch) (12 12): pd784021 only note pd784031(a), 784035(a), and 784036(a) only 54 user? manual u11316ej4v1ud chapter 2 pin functions 2.1 pin function tables 2.1.1 normal operating mode (1) port pins (1/2) pin name input/output alternate function functions p00 to p07 input/output port 0 (p0): 8-bit input/output port can be used as real-time output ports (4 bits 2) input/output specifiable bit-wise for input mode pins, on-chip pull-up resistor connection can be specified at once by a software setting transistor drive capability p10 input/output pwm0 p11 pwm1 p12 asck2/sck2 p13 rxd2/si2 p14 txd2/so2 p15 to p17 p20 input nmi p21 intp0 p22 intp1 p23 intp2/ci p24 intp3 p25 intp4/asck/sck1 p26 intp5 p27 si0 p30 input/output rxd/si1 p31 txd/so1 p32 sck0/scl p33 so0/sda p34 to p37 to0 to to3 port 1 (p1): 8-bit input/output port input/output specifiable bit-wise. for input mode pins, on-chip pull-up resistor connection can be specified at once by a software setting led drive capability port 2 (p2): 8-bit input/output port p20 cannot be used as a general-purpose port (non-maskable interrupt). input level can be confirmed in the interrupt routine. for p22 to p27, on-chip pull-up resistor connection can be specified by a software setting in 6-bit units the p25/intp4/asck/sck1 pin operates as the sck1 i/o pin in accordance with the csim1 register specification port 3 (p3): 8-bit input/output port input/output specifiable bit-wise for input mode pins, on-chip pull-up resistor connection can be specified at once by a software setting chapter 2 pin functions 55 user? manual u11316ej4v1ud (1) port pins (2/2) pin name input/output alternate function functions p40 to p47 note 1 input/output ad0 to ad7 port 4 (p4): 8-bit input/output port input/output specifiable bit-wise for input mode pins, on-chip pull-up resistor connection can be specified at once by a software setting leds drive capability p50 to p57 note 1 input/output a8 to a15 port 5 (p5): 8-bit input/output port input/output specifiable bit-wise for input mode pins, on-chip pull-up resistor connection can be specified at once by a software setting leds drive capability p60 to p63 note 2 input/output a16 to a19 p64 note 1 rd p65 note 1 wr p66 wait/hldrq p67 refrq/hldak p70 to p77 input/output ani0 to ani7 port 7 (p7): 8-bit input/output port input/output specifiable bit-wise notes 1. with the pd784031, p40 to p47, p50 to p57, p64, and p65 cannot be used as port pins. 2. these pins of the pd784031 are output port pins. port 6 (p6): 8-bit input/output port input/output specifiable bit-wise for input mode pins, on-chip pull-up resistor connection can be specified at once by a software setting chapter 2 pin functions 56 user? manual u11316ej4v1ud (2) non-port pins (1/2) pin name input/output alternate function functions to0/to3 output p34 to p37 timer output ci input p23/intp2 count clock input to timer/counter 2 rxd input p30/si1 serial data input (uart0) rxd2 p13/si2 serial data input (uart2) txd output p31/so1 serial data output (uart0) txd2 p14/so2 serial data output (uart2) asck input p25/intp4/sck1 baud rate clock input (uart0) asck2 p12/sck2 baud rate clock input (uart2) sda input/output p33/so0 serial data input/output (2-wire serial i/o, i 2 c bus note ) si0 input p27 serial data input (3-wire serial i/o0) si1 p30/rxd serial data input (3-wire serial i/o1) si2 p13/rxd2 serial data input (3-wire serial i/o2) so0 output p33/sda serial data output (3-wire serial i/o0) so1 p31/txd serial data output (3-wire serial i/o1) so2 p14/txd2 serial data output (3-wire serial i/o2) sck0 input/output p32/scl serial clock input/output (3-wire serial i/o0) sck1 p25/intp4/asck serial clock input/output (3-wire serial i/o1) sck2 p12/asck2 serial clock input/output (3-wire serial i/o2) scl p32/sck0 serial clock input/output (2-wire serial i/o, i 2 c bus note ) nmi input p20 external interrupt requests intp0 p21 count clock input to timer/counter 1 cr11 or cr12 capture trigger signal intp1 p22 count clock input to timer/counter 2 cr22 capture trigger signal intp2 p23/ci count clock input to timer/counter 2 cr21 capture trigger signal intp3 p24 count clock input to timer/counter 0 cr02 capture trigger signal intp4 p25/asck/sck1 intp5 p26 a/d converter conversion start trigger input ad0 to ad7 input/output p40 to p47 time division address/data bus (external memory connection) a8 to a15 output p50 to p57 upper address bus (external memory connection) a16 to a19 output p60 to p63 upper address with address extension (external memory connection) rd output p64 external memory read strobe wr output p65 external memory write strobe wait input p66/hldrq wait insertion refrq output p67/hldak external pseudo-static memory refresh pulse output hldrq input p66/wait bus hold request input hldak output p67/refrq bus hold response output note pd784038y subseries only chapter 2 pin functions 57 user? manual u11316ej4v1ud (2) non-port pins (2/2) pin name input/output alternate function functions astb output clkout time division address (a0 to a7) latch timing output (during external memory access) clkout note 1 output astb clock output reset input chip reset x1 input system clock oscillation crystal connections x2 (clock can also be input to x1) ani0 to ani7 input p70 to p77 a/d conversion analog voltage inputs ano0, ano1 output d/a conversion analog voltage outputs av ref1 a/d converter reference voltage application av ref2 , av ref3 d/a converter reference voltage application av dd a/d converter positive power supply av ss a/d converter gnd v dd0 note 2 positive power supply pin of ports v dd1 note 2 positive power supply pin of function blocks other than ports v ss0 note 3 gnd pin of ports v ss1 note 3 gnd pin of function blocks other than ports test connect directly to v ss0 (ic test pin). notes 1. with the pd784031, clkout cannot be used. 2. keep v dd0 and v dd1 at the same potential. 3. keep v ss0 and v ss1 at the same potential. 2.1.2 prom programming mode ( pd78p4038 only: v pp +5 v/+12.5 v, reset = l) pin name input/output functions v pp input prom programming mode setting high-voltage application pin in program write/verify reset prom programming mode setting a0 to a16 address bus d0 to d7 input/output data bus ce input prom enable input/program pulse input oe prom read strobe input pgm prom program/program inhibit input v dd positive power supply v ss gnd chapter 2 pin functions 58 user? manual u11316ej4v1ud 2.2 pin functions 2.2.1 normal operating mode (1) p00 to p07 (port 0) ... 3-state input/output port 0 is an 8-bit input/output port with an output latch, and has direct transistor drive capability. input/output can be spe cified bit-wise by means of the port 0 mode register (pm0). each pin incorporates a software programmable pull-up resistor. p00 to p03 and p04 to p07 can output the port 0 buffer register (p0l, p0h) contents at any time interval as 4-bit or 8-bit real-time output port. the real-time output port control register (rtpc) is used to select whether this port is used as a norm al output port or a real-time output port. when reset is input, port 0 is set as an input port (output high-impedance state), and the output latch contents are undefined. (2) p10 to p17 (port 1) ... 3-state input/output port 1 is an 8-bit input/output port with an output latch. input/output can be specified bit-wise by means of the port 1 mode register (pm1). each pin incorporates a software programmable pull-up resistor. this port has direct led drive capability. pins p10 and p11 are also made to function as pwm output pins by means of the pwm control register (pwmc), and pins p12 to p14 can also be made to function as serial input/output pins by means of the port 1 mode control register (pmc1). when reset is input, port 1 is set as an input port (output high-impedance state), and the output latch contents are undefined. table 2-1 port 1 operating modes pin name port mode control signal input/output mode operation to operate as control pin p10 input/output port pwm0 output set (to 1) en0 bit of pwmc p11 pwm1 output set (to 1) en1 bit of pwmc p12 asck2/sck2 input/output set (to 1) pmc12 bit of pmc1 p13 rxd2/si2 input set (to 1) pmc13 bit of pmc1 p14 txd2/so2 output set (to 1) pmc14 bit of pmc1 p15 to p17 (a) port mode p10 and p11 operate as port mode pins when the en0 and en1 bits of the pwm control (pwmc) register are cleared (to 0), and p12 to p14 do the same when the relevant bits of the port 1 mode control (pmc1) register are cleared (to 0), and p15 to p17 always operate as port mode pins. input/output can be specified bit-wise by means of the port 1 mode register (pm1). (b) control signal input/output mode p10 and p11 operate as pwm signal output pins when the en0 and en1 bits, respectively, of the pwm control (pwmc) register are set (to 1). p12 to p14 can be set as control pins bit-wise by setting the port 1 mode control (pmc1) register. (i) pwm0, pwm1 pwm0 and pwm1 are pwm output pins. (ii) asck2/sck2 asck2 is the asynchronous serial interface baud rate clock input pin. sck2 is the serial clock input/output pin (in 3-wire serial i/o2 mode). chapter 2 pin functions 59 user? manual u11316ej4v1ud (iii) rxd2/si2 rxd2 is the asynchronous serial interface serial data input pin. si2 is the serial data input pin (in 3-wire serial i/o2 mode). (iv) txd2/so2 txd2 is the asynchronous serial interface serial data output pin. so2 is the serial data output pin (in 3-wire serial i/o2 mode). (3) p20 to p27 (port 2) ... input port 2 is an 8-bit input-only port. p22 to p27 incorporate a software programmable pull-up resistor. as well as operating as an input port, port 2 pins also operate as control signal input pins, such as external interrupt signal pins (see table 2-2 ). all 8 pins are schmitt-triggered inputs to prevent malfunction due to noise. also, pin p25 can also be made to function as a serial clock output pin by selecting the external clock as ?erial operation enabled?with the clocked serial interface mode register 1 (csim1). table 2-2 port 2 operating modes port functions p20 input port / nmi input note p21 input port / intp0 input / cr11 capture trigger input / timer/counter 1 count clock / real-time output port trigger signal p22 input port / intp1 input / cr22 capture trigger input p23 input port / intp2 input / ci input p24 input port / intp3 input / cr02 capture trigger timer/input/counter 0 count clock p25 input port / intp4 input / asck input / sck1 input/output p26 input port / intp5 input / a/d converter external trigger input p27 input port / si0 input note nmi input is acknowledged regardless of whether interrupts are enabled or disabled. (a) function as port pins the pin level can always be read or tested regardless of the dual-function pin operation. (b) functions as control signal input pins (i) nmi (non-maskable interrupt) the external non-maskable interrupt request input pin. rising edge detection or falling edge detection can be specified by means of the external interrupt mode register 0 (intm0). chapter 2 pin functions 60 user? manual u11316ej4v1ud (ii) intp0 to intp5 (interrupt from peripherals) external interrupt request input pins. when the valid edge specified by the external interrupt mode register 0, (intm0/intm1) is detected by pins intp0 to intp5, an interrupt is generated (see chapter 21 edge detection function ). in addition, pins intp0 to intp3 and intp5 are also used as external trigger input pins with the various functions shown below. ? intp0 ....... timer/counter 1 capture trigger input pin timer/counter 1 external count clock input pin real-time output port trigger input pin ? intp1 ....... timer/counter 2 capture trigger input pin to capture register (cr22) ? intp2 ....... timer/counter 2 external count clock input pin capture trigger input pin to capture/compare register (cr21) ? intp3 ....... timer/counter 0 capture trigger input pin timer/counter 0 external count clock input pin ? intp5 ....... a/d converter external trigger input pin (iii) ci (clock input) the timer/counter 2 external clock input pin. (iv) asck (asynchronous serial clock) the external baud rate clock input pin. (v) sck1 (serial clock) the serial clock input/output pin (in 3-wire serial i/o1 mode). (vi) sio (serial input 0) the serial data input pin (in 3-wire serial i/o0 mode). (4) p30 to p37 (port 3) ... 3-state input/output port 3 is an 8-bit input/output port with an output latch. input/output can be specified bit-wise by means of the port 3 mode register (pm3). each pin incorporates a software programmable pull-up resistor. in addition to its function as an input/output port, port 3 also has various alternate-function control signal pin functions. the operating mode can be specified bit-wise by means of the port 3 mode control register (pmc3), as shown in table 2-3. the pin level of any pin can always be read or tested regardless of the alternate-function pin operation. when reset is input, port 3 is set as an input port (output high-impedance state), and the output latch contents are undefined. table 2-3 port 3 operating modes (n = 0 to 7) mode port mode control signal input/output mode setting condition pmc3n = 0 pmc3n = 1 p30 input/output port rxd input / si1 input p31 txd output / so1 output p32 sck0 input/output / scl input/output p33 so0 output / sda input/output p34 to0 output p35 to1 output p36 to2 output p37 to3 output chapter 2 pin functions 61 user? manual u11316ej4v1ud (a) port mode each port specified as port mode by the port 3 mode control (pmc3) register can be specified as input/output bit-wise by means of the port 3 mode register (pm3). (b) control signal input/output mode pins can be set as control pins bit-wise by setting the port 3 mode control (pmc3) register. (i) rxd (receive data)/si1 (serial input 1) rxd is the asynchronous serial interface serial data input pin. si1 is the serial data input pin (in 3-wire serial i/o1 mode). (ii) txd (transmit data)/so1 (serial output 1) txd is the asynchronous serial interface serial data output pin. so1 is the serial data output pin (in 3-wire serial i/o1 mode). (iii) sck0 (serial clock 0)/scl (serial clock) sck0 is the clocked serial interface serial clock input/output pin (in 3-wire serial i/o 0 mode). scl is the synchronous serial interface serial clock input/output pin (in 2-wire serial i/o mode/i 2 c bus mode note ). note pd784038y subseries only (iv) so0 (serial output 0)/sda (serial data) so0 is the serial data output pin (in 3-wire serial i/o 0 mode), and sda is the serial data input/output pin (in 2- wire serial i/o mode/i 2 c bus mode note ). note pd784038y subseries only (v) to0 to to3 (timer output) the timer output pins. (5) p40 to p47 (port 4) ... 3-state input/output port 4 is an 8-bit input/output port with an output latch. input/output can be specified bit-wise by means of the port 4 mode register (pm4). each pin incorporates a software programmable pull-up resistor. this port has direct led drive capability. port 4 also functions as the time division address/data bus (ad0 to ad7) by the memory extension mode register (mm) when external memory or i/os are extended. with the pd784031, p40 to p47 cannot be used as port pins. these pins function only as the time division address/data bus pins (ad0 to ad7). when reset is input, port 4 is set as an input port (output high-impedance state), and the output latch contents are undefined. (6) p50 to p57 (port 5) ... 3-state input/output port 5 is an 8-bit input/output port with an output latch. input/output can be specified bit-wise by means of the port 5 mode register (pm5). each pin incorporates a software programmable pull-up resistor. this port has direct led drive capability. in addition, p50 to p57 can be selected by means of the memory extension mode register (mm) in 2-bit units as pins that function as the address bus (a8 to a15) when external memory or i/os are extended. with the pd784031, p50 to p57 cannot be used as port pins. these pins function only as the address bus pins (a8 to a15). when reset is input, port 5 is set as an input port (output high-impedance state), and the output latch contents are undefined. chapter 2 pin functions 62 user? manual u11316ej4v1ud (7) p60 to p67 (port 6) ... 3-state input/output ?with pd784031 p60 to p63 are output port pins and p66 and p67 are input/output port pins with output latch. p64 to p67 incorporate a software programmable pull-up resistor. in addition to the functions as port pins, these pins also have various alternate-function control signal pin functions, as shown in table 2-4. operations as control pins are performed by the respective function operations. p64 and p65 cannot be used as port pins and function only as rd and wr output pins. when reset is input, the level of the above pins are set as follows: p60 to p63: low p64, p65: high p66, p67: input port (output high impedance) the higher 4 bits of the contents are undefined, and the lower 4 bits are reset to 0h. ?with other than pd784031 port 6 is an 8-bit input/output port with an output latch. p60 to p67 incorporate a software programmable pull-up resistor. in addition to its function as a port, port 6 also has various alternate-function control signal pin functions, as shown in tab le 2-4. operations as control pins are performed by the respective function operations. when reset is input, p60 to p67 are set as input port pins (output high-impedance state), and the output latch contents are undefined. table 2-4 port 6 operating modes pin name port mode control signal input/output mode operation to operate as control pin p60 to p63 input/output ports a16 to a19 output specified in 2-bit units by bits mm3 to mm0 of the mm p64 note 2 rd output p65 note 2 wr output p66 wait input specified by setting bits pwn1 & pwn0 (n = 0 to 7) of the pwc1 & pwc2 and p66 to input mode hldrq input bus hold enabled by the hlde bit of the hldm p67 hldak output refrq output set (to 1) the rfen bit of the rfm notes 1. these pins of the pd784031 are output port pins only. 2. with the pd784031, this pin cannot be used as a port pin. caution p60 to p63 of the pd784031 are in the output high-impedance state while the reset signal is input, but output a low level after the reset signal has been cleared. therefore, design the external circuit so that the low level may be output as the initial status. remark for details, refer to chapter 23 local bus interface function . (a) port mode ?with pd784031 each port not specified as control mode, p66 and p67 serve as output port pins, and p66 and p67 can be specified as input/output bit-wise by means of the port 6 mode register (pm6). ?with other than pd784031 each port not set in the control mode can be set in the input or output mode in 1-bit units by using the port 6 mode register (pm6). with the pd784031, or when external memory extension mode is specified by bits mm3 to mm0 of the mm note 1 chapter 2 pin functions 63 user? manual u11316ej4v1ud (b) control signal input/output mode (i) a16 to a19 (address bus) upper address bus output pins in case of external memory space extension (10000h to fffffh). these pins operate in accordance with the memory extension mode register (mm). (ii) rd (read strobe) pin that outputs the strobe signal for an external memory read operation. operates in accordance with the memory extension mode register (mm). with the pd784031, this pin always serves as an rd pin. (iii) wr (write strobe) pin that outputs the strobe signal for an external memory write operation. operates in accordance with the memory extension mode register (mm). with the pd784031, this pin always serves as a wr pin. (iv) wait (wait) wait signal input pin. operates in accordance with the programmable wait control registers (pwc1, pwc2). (v) hldrq (hold request) external bus hold request signal input pin. operates in accordance with the hold mode register (hldm). (vi) hldak (hold acknowledge) bus hold acknowledge signal output pin. operates in accordance with the hold mode register (hldm). (vii) refrq (refresh request) this pin outputs refresh pulses to pseudo-static memory when this memory is connected externally. operates in accordance with the refresh mode register (rfm). (8) p70 to p77 (port 7) ... 3-state input/output port 7 is an 8-bit input/output port. in addition to operating as an input/output port, it also operates as the a/d converter analog input pins (ani0 to ani7). input/output can be specified bit-wise by means of the port 7 mode register (pm7). the levels of these pins can always be read or tested, regardless of the operation of the multiplexed pins. when reset is input, port 7 is set as an input port (output high-impedance state), and the output latch contents are undefined. (9) astb (address strobe)/clkout (clock output) ... output this pin outputs the timing signal that latches address information externally in order to access an external address. it also operates as the pin that supplies the clock to an external device. with the pd784031, clkout cannot be used. (10) x1, x2 (crystal) the internal clock oscillation crystal connection pins. when the clock is supplied externally, it is input to the x1 pin. usu ally signal with the inverse phase of the x1 pin signal phase is input to the x2 pin (refer to 4.3.1 clock oscillation circuit ). chapter 2 pin functions 64 user? manual u11316ej4v1ud (11) reset (reset) ... input the active-low reset input. (12) ano0, ano1 ... output the d/a converter analog voltage output pins. (13) av ref1 the a/d converter reference voltage input pin. (14) av ref2 the d/a converter reference voltage input (+ side) pin. (15) av ref3 the d/a converter reference voltage input (?side) pin. (16) av dd the a/d converter power supply pin. this should be made at the same potential as the v dd pin. (17) av ss the a/d converter gnd pin. this should be made at the same potential as the v ss pin. (18) v dd0 positive power supply pins of the ports. these pins should be made at the same potential as the v dd1 . (19) v dd1 positive power supply pins of the function blocks other than ports. these pins should be made at the same potential as the v dd0 . (20) v ss0 gnd potential pins of the ports. these pins should be made at the same potential as the v ss1 . (21) v ss1 gnd potential pins of the function blocks other than ports. these pins should be made at the same potential as the v ss0 . (22) test pin used by nec electronics for ic testing. must be directly connected to v ss0 . caution in the pd78233 and 78237, the test pin is the mode pin and is fixed high. when changing over from the pd78233, 78237, the circuitry can be modified so that this pin is directly connected to v ss0 . modification as shown below is needed if the pd78234, 78238 was used with switching between the on- chip rom mode and rom-less mode performed by mode pin switching (the test pin must be directly connected to v ss0 ). modification examples: incorporate all programs in rom. store all programs in external rom. change the location address of a program previously held in external rom, shift the address to avoid overlapping internal rom, and execute this program from the program internal rom. chapter 2 pin functions 65 user? manual u11316ej4v1ud 2.2.2 prom programming mode ( pd78p4038) (1) v pp (programming power supply) ... input input pin that sets the pd78p4038 to the prom programming mode. when the input voltage of this pin is +5 v or more and the reset input is driven low, the pd78p4038 switches to the prom programming mode. if ce = l is set when v pp = +12.5 v and oe = h, the program data on d0 to d7 can be written in the internal prom cell selected by a0 to a16. (2) reset (reset) ... input input pin that sets the pd78p4038 to the prom programming mode. when the input voltage of the v pp pin reaches +5 v or more and the input of this pin is low, the pd78p4038 switches to the prom programming mode. (3) a0 to a16 (address bus) ... input the address bus. selects an internal prom address (00000h to 1ffffh). (4) d0 to d7 (data bus) ... input/output the data bus. internal prom program reads and writes are performed via this bus. (5) ce (chip enable) ... input inputs the internal prom enable signal. when this signal is active, program writing/reading is enabled. (6) oe (output enable) ... input inputs the internal prom read strobe signal. when this signal is activated while ce = l, the program data (1 byte) in the internal prom cell selected by a0 to a16 can be read onto d0 to d7. (7) pgm (program) ... input the internal prom operating mode control signal input pin. when this signal is active, it is possible to write to internal prom. when this signal is inactive, it is possible to read from internal prom. (8) v dd positive power supply pins. (9) v ss gnd potential pins. chapter 2 pin functions 66 user? manual u11316ej4v1ud 2.3 input/output circuits and connection of unused pins table 2-5 shows the input/output circuit types of the pins that have functions, and the connection method when that function is not used. each input/output circuit type is shown in figure 2-1. table 2-5 pin input/output circuit types and recommended connection when not used (1/2) pin name input/output input/output recommended connection circuit type when not used p00 to p07 5-h input/output input : connect to v dd0 output : leave open p10/pwm0 p11/pwm1 p12/asck2/sck2 8-c p13/rxd2/si2 5-h p14/txd2/so2 p15 to p17 p20/nmi 2 input connect to v dd0 or v ss0 p21/intp0 p22/intp1 2-c connect to v dd0 p23/intp2/ci p24/intp3 p25/intp4/asck/sck1 8-c input/output input : connect to v dd0 output : leave open p26/intp5 2-c input connect to v dd0 p27/si0 p30/rxd/si1 5-h input/output input : connect to v dd0 p31/txd/so1 output : leave open p32/sck0/scl 10-b p33/so0/sda p34/to0 to p37/to3 5-h p40/ad0 to p47/ad7 p50/a8 to p57/a15 rom-less version 4-b output leave open mask rom version 5-h input/output input : connect to v dd0 p64/rd output : leave open p65/wr p66/wait/hldrq p67/refrq/hldak p60/a16 to p63/a19 chapter 2 pin functions 67 user? manual u11316ej4v1ud table 2-5 pin input/output circuit types and recommended connection when not used (2/2) pin name input/output input/output recommended connection circuit type when not used p70/ani0 to p77/ani7 20-a input/output input : connect to v dd0 or v ss0 output : leave open ano0, ano1 12 output leave open astb/clkout 4-b reset 2 input test 1-a directly connect to v ss0 av ref1 to av ref3 connect to v ss0 av ss av dd connect to v dd0 caution if the input/output mode is undefined for an input/output alternate-function pin, it should be connected to v dd0 via a resistor of several tens of k ? ? ? ? ? (especially when the reset input pin goes to the low-level input voltage or over upon powering on, and when input/output is switched by software.) remark the type numbers are standard for the 78k series, and therefore are not necessarily serial numbers within each product (there are non-incorporated circuits). chapter 2 pin functions 68 user? manual u11316ej4v1ud figure 2-1 pin input/output circuits p n in type 1-a v dd0 type 2 type 4-b type 8-c type 10-b type 2-c type 5-h type 12 type 20-a in schmitt-triggered input with hysteresis characteristics. schmitt-triggered input with hysteresis characteristics. push-pull output allowing output to be set to high impedance (p-ch & n-ch both off). p n data output disable out v dd0 p n data output disable in/out in/out v dd0 p pullup enable v dd0 p n data output disable in/out p pullup enable open drain v dd0 v dd0 p in pullup enable v dd0 p n data output disable in/out p pullup enable v dd0 v dd0 input enable p n out analog output voltage p n data output disable v dd0 input enable comparator p n av ref (threshold voltage) + - v ss0 v ss0 v ss0 v ss0 v ss0 av ss v ss0 chapter 2 pin functions 69 user s manual u11316ej4v1ud 2.4 cautions (1) when connecting unused pins, if the input/output mode is undefined for an input/output alternate-function pin, it should be connected to v dd0 with a resistor of several tens of k ? (especially when the reset input pin becomes the low-level input voltage or over upon powering on, and when input/output is switched by software.) (2) p60 to p63 of the pd784031 are in the output high-impedance state while the reset signal is input, but output a low level after the reset signal has been cleared. therefore, design the external circuit so that the low level may be output as the initial status. (3) in the pd78233 and 78237, the test pin is the mode pin and is fixed high. when changing over from the pd78233/ 78237, the circuitry must be modified so that this pin is directly connected to v ss0 . modification as shown below is needed if the pd78234/78238 was used with switching between the on-chip rom mode and rom-less mode performed by mode pin switching (the test pin must be directly connected to v ss0 ). modifications examples: incorporate all programs in rom store all programs in external rom change the location address of a program previously held in external rom, shift the address to avoid overlapping on- chip rom, and execute this program from the program in on-chip rom 70 user? manual u11316ej4v1ud chapter 3 cpu architecture 3.1 memory space the pd784038 can access a 1-mbyte memory space. the mapping of the internal data area (special function registers and internal ram) depends on the location instruction. a location instruction must be executed after reset release, and can only be used once. the program after reset release must be as follows: rstvct cseg at 0 dw rststrt to initseg cseg base rststrt: location 0h ; or location 0fh movg sp, #stkbgn chapter 3 cpu architecture 71 user? manual u11316ej4v1ud (1) when location 0h instruction is executed internal memory the internal data area and internal rom area are follows: parts number internal data area internal rom area pd784031 0f700h to 0ffffh pd784035 00000h to 0bfffh pd784036 00000h to 0f6ffh pd784037 0f100h to 0ffffh 00000h to 0f0ffh 10000h to 17fffh pd784038 0ee00h to 0ffffh 00000h to 0edffh pd78p4038 10000h to 1ffffh caution the following areas of the internal rom that overlap the internal data area cannot be used when the location 0h instruction is executed. parts number area that cannot be used pd784035 pd784036 0f700h to 0ffffh (2,304 bytes) pd784037 0f100h to 0ffffh (3,840 bytes) pd784038 0ee00h to 0ffffh (4,608 bytes) pd78p4038 external memory the external memory is accessed in the external memory expansion mode. (2) when location 0fh instruction is executed internal memory the internal data area and internal rom area are follows: parts number internal data area internal rom area pd784031 ff700h to fffffh pd784035 00000h to 0bfffh pd784036 00000h to 0ffffh pd784037 ff100h to fffffh 00000h to 17fffh pd784038 fee00h to fffffh 00000h to 1ffffh pd78p4038 external memory the external memory is accessed in the external memory expansion mode. chapter 3 cpu architecture 72 user? manual u11316ej4v1ud figure 3-1 pd784031 memory map notes 1. base area, reset or interrupt entry area, excluding internal ram in the case of reset. 2. 0fe31h (44 b) for the pd784031y. (256 bytes) special function registers (sfrs) external rom (63,232 bytes) internal ram (2,048 bytes) external memory (960 kbytes) general-purpose registers (128 bytes) data area (512 bytes) program/data area (1,536 bytes) callf entry area (2 kbytes) callt table area (64 bytes) vector table area (64 bytes) internal ram (2,048 bytes) external memory (997,120 bytes) (256 bytes) special function registers (sfrs) when location 0h instruction is executed when location 0fh instruction is executed macro service control word area (42 kbytes) 10000h 0ffffh 0f700h 0f6ffh 0ffdfh 0ffd0 h 0ff00 h 0feffh 0fd00 h 0fcffh fffffh 00800h 007ffh 0feff h ffeff h 0fe80 h 0fe7fh 0fe2fh 0fe06 h 0fd00 h 0fcffh 0f700h 00fffh 00080h 0007fh 00040h 0003fh 00000h ffe80 h ffe7f h ffe2f h ffe06 h ffd00 h ffcff h ff700h fffffh fffdf h fffd0 h fff00 h ffeff h ff700h ff6ff h 10000h 0ffffh 00000h note 1 00000h 00fffh note 1 note 2 note 2 chapter 3 cpu architecture 73 user s manual u11316ej4v1ud figure 3-2 accessed in external memory extension mode. 2. base area, reset or interrupt entry area, excluding internal ram in the case of reset. 3. 0fe31h (44 b) for the pd784035y. internal rom (48 kbytes) (256 bytes) special function registers (sfrs) external rom (14,080 bytes) internal ram (2,048 bytes) external memory note 1 (960 kbytes) general-purpose registers (128 bytes) data area (512 bytes) program/data area (1,536 bytes) callf entry area (2 kbytes) program/data area (48 bytes) callt table area (64 bytes) vector table area (64 bytes) internal ram (2,048 bytes) external memory (997,120 bytes) (256 bytes) special function registers (sfrs) internal rom (48 kbytes) when location 0h instruction is executed when location 0fh instruction is executed macro service control word area (42 kbytes) 10000h 0ffffh 0f700h 0f6ffh 0ffdfh 0ffd0 h 0ff00 h 0feffh 0c000h 0bfffh fffffh 00800h 007ffh 0feff h ffeff h 0fe80 h 0fe7fh 0fe2fh 0fe06 h 0fd00 h 0fcffh 0f700h 0bfffh 01000h 00fffh 00080h 0007fh 00040h 0003fh 00000h ffe80 h ffe7f h ffe2f h ffe06 h ffd00 h ffcff h ff700h fffffh fffdf h fffd0 h fff00 h ffeff h ff700h ff6ff h 10000h 0ffffh 0c000h 0bfffh 00000h 00000h note 1 note 1 note 3 note 3 note 1 note 1 note 2 note 2 chapter 3 cpu architecture 74 user s manual u11316ej4v1ud figure 3-3 accessed in external memory extension mode. 2. the 2,304 bytes of this area can be used as internal rom only when the location 0fh instruction is executed. 3. 63,232 bytes when the location 0h is executed, and 65,536 bytes when the location 0fh instruction is executed. 4. base area, reset or interrupt entry area, excluding internal ram in the case of reset. 5. 0fe31h (44b) for the pd784036y. (256 bytes) special function registers (sfrs) internal rom (63,232 bytes) internal ram (2,048 bytes) external memory (960 kbytes) internal rom (64 kbytes) when location 0h instruction is executed general-purpose registers (128 bytes) data area (512 bytes) program/data area (1,536 bytes) macro service control word area (42 bytes) callf entry area (2 kbytes) program/data area callt table area (64 bytes) vector table area (64 bytes) internal ram (2,048 bytes) external memory (980,736 bytes) (256 bytes) special function registers (sfrs) when location 0fh instruction is executed 10000h 0ffffh 0f700h 0f6ffh 0ffdfh 0ffd0 h 0ff00 h 0feffh fffffh 00800h 007ffh 0feff h ffeff h 0fe80 h 0fe7fh 0fe2fh 0fe06 h 0fd00 h 0fcffh 0f700h 01000h 00fffh 00080h 0007fh 00040h 0003fh 00000h ffe80 h ffe7f h ffe2f h ffe06 h ffd00 h ffcff h ff700h fffffh fffdf h fffd0 h fff00 h ffeff h ff700h ff6ff h 00000h 00000h 0f6ffh 10000h 0ffffh 0ffffh note 1 note 1 note 4 note 5 note 5 note 2 note 3 note 1 note 1 note 4 chapter 3 cpu architecture 75 user s manual u11316ej4v1ud figure 3-4 accessed in external memory extension mode. 2. the 3,840 bytes of this area can be used as internal rom only when the location 0fh instruction is executed. 3. 94,464 bytes when the location 0h is executed, and 98,304 bytes when the location 0fh instruction is executed. 4. base area, reset or interrupt entry area, excluding internal ram in the case of reset. 5. 0fe31h (44b) for the pd784037y. internal rom (32,768 bytes) (256 bytes) special function registers (sfrs) internal rom (61,696 bytes) internal ram (3,584 bytes) external memory (928 kbytes) internal rom (96 kbytes) when location 0h instruction is executed general-purpose registers (128 bytes) data area (512 bytes) program/data area (3,072 bytes) macro service control word area (42 bytes) callf entry area (2 kbytes) program/data area callt table area (64 bytes) vector table area (64 bytes) internal ram (3,584 bytes) external memory (946,432 bytes) (256 bytes) special function registers (sfrs) when location 0fh instruction is executed 18000h 17fffh 0f100h 0f0ffh 0ffdfh 0ffd0 h 0ff00 h 0feffh fffffh 00800h 007ffh 0feffh ffeff h 0fe80 h 0fe7fh 0fe2fh 0fe06 h 0fd00 h 0fcffh 0f100h 01000h 00fffh 00080h 0007fh 00040h 0003fh 00000h ffe80 h ffe7f h ffe2f h ffe06 h ffd00 h ffcff h ff100h fffffh fffdf h fffd0 h fff00 h ffeff h ff100h ff0ff h 00000h 00000h 0f0ffh 18000h 17fffh 17fffh 10000h 0ffffh 17fffh 10000h note 1 note 1 note 4 note 5 note 5 note 2 note 3 note 1 note 1 note 4 chapter 3 cpu architecture 76 user s manual u11316ej4v1ud figure 3-5 accessed in external memory extension mode. 2. the 4,608 bytes of this area can be used as internal rom only when the location 0fh instruction is executed. 3. 126,464 bytes when the location 0h is executed, and 131,072 bytes when the location 0fh instruction is executed. 4. base area, reset or interrupt entry area, excluding internal ram in the case of reset. 5. 0fe31h (44 b) for the pd784038y. internal rom (65,536 bytes) (256 bytes) special function registers (sfrs) internal rom (60,928 bytes) internal ram (4,352 bytes) external memory (896 kbytes) internal rom (128 kbytes) when location 0h instruction is executed general-purpose registers (128 bytes) data area (512 bytes) program/data area (3,840 bytes) macro service control word area (42 bytes) callf entry area (2 kbytes) program/data area callt table area (64 bytes) vector table area (64 bytes) internal ram (4,352 bytes) external memory (912,896 bytes) (256 bytes) special function registers (sfrs) when location 0fh instruction is executed 20000h 1ffffh 0ee00 h 0edff h 0ffdfh 0ffd0 h 0ff00 h 0feffh fffffh 00800h 007ffh 0feffh ffeff h 0fe80 h 0fe7fh 0fe2fh 0fe06 h 0fd00 h 0fcffh 0ee00 h 01000h 00fffh 00080h 0007fh 00040h 0003fh 00000h ffe80 h ffe7f h ffe2f h ffe06 h ffd00 h ffcff h fee00 h fffffh fffdf h fffd0 h fff00 h ffeff h fee00 h fedff h 00000h 00000h 0edff h 20000h 1ffffh 1ffffh 10000h 0ffffh 1ffffh 10000h note 1 note 1 note 4 note 5 note 5 note 2 note 3 note 1 note 1 note 4 chapter 3 cpu architecture 77 user? manual u11316ej4v1ud 3.2 internal rom area the pd784038 subseries products shown below incorporate rom which is used to store programs, table data, etc. if the internal rom area and internal data area overlap when the location 0h instruction is executed, the internal data area is accessed, and the overlapping part of the internal rom area cannot be accessed. product name internal rom address space location 0h instruction location 0fh instruction pd784035 48 k 8 bits 00000h to 0bfffh 00000h to 0bfffh pd784036 64 k 8 bits 00000h to 0f6ffh 00000h to 0ffffh pd784037 96 k 8 bits 00000h to 0f0ffh 00000h to 17fffh 10000h to 17fffh pd784038 128 k 8 bits 00000h to 0edffh 00000h to 1ffffh pd78p4038 10000h to 1ffffh the internal rom can be accessed at high speed. normally, fetches are performed at the same speed as external rom, but if the ifch bit of the memory extension mode register (mm) is set (to 1), the high-speed fetch function is used and interna l rom fetches are performed at high speed (2-byte fetch performed in 2 system clocks). when the instruction execution cycle equal to an external rom fetch is selected, wait insertion is performed by the wait function, but when high-speed fetches are used, wait insertion is not performed for internal rom. however, do not set external wait to the internal rom area. otherwise, the cpu may be in the deadlock status which can be cleared only by reset input. reset input sets the instruction execution cycle equal to the external rom fetch cycle. remark this address space of the pd784031 is in an external memory. chapter 3 cpu architecture 78 user s manual u11316ej4v1ud 3.3 base area the space from 0 to ffffh comprises the base area. the base area is the object for the following uses: reset entry address interrupt entry address callt instruction entry address 16-bit immediate addressing mode (with instruction address addressing) 16-bit direct addressing mode 16-bit register addressing mode (with instruction address addressing) 16-bit register indirect addressing mode short direct 16-bit memory indirect addressing mode the vector table area, callt instruction table area and callf instruction entry area are allocated to the base area. when the location 0h instruction is executed, the internal data area is located in the base area. note that, in the internal data area, program fetches cannot be performed from the internal high-speed ram area or special function register (sfr) area. also, internal ram area data should only be used after initialization has been performed. 3.3.1 vector table area the 64-byte area from 00000h to 0003fh is reserved as the vector table area. the vector table area stores the program start addresses used when a branch is made as the result of reset input or generation of an interrupt request. when context switching is used by an interrupt, the number of the register bank to be switched to is stored here. any portion not used as the vector table can be used as program memory or data memory. 16-bit values can be written to the vector table. therefore, branches can only be made within the base area. chapter 3 cpu architecture 79 user s manual u11316ej4v1ud table 3-1 vector table vector table address interrupt cause 0003ch operand error 0003eh brk 00000h reset (reset input) 00002h nmi 00004h wdt 00006h intp0 00008h intp1 0000ah intp2 0000ch intp3 0000eh intc00 00010h intc01 00012h intc10 00014h intc11 00016h intc20 00018h intc21 0001ah intc30 0001ch intp4 0001eh intp5 00020h intad 00022h intser1 00024h intsr1/intcsi1 00026h intst1 00028h intcsi 0002ah intser2 0002ch intsr2/intcsi2 0002eh intst2 00030h intspc note note pd784038y subseries only 3.3.2 callt instruction table area the 1-byte call instruction (callt) subroutine entry addresses can be stored in the 64-byte area from 00040h to 0007fh. the callt instruction references this table, and branches to a base area address written in the table as a subroutine. as the callt instruction is one byte in length, use of the callt instruction for subroutine calls written frequently throughout th e program enables the program object size to be reduced. the table can contain up to 32 subroutine entry addresses, and therefore it is recommended that they be recorded in order of frequency. if this area is not used as the callt instruction table, it can be used as ordinary program memory or data memory. 3.3.3 callf instruction entry area a subroutine call can be made directly to the area from 00800h to 00fffh with the 2-byte call instruction (callf). as the callf instruction is a two-byte call instruction, it enables the object size to be reduced compared with use of the dire ct subroutine call call instruction (3 or 4 bytes). writing subroutines directly in this area is an effective means of exploiting the high-speed capability of the device. if you wish to reduce the object size, writing an unconditional branch (br) instruction in this area and locating the subroutin e itself outside this area will result in a reduced object size for subroutines that are called from five or more points. in thi s case, only the 4 bytes of the br instruction are occupied in the callf entry area, enabling the object size to be reduced with a larg e number of subroutines. chapter 3 cpu architecture 80 user s manual u11316ej4v1ud 3.4 internal data area the internal data area consists of the internal ram area and special function register area (see figures 3-1 to 3-5 ). the final address of the internal data area can be specified by means of the location instruction as either 0ffffh (when a location 0h instruction is executed) or fffffh (when a location 0fh instruction is executed). selection of the addresses of the internal data area by means of the location instruction must be executed once immediately after reset release, and once the selection is made, it cannot be changed. the program after reset release must be as shown in the example below. if the internal data area and another area are allocated to the same addresses, the internal data area is accessed and the other area cannot be accessed. example rstvct cseg at 0 dw rststrt to initseg cseg base rststrt: location 0h ; or location 0fh movg sp, #stkbgn caution when the location 0h instruction is executed, it is necessary to ensure that the program after reset release does not overlap the internal data area. it is also necessary to make sure that the entry addresses of the service routines for non-maskable interrupts such as nmi do not overlap the internal data area. also, initialization must be performed for maskable interrupt entry areas, etc., before the internal data area is referenced. 3.4.1 internal ram area the pd784038 incorporates general-purpose static ram. this area is configured as follows: peripheral ram (pram) internal ram area internal high-speed ram (iram) table 3-2 internal ram area internal ram internal ram area product name peripheral ram: pram internal high-speed ram: iram pd784031 2,048 bytes 1,536 bytes 512 bytes pd784035 (0f700h to 0feffh) (0f700h to 0fcffh) (0fd00h to 0feffh) pd784036 pd784037 3,584 bytes 3,072 bytes (0f100h to 0feffh) (0f100h to 0fcffh) pd784038 4,352 bytes 3,840 bytes pd78p4038 (0ee00h to 0feffh) (0ee00h to 0fcffh) remark the addresses in the table are the values that apply when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values shown above. chapter 3 cpu architecture 81 user s manual u11316ej4v1ud the internal ram memory map is shown in figure 3-6. figure 3-6 internal ram memory map 00feffh 00fe80h 00fe2fh note 1 00fe06h 00fe00h 00fdffh peripheral ram internal high-speed ram macro service control word area general-purpose register area short direct addressing 1 permissible range short direct addressing 2 permissible range 00fd20h 00fd1fh 00fd00h 00fcffh differs depending on product note 2 notes 1. 00fe31h for pd784038y subseries. 2. pd784031, 784035, 784036 : 00f700h pd784037 : 00f100h pd784038, 78p4038 : 00ee00h remark the addresses in the figure are the values that apply when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values shown above. chapter 3 cpu architecture 82 user s manual u11316ej4v1ud (1) internal high-speed ram (iram) the internal high-speed ram (iram) allows high-speed accesses to be made. the short direct addressing mode for high- speed accesses can be used on fd20h to feffh in this area. there are two kinds of short direct addressing mode, short direct addressing 1 and short direct addressing 2, according to the target address. the function is the same in both of these addressing modes. with some instructions, the word length is shorter with short direct addressing 2 than with short direct addressing 1. see the 78k/iv series user s manual instruction volume for details. a program fetch cannot be performed from iram. if a program fetch is performed from an address onto which iram is mapped, cpu inadvertent loop will result. the following areas are reserved in iram. general-purpose register area : fe80h to feffh macro service control word area : fe06h to fe2fh (excluding 0fe22h, 0fe23h, 0fe2ah, 0fe2bh) macro service channel area : fe00h to feffh (the address is specified by the macro service control word) if the reserved function is not used in these areas, they can be used as ordinary data memory. remark the addresses in this text are those that apply when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values shown in the text. (2) peripheral ram (pram) the peripheral ram (pram) is used as ordinary program memory or data memory. when used as program memory, the program must be written to the peripheral ram beforehand by a program. program fetches from peripheral ram are fast, with a 2-byte fetch being executed in 2 clocks. 3.4.2 special function register (sfr) area the on-chip peripheral hardware special function registers (sfrs) are mapped onto the area from 0ff00h to 0ffffh (see figures 3-1 to 3-5 ). the area from 0ffd0h to 0ffdfh is mapped as an external sfr area, and allows externally connected peripheral i/os, etc., to be accessed in external memory extension mode (specified by the memory extension mode register (mm)) by the rom- less product or on-chip rom products. caution addresses onto which sfrs are not mapped should not be accessed in this area. if such an address is accessed by mistake, the cpu may become deadlocked. a deadlock can only be released by reset input. remark the addresses in this text are those that apply when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values shown in the text. 3.4.3 external sfr area in pd784038 subseries products, the 16-byte area from 0ffd0h to 0ffdfh in the sfr area (when the location 0h is executed; 0fffd0h to 0fffdfh when the location 0fh instruction is executed) is mapped as an external sfr area. when the external memory extension mode is set in a rom-less product or on-chip rom product, externally connected peripheral i/os, etc., can be accessed using the address bus or address/data bus, etc. as the external sfr area can be accessed by sfr addressing, peripheral i/o and similar operations can be performed easily, the object size can be reduced, and macro service can be used. bus operations for accesses to the external sfr area are performed in the same way as for ordinary memory accesses. chapter 3 cpu architecture 83 user s manual u11316ej4v1ud 3.5 external memory space the external memory space is a memory space that can be accessed in accordance with the setting of the memory extension mode register (mm). it can store programs, table data, etc., and can have peripheral i/o devices allocated to it. 3.6 the pd78p4038 incorporates 128-kbyte internal rom and 4,352-byte internal ram. therefore, the memory mapping of the pd78p4038 is slightly different from that of the pd784035, 784036, and 784037. in order to mask this difference, the pd78p4038 has a function (the memory size switching function) which prevents part of the internal memory from being used by software. memory size switching is performed by means of the internal memory size switching register (ims). to make the memory mapping of the pd78p4038 the same as that of the pd784035, 784036, and 784037, be sure to write this register immediately after reset. do not change the written value. the ims can be written to with an 8-bit manipulation instruction. the ims format is shown in figure 3-7 . reset input sets the ims register to ffh. figure 3-7 internal memory size switching register (ims) format 7 ims7 ims 6 ims6 5 ims5 4 ims4 3 ims3 2 ims2 1 ims1 0 ims0 address 0fffch after reset ffh r/w r/w ims0 to 7 memory size same as pd784038 same as pd784037 ffh eeh same as pd784036 same as pd784035 dch cch ims is not provided to the pd784035, 784036, 784037, and 784038. however, the operation is not affected even if an instruction to write ims is executed with these models. caution if the chapter 3 cpu architecture 84 user s manual u11316ej4v1ud 3.7 control registers control registers consist of the program counter (pc), program status word (psw), and stack pointer (sp). 3.7.1 program counter (pc) this is a 20-bit binary counter that holds address information on the next program to be executed (see figure 3-8 ). normally, the pc is incremented automatically by the number of bytes in the fetched instruction. when an instruction associated with a branch is executed, the immediate data or register contents are set in the pc. upon reset input, the 16-bit data in address 0 and 1 is set in the low-order 16 bits, and 0000 in the high-order 4 bits of the pc. figure 3-8 program counter (pc) format 19 pc 0 3.7.2 program status word (psw) the program status word (psw) is a 16-bit register comprising various flags that are set or reset according to the result of instruction execution. read accesses and write accesses are performed in high-order 8-bit (pswh) and low-order 8-bit (pswl) units. individual flags can be manipulated by bit-manipulation instructions. the contents of the psw are automatically saved to the stack when a vectored interrupt request is acknowledged or a brk instruction is executed, and automatically restored when an reti or retb instruction is executed. when context switching is used, the contents are automatically saved in rp3, and automatically restored when an retcs or retcsb instruction is executed. reset input resets (to 0) all bits. 0 must always be written to the bits written as 0 in figure 3-9 . the contents of bits written as - are undefined when read. figure 3-9 program status word (psw) format 7 uf pswh symbol 6 rbs2 5 rbs1 4 rbs0 3 2 1 0 7 s pswl 6 z 5 rss 4 ac 3 ie 2 p/v 1 0 0 cy the flags are described below. (1) carry flag (cy) the carry flag records a carry or borrow resulting from an operation. this flag also records the shifted-out value when a shift/rotate instruction is executed, and functions as a bit accumulator when a bit-manipulation instruction is executed. the status of the cy flag can be tested with a conditional branch instruction. chapter 3 cpu architecture 85 user s manual u11316ej4v1ud (2) parity/overflow flag (p/v) the p/v flag performs the following two kinds of operation associated with execution of an operation instruction. the status of the p/v flag can be tested with a conditional branch instruction. parity flag operation set (to 1) when the number of bits set (to 1) as the result of execution of a logical operation instruction, shift/rotate instruction, or a chkl or chkla instruction is even, and reset (to 0) if odd. when a 16-bit shift instruction is executed, however, only the low-order 8 bits of the operation result are valid for the parity flag. overflow flag operation set (to 1) only when the numeric range expressed as a two s complement is exceeded as the result of execution of a arithmetic operation instruction, and reset (to 0) otherwise. more specifically, the value of this flag is the exclusive or of the carry into the msb and the carry out of the msb. for example, the two s complement range in an 8-bit arithmetic operation is 80h ( 128) to 7fh (+127), and the flag is set (to 1) if the operation result is outside this range, and reset (to 0) if within this range. example the operation of the overflow flag when an 8-bit addition instruction is executed is shown below. when the addition of 78h (+120) and 69h (+105) is performed, the operation result is e1h (+225), and the two s complement limit is exceeded, with the result that the p/v flag is set (to 1). expressed as a two s complement, e1h is -31. 78h (+120) = 0,111 1,000 +) 69h (+105) = +) 0,110 1,001 0 1,110 0,001 = 31 p/v = 1 cy when the following two negative numbers are added together, the operation result is within the two s complement range, and therefore the p/v flag is reset (to 0). fbh ( 5) = 1,111 1,011 +) f0h ( 16) = +) 1,111 0,000 1 1,110 1,011 = 21 p/v = 0 cy (3) interrupt request enable flag (ie) this flag controls cpu interrupt request acknowledgment operations. when 0 , interrupts are disabled, and only non-maskable interrupts and unmasked macro service can be acknowledged. all other interrupts are disabled. when 1 , the interrupt enabled state is set, and enabling of interrupt request acknowledgment is controlled by the interrupt mask flags corresponding to the individual interrupt requests and the priority of the individual interrupts. the ie flag is set (to 1) by execution of an ei instruction, and reset (to 0) by execution of a di instruction or acknowledgmen t of an interrupt. (4) auxiliary carry flag (ac) the ac flag is set (to 1) when there is a carry out of bit 3 or a borrow into bit 3 as the result of an operation, and reset (t o 0) otherwise. this flag is used when the adjba or adjbs instruction is executed. chapter 3 cpu architecture 86 user s manual u11316ej4v1ud (5) register set selection flag (rss) the rss flag specifies the general-purpose registers that function as x, a, c, and b, and the general-purpose register pairs (16-bit) that function as ax and bc. this flag is provided to maintain compatibility with the 78k/iii series, and must be set to 0 except when using a 78k/iii serie s program. (6) zero flag (z) the z flag records the fact that the result of an operation is 0 . it is set (to 1) when the result of an operation is 0 , and reset (to 0) otherwise. the status of the z flag can be tested with a conditional branch instruction. (7) sign flag (s) the s flag records the fact that the msb is 1 as the result of an operation. it is set (to 1) when the msb is 1 as the result of an operation, and reset (to 0) otherwise. the status of the s flag can be tested with a conditional branch instruction. (8) register bank selection flag (rbs0 to rbs2) this is a 3-bit flag used to select one of the 8 register banks (register bank 0 to register bank 7) (see table 3-3 ). it stores 3-bit information which indicates the register bank selected by execution of a sel rbn instruction, etc. table 3-3 register bank selection rbs2 rbs1 rbs0 specified register bank 0 0 0 register bank 0 0 0 1 register bank 1 0 1 0 register bank 2 0 1 1 register bank 3 1 0 0 register bank 4 1 0 1 register bank 5 1 1 0 register bank 6 1 1 1 register bank 7 (9) user flag (uf) this flag can be set and reset in the user program, and used for program control. chapter 3 cpu architecture 87 user s manual u11316ej4v1ud 3.7.3 use of rss bit basically, the rss bit should be fixed at 0 at all times. the following explanation refers to the case where a 78k/iii series program is used, and the program used sets the rss bit to 1. this explanation can be skipped if the rss bit is fixed at 0. the rss bit is provided to allow the functions of a (r1), x (r0), b (r3), c (r2), ax (rp0), and bc (rp1) to be used by register s r4 to r7 (rp2, rp3) as well. effective use of this bit enables efficient programs to be written in terms of program size and program execution. however, careless use can result in unforeseen problems. therefore, the rss bit should always be set to 0. the rss bit should only be set to 1 when a 78k/iii series program is used. use of the rss bit set to 0 in all programs will improve programming and debugging efficiency. even when using a program in which the rss bit set to 1 is used, it is recommended that the program be amended if possible so that it does not set the rss bit to 1. (1) rss bit specification registers used by instructions for which the a, x, b, c, and ax registers are directly entered in the operand column of the operation list (see 27.2. ) registers specified as implied by instructions that use the a, ax, b, and c registers by means of implied addressing registers used in addressing by instructions that use the a, b, and c registers in indexed addressing and based indexed addressing the registers used in these cases are switched as follows according to the rss bit. when rss = 0 a r1, x r0, b r3, c r2, ax rp0, bc rp1 when rss = 1 a r5, x r4, b r7, c r6, ax rp2, bc rp3 chapter 3 cpu architecture 88 user? manual u11316ej4v1ud registers used other than those mentioned above are always the same irrespective of the value of the rss bit. with the nec electronics assembler (ra78k4), the register operation code generated when the a, x, b, c, ax, and bc registers are described by those names is determined by the assembler rss pseudo-instruction. when the rss bit is set or reset, an rss pseudo-instruction must be written immediately before (or immediately after) the relevant instruction (see example below). chapter 3 cpu architecture 89 user s manual u11316ej4v1ud (3) operating precautions switching the rss bit has the same effect as having two register sets. however, when writing a program, care must be taken to ensure that the static program description and dynamic rss bit changes at the time of program execution always coincide. also, a program that sets rss to 1 cannot be used by a program that uses the context switching function, and therefore program usability is poor. moreover, since different registers are used with the same name, program readability is poor and debugging is difficult. therefore, if it is necessary to set rss to 1, these disadvantages must be fully taken into considerat ion when writing a program. a register not specified by the rss bit can be accessed by writing its absolute name. 3.7.4 stack pointer (sp) the stack pointer is a 24-bit register that holds the start address of the stack area (lifo type: 00000h to ffffffh) (see figure 3-10 ). it is used to address the stack area when subroutine processing or interrupt servicing is performed. be sure to write 0 in the high-order 4 bits. the contents of the sp are decremented before a write to the stack area and incremented after a read from the stack area (see figures 3-11 and 3-12 ). the sp is accessed by dedicated instructions. the sp contents are undefined after reset input, and therefore the sp must always be initialized by an initialization program directly after reset release (before a subroutine call or interrupt acknowledgment). example sp initialization movg sp, #0fee0h; sp 0fee0h (when used from fedfh) figure 3-10 stack pointer (sp) format 23 sp 0 chapter 3 cpu architecture 90 user s manual u11316ej4v1ud figure 3-11 data saved to stack area push sfr instruction stack push sfrp instruction stack upper byte lower byte upper byte undefined undefined pc15 to pc8 pc7 to pc0 pc15 to pc8 pc7 to pc0 pc19 to pc16 pc19 to pc16 pswh 7 to pswh 4 pswh 7 to pswh 4 pswl pswl r7 r6 r5 r4 rp3 rp2 ax a x middle byte lower byte push rg instruction stack push psw instruction stack call, callf, callt instruction stack vectored interrupt stack push post, pushu post instruction (in case of push ax, rp2, rp3) stack sp sp 1 sp sp 1 sp sp 1 sp 2 sp sp 2 sp sp 1 sp 2 sp sp 2 sp sp 1 sp 2 sp 3 sp sp 3 sp sp 1 sp 2 sp 3 sp sp 3 sp sp 1 sp 2 sp 3 sp 4 sp sp 4 sp sp 1 sp 2 sp 3 sp 4 sp 5 sp 6 sp sp 6 ? ? ? ? ? ? ? ? ? chapter 3 cpu architecture 91 user? manual u11316ej4v1ud figure 3-12 data restored from stack area pop sfr instruction stack pop sfrp instruction stack upper byte lower byte upper byte note note pc15 to pc8 pc7 to pc0 pc15 to pc8 pc7 to pc0 pc19 to pc16 pc19 to pc16 pswh 7 to pswh 4 pswh 7 to pswh 4 pswl pswl r7 r6 r5 r4 rp3 rp2 ax a x middle byte lower byte pop rg instruction stack pop psw instruction stack ret instruction stack reti, retb instruction stack pop post, popu post instruction (in case of pop ax, rp2, rp3) stack sp sp + 1 sp + 1 sp sp sp + 2 sp + 1 sp sp sp + 3 sp + 2 sp + 1 sp sp sp + 3 sp + 2 sp + 1 sp sp sp + 4 sp + 3 sp + 2 sp + 1 sp sp sp + 6 sp + 5 sp + 4 sp + 3 sp + 2 sp + 1 sp sp sp + 2 sp + 1 sp ? ? ? ? ? ? ? ? ? note this 4-bit data is ignored. cautions 1. with stack addressing, the entire 1-mbyte space can be accessed but a stack area cannot be reserved in the sfr area or internal rom area. 2. the stack pointer (sp) is undefined after reset input. moreover, non-maskable interrupts can still be acknowledged when the sp is in an undefined state. an unanticipated operation may therefore be performed if a non-maskable interrupt request is generated when the sp is in the undefined state directly after reset release. to avoid this risk, the program after reset release must be written as follows. rstvct cseg at 0 dw rststrt to initseg cseg base rststrt : location 0h ; or location 0fh movg sp, #stkbgn chapter 3 cpu architecture 92 user s manual u11316ej4v1ud 3.8 general registers 3.8.1 configuration there are sixteen 8-bit general-purpose registers, and two 8-bit general-purpose registers can be used together as a 16-bit general-purpose register. in addition, four of the 16-bit general-purpose registers can be combined with an 8-bit register for address extension, and used as 24-bit address specification registers. general-purpose registers other than the v, u, t, and w registers for address extension are mapped onto internal ram. these register sets are provided in 8 banks, and can be switched by means of software or the context switching function. upon reset input, register bank 0 is selected. the register bank used during program execution can be checked by reading the register bank selection flag (rbs0, rbs1, rbs2) in the psw. figure 3-13 general-purpose register format 7070 a (r1) x (r0) ax (rp0) b (r3) c (r2) bc (rp1) r5 r4 rp2 r7 r6 rp3 r9 r8 vp (rp4) v vvp (rg4) r11 r10 up (rp5) u uup (rg5) d (r13) e (r12) de (rp6) t tde (rg6) h (r15) l (r14) hl (rp7) w whl (rg7) 0 23 15 8 banks remark absolute names are shown in parentheses. chapter 3 cpu architecture 93 user s manual u11316ej4v1ud figure 3-14 general-purpose register addresses rbnk0 feffh note fe80h note rbnk1 rbnk2 rbnk3 rbnk4 rbnk5 rbnk6 rbnk7 h (r15) (fh) 8-bit processing 16-bit processing d (r13) (dh) r11 (bh) r9 (9h) r7 (7h) r5 (5h) b (r3) (3h) a (r1) (1h) 77 0 0 15 0 l (r14) (eh) e (r12) (ch) r10 (ah) r8 (8h) r6 (6h) r4 (4h) c (r2) (2h) x (r0) (0h) hl (rp7) (eh) de (rp6) (ch) up (rp5) (ah) vp (rp4) (8h) rp3 (6h) rp2 (4h) bc (rp1) (2h) ax (rp0) (0h) note when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the address values shown above. caution r4, r5, r6, r7, rp2, and rp3 can be used as the x, a, c, b, ax, and bc registers respectively by setting the rss bit of the psw to 1, but this function should only be used when using a 78k/iii series program. remark when the register bank is changed, and it is necessary to return to the original register bank, an sel rbn instruction should be executed after saving the psw to the stack with a push psw instruction. when returning to the original register bank, if the stack location does not change the pop psw instruction should be used. when the register bank is changed by a vectored interrupt service program, etc., the psw is automatically saved to the stack when an interrupt is acknowledged and restored by an reti or retb instruction, so that, if only one register bank is used in the interrupt service routine, only an sel rbn instruction needs be executed, and execution of a push psw and pop psw instruction is not necessary. example when register bank 2 is specified push psw sel rb2 operations in register bank 2 pop psw operations in original register bank ? ? ? ? ? ? ? ...... ...... ...... chapter 3 cpu architecture 94 user s manual u11316ej4v1ud 3.8.2 functions in addition to being manipulated in 8-bit units, the general-purpose registers can also be manipulated in 16-bit units by pairi ng two 8-bit registers. also, four of the 16-bit registers can be combined with an 8-bit register for address extension and manip ulated in 24-bit units. each register can be used in a general-purpose way for temporary storage of an operation result and as the operand of an inter-register operation instruction. the area from 0fe80h to 0feffh (when the location 0h instruction is executed; 0ffe80h to 0ffeffh when the location 0fh instruction is executed) can be given an address specification and accessed as ordinary data memory irrespective of whether or not it is used as the general-purpose register area. as 8 register banks are provided in the 78k/iv series, efficient programs can be written by using different register banks for normal processing and processing in the event of an interrupt. the registers have the following specific functions. a (r1): register mainly used for 8-bit data transfers and operation processing. can be used in combination with all addressing modes for 8-bit data. can also be used for bit data storage. can be used as the register that stores the offset value in indexed addressing and based indexed addressing. x (r0): can be used for bit data storage. ax (rp0): register mainly used for 16-bit data transfers and operation processing. can be used in combination with all addressing modes for 16-bit data. axde: used for 32-bit data storage when a divux, macw, or macsw instruction is executed. b (r3): has a loop counter function, and can be used by the dbnz instruction. can be used as the register that stores the offset value in indexed addressing and based indexed addressing. used as the macw and macsw instruction data pointer. c (r2): has a loop counter function, and can be used by the dbnz instruction. can be used as the register that stores the offset value in based indexed addressing. used as the counter in a string instruction and the sacw instruction. used as the macw and macsw instruction data pointer. rp2: used to save the low-order 16 bits of the program counter (pc) when context switching is used. rp3: used to save the high-order 4 bits of the program counter (pc) and the program status word (psw) (excluding bits 0 to 3 of pswh) when context switching is used. chapter 3 cpu architecture 95 user s manual u11316ej4v1ud vvp (rg4): has a pointer function, and operates as the register that specifies the base address in register indirect addressing, based addressing and based indexed addressing. uup (rg5): has a user stack pointer function, and enables a stack separate from the system stack to be implemented by means of the pushu and popu instructions. has a pointer function, and operates as the register that specifies the base address in register indirect addressing and based addressing. de (rp6), hl (rp7): operate as the registers that store the offset value in indexed addressing and based indexed addressing. tde (rg6): has a pointer function, and operates as the register that specifies the base address in register indirect addressing and based addressing. used as the pointer in a string instruction and the sacw instruction. whl (rg7): register used mainly for 24-bit data transfers and operation processing. has a pointer function, and operates as the register that specifies the base address in register indirect addressing and based addressing. used as the pointer in a string instruction and the sacw instruction. chapter 3 cpu architecture 96 user s manual u11316ej4v1ud in addition to the function name that emphasizes the specific function of the register (x, a, c, b, e, d, l, h, ax, bc, vp, up, de, hl, vvp, uup, tde, whl), each register can also be described by its absolute name (r0 to r15, rp0 to rp7, rg4 to rg7). the correspondence between these names is shown in table 3-4. table 3-4 correspondence between function names and absolute names note rss should only be set to 1 when a 78k/iii series program is used. remark r8 to r11 have no function name. (a) 8-bit registers absolute name function name rss = 0 rss = 1 note r0 x r1 a r2 c r3 b r4 x r5 a r6 c r7 b r8 r9 r10 r11 r12 e e r13 d d r14 l l r15 h h (b) 16-bit registers absolute name function name rss = 0 rss = 1 note rp0 ax rp1 bc rp2 ax rp3 bc rp4 vp vp rp5 up up rp6 de de rp7 hl hl (c) 24-bit registers absolute name function name rg4 vvp rg5 uup rg6 tde rg7 whl chapter 3 cpu architecture 97 user? manual u11316ej4v1ud 3.9 special function registers (sfrs) these are registers to which a special function is assigned, such as on-chip peripheral hardware mode registers, control registers, etc. they are mapped onto the 256-byte space from 0ff00h to 0ffffh note . note when the location 0h instruction is executed. when the location 0fh instruction is executed, the area is fff00h to fffffh. caution addresses onto which sfrs are not assigned should not be accessed in this area. if such an address is as accessed by mistake, the pd784038 may become deadlocked. a deadlock can only be released by reset input. a list of special function registers (sfrs) is given in table 3-5. the meaning of the items in the table is as explained below . symbol ............................... symbol that indicates the incorporated sfr. this is a reserved word in the nec electroni cs assembler (ra78k4). with the c compiler (cc78k4), this symbol can be used as an sfr variable by means of a #pragma sfr command. r/w .................................... indicates whether the corresponding sfr is read/write enabled. r/w: read/write enabled r : read-only w : write-only manipulable bit units ......... indicates the applicable manipulation bit units when the corresponding sfr is manipulated. a 16-bit-manipulable sfr can be written in the operand ?frp? and when specified by an address, an even address is specified. a bit-manipulable sfr can be written in a bit manipulation instruction. after reset ......................... indicates the status of the register after reset input. chapter 3 cpu architecture 98 user s manual u11316ej4v1ud table 3-5 list of special function registers (sfrs) (1/4) address special function register (sfr) name symbol r/w manipulable bit units after reset 1 bit 8 bits 16 bits 0ff00h port 0 p0 r/w ? undefined 0ff01h port 1 p1 ? 0ff02h port 2 p2 r ? 0ff03h port 3 p3 r/w ? 0ff04h port 4 note 2 p4 ? 0ff05h port 5 note 2 p5 ? 0ff06h port 6 p6 ? 00h 0ff07h port 7 p7 ? undefined 0ff0eh port 0 buffer register p0l ? 0ff0fh port 0 buffer register h p0h ? 0ff10h compare register (timer/counter 0) cr00 0ff12h capture/compare register (timer/counter 0) cr01 0ff14h compare register l (timer/counter 1) cr10 cr10w ? 0ff15h compare register h (timer/counter 1) 0ff16h capture/compare register l (timer/counter 1) cr11 cr11w ? 0ff17h capture/compare register h (timer/counter 1) 0ff18h compare register l (timer/counter 2) cr20 cr20w ? 0ff19h compare register h (timer/counter 2) 0ff1ah capture/compare register l (timer/counter 2) cr21 cr21w ? 0ff1bh capture/compare register h (timer/counter 2) 0ff1ch compare register l (timer 3) cr30 cr30w ? 0ff1dh compare register h (timer 3) 0ff20h port 0 mode register pm0 ? ffh 0ff21h port 1 mode register pm1 ? 0ff23h port 3 mode register pm3 ? 0ff24h port 4 mode register note 2 pm4 ? 0ff25h port 5 mode register note 2 pm5 ? 0ff26h port 6 mode register pm6 ? 0ff27h port 7 mode register pm7 ? 0ff2eh real-time output port control register rtpc ? 00h 0ff30h capture/compare control register 0 crc0 10h 0ff31h timer output control register toc ? 00h 0ff32h capture/compare control register 1 crc1 0ff33h capture/compare control register 2 crc2 10h notes 1. when the location 0h instruction is executed. when the location 0fh instruction is executed, f0000h should be added to the value shown. 2. not provided to the pd784031. note 1 chapter 3 cpu architecture 99 user? manual u11316ej4v1ud table 3-5 list of special function registers (sfrs) (2/4) address special function register (sfr) name symbol r/w manipulable bit units after reset 1 bit 8 bits 16 bits 0ff36h capture register (timer/counter 0) cr02 r 0000h 0ff38h capture register l (timer/counter 1) cr12 cr12w ? 0ff39h capture register h (timer/counter 1) 0ff3ah capture register l (timer/counter 2) cr22 cr22w ? 0ff3bh capture register h (timer/counter 2) 0ff41h port 1 mode control register pmc1 r/w ? 00h 0ff43h port 3 mode control register pmc3 ? 0ff4eh pull-up resistor option register puo ? 0ff50h timer register 0 tm0 note 3 r 0000h 0ff51h 0ff52h timer register 1 tm1 note 3 tm1w note 3 ? 0ff53h 0ff54h timer register 2 tm2 note 3 tm2w note 3 ? 0ff55h 0ff56h timer register 3 tm3 note 3 tm3w note 3 ? 0ff57h 0ff5ch prescaler mode register 0 prm0 r/w 11h 0ff5dh timer control register 0 tmc0 ? 00h 0ff5eh prescaler mode register 1 prm1w 11h 0ff5fh timer control register 1 tmc1 ? 00h 0ff60h d/a conversion value setting register 0 dacs0 0ff61h d/a conversion value setting register 1 dacs1 0ff62h d/a converter mode register dam 03h 0ff68h a/d converter mode register adm ? 00h 0ff6ah a/d conversion result register adcr r undefined 0ff70h pwm control register pwmc r/w ? 05h 0ff71h pwm prescaler register pwpr 00h 0ff72h pwm modulo register 0 pwm0 undefined 0ff74h pwm modulo register 1 pwm1 0ff7dh one-shot pulse output control register ospc ? 00h 0ff80h i 2 c bus control register iicc ? 0ff81h prescaler mode register for serial clock sprm 04h 0ff82h clocked serial interface mode register csim ? 00h 0ff83h slave address register sva r/w note 5 01h notes 1. when the location 0h instruction is executed. when the location 0fh instruction is executed, ?0000h should be added to the value shown. 2. pd784038y subseries only. 3. use of tm0, tm1/tm1w, tm2/tm2w, and tm3/tm3w is limited. for details, refer to (7) in 3.10 cautions . 4. bit 0 is read-only. 5. only bit 0 can be manipulated. note 1 note 2 note 4 chapter 3 cpu architecture 100 user? manual u11316ej4v1ud table 3-5 list of special function registers (sfrs) (3/4) address special function register (sfr) name symbol r/w manipulable bit units after reset 1 bit 8 bits 16 bits 0ff84h clocked serial interface mode register 1 csim1 r/w ? 00h 0ff85h clocked serial interface mode register 2 csim2 ? 0ff86h serial shift register sio undefined 0ff88h asynchronous serial interface mode register asim ? 00h 0ff89h asynchronous serial interface mode register 2 asim2 ? 0ff8ah asynchronous serial interface status register asis r ? 0ff8bh asynchronous serial interface status register 2 asis2 ? 0ff8ch receive buffer: uart0 rxb undefined transmit shift register: uart0 txs w shift register: ioe1 sio1 r/w 0ff8dh receive buffer: uart2 rxb2 r undefined transmit shift register: uart2 txs2 w shift register: ioe2 sio2 r/w 0ff90h baud rate generator control register brgc 00h 0ff91h baud rate generator control register 2 brgc2 0ffa0h external interrupt mode register 0 intm0 ? 0ffa1h external interrupt mode register 1 intm1 ? 0ffa4h sampling clock selection register scs0 0ffa8h in-service priority register ispr r ? 0ffaah interrupt mode control register imc r/w ? 80h 0ffach interrupt mask register 0l mk0l mk0 ? ffffh 0ffadh interrupt mask register 0h mk0h ? 0ffaeh interrupt mask register 1l mk1l ? ffh 0ffc0h standby control register stbc note 2 30h 0ffc2h watchdog timer mode register wdm note 2 00h 0ffc4h memory extension mode register mm ? 20h 0ffc5h hold mode register hldm ? 00h 0ffc6h clock output mode register clom ? 0ffc7h programmable wait control register 1 pwc1 aah 0ffc8h programmable wait control register 2 pwc2 aaaah 0ffcch refresh mode register rfm ? 00h notes 1. when the location 0h instruction is executed. when the location 0fh instruction is executed, ?0000h should be added to the value shown. 2. the write operation is possible by using the dedicated instruction ?ov stbc, #byte?or ?ov wdm, #byte only. instructions other than these cannot perform the write operation. note 1 chapter 3 cpu architecture 101 user? manual u11316ej4v1ud table 3-5 list of special function registers (sfrs) (4/4) address special function register (sfr) name symbol r/w manipulable bit units after reset 1 bit 8 bits 16 bits 0ffcdh refresh area specification register rfa r/w ? 00h 0ffceh oscillation stabilization time specification register osts 0ffd0h to external sfr area ? 0ffdfh 0ffe0h interrupt control register (intp0) pic0 ? 43h 0ffe1h interrupt control register (intp1) pic1 ? 0ffe2h interrupt control register (intp2) pic2 ? 0ffe3h interrupt control register (intp3) pic3 ? 0ffe4h interrupt control register (intc00) cic00 ? 43h 0ffe5h interrupt control register (intc01) cic01 ? 0ffe6h interrupt control register (intc10) cic10 ? 0ffe7h interrupt control register (intc11) cic11 ? 0ffe8h interrupt control register (intc20) cic20 ? 0ffe9h interrupt control register (intc21) cic21 ? 0ffeah interrupt control register (intc30) cic30 ? 0ffebh interrupt control register (intp4) pic4 ? 0ffech interrupt control register (intp5) pic5 ? 0ffedh interrupt control register (intad) adic ? 0ffeeh interrupt control register (intser) seric ? 0ffefh interrupt control register (intsr) sric ? interrupt control register (intcsi1) csiic1 ? 0fff0h interrupt control register (intst) stic ? 0fff1h interrupt control register (intcsi) csiic ? 0fff2h interrupt control register (intser2) seric2 ? 0fff3h interrupt control register (intsr2) sric2 ? interrupt control register (intcsi2) csiic2 ? 0fff4h interrupt control register (intst2) stic2 ? note 2 0fff5h interrupt control register (intspc) spcic ? 0fffch internal memory size switching register note 3 ims ffh notes 1. when the location 0h instruction is executed. when the location 0fh instruction is executed, ?0000h should be added to the value shown. 2. pd784038y subseries only. 3. writing to this register is valid only when the pd78p4038 is used. note 1 chapter 3 cpu architecture 102 user s manual u11316ej4v1ud 3.10 cautions (1) program fetches cannot be performed from the internal high-speed ram area (0fd00h to 0feffh when the location 0h instruction is executed; ffd00h to ffeffh when the location 0fh instruction is executed). (2) special function registers (sfrs) addresses onto which sfrs are not assigned should not be accessed in the area 0ff00h to 0ffffh note . if such an address is accessed by mistake, the pd784038 may become deadlocked. a deadlock can only be released by reset input. note when the location 0h instruction is executed; fff00h to fffffh when the location 0fh instruction is executed. (3) stack pointer (sp) operation with stack addressing, the entire 1-mbyte space can be accessed, but a stack area cannot be reserved in the sfr area or internal rom area. (4) stack pointer (sp) initialization the sp is undefined after reset input, while non-maskable interrupts can be acknowledged directly after reset release. therefore, an unforeseen operation may be performed if a non-maskable interrupt request is generated while the sp is in the undefined state directly after reset release. to minimize this risk, the following program should be coded without fail after reset release. rstvct cseg at 0 dw rststrt to initseg cseg base rststrt : location 0h ; or location 0fh movg sp, #stkbgn (5) the internal memory size switching register (ims) that selects the internal memory size of the pd78p4038 cannot be completely emulated by the in-circuit emulator and has the following restrictions. to debug products other than the pd784038, select a mask version that performs debugging as the emulation cpu. for the selection of an emulation cpu to the pd78p4038, even if a write instruction other than ffh (eeh, dch, cch) to ims is executed the memory size (ffh) is always identical to the pd784038. (6) do not set external wait to the internal rom area. otherwise, the cpu may be in the deadlock status which can be cleared only by reset input. (7) if the value of the timer register is read under the condition indicated by in table 3-6, the read value may be illegal. do not read the timer register under condition . chapter 3 cpu architecture 103 user s manual u11316ej4v1ud table 3-6 limits of reading timer register ( : can be read, : must not be read) f clk f xx /2 f xx /4 f xx /8 f xx /16 timer count clock f xx /8 ?? f xx /16 ??? f xx /n ??? f xx : oscillation frequency 2. f clk : internal system clock frequency 3. n = 32, 64, 128, 256, 512, 1,024, 2,048 104 user? manual u11316ej4v1ud chapter 4 clock generator 4.1 configuration and function the clock generator generates and controls the internal clock and internal system clock supplied to the cpu and on-chip hardware. the clock generator block diagram is shown in figure 4-1. figure 4-1 clock generator block diagram stbc x1 internal bus f xx /2 ck1 ck0 stp hlt reset clock oscillator x2 f xx /4 f clk f xx /16 frequency divider selector f xx /2 f xx /8 osts extc osts1 osts0 reset osts2 f xx internal system clock (cpu, watchdog timer, noise elimination circuit, a/d, pwm, interrupts, local bus interface) internal clock (uart/ioe, csi, noise elimination circuit, timer/counters, oscillation stabilization timer ) remark f xx : crystal/ceramic oscillation frequency or internal clock frequency f clk : internal system clock frequency the clock oscillator oscillates by means of a crystal resonator/ceramic resonator connected to the x1 and x2 pins. when standby mode (stop) is set, oscillation stops (see chapter 24 standby function ). it is also possible to input an external clock. in this case, the clock signal is input to the x1 pin, and the inverse phase s ignal to the x2 pin. the frequency divider generates an internal system clock by 1/2, 1/4, 1/8, or 1/16 scaling of the clock oscillator output (f xx ) according to the setting of the standby control register (stbc). chapter 4 clock generator 105 user s manual u11316ej4v1ud figure 4-2 clock oscillator external circuitry (a) crystal/ceramic resonator oscillation v ss1 x2 pd784038 x1 (b) external clock extc bit of .osts = 1 extc bit of .osts = 0 open x1 x2 pd784038 x1 x2 pd784038 cautions 1. the oscillator should be as close as possible to the x1 and x2 pins. 2. no other signal lines should pass through the area enclosed by the dotted line. remark differences between crystal resonator and ceramic resonator generally speaking, the oscillation frequency of a crystal resonator is extremely stable. it is therefore ideal for performing high-precision time management (in clocks, frequency meters, etc.). a ceramic resonator is inferior to a crystal resonator in terms of oscillation frequency stability, but it has three advantages: a fast oscillation start-up time, small size, and low price. it is therefore suitable for general use (when high-precision time management is not required). in addition, there are products with a built-in capacitor, etc., which enable the number of parts and mounting area to be reduced. chapter 4 clock generator 106 user? manual u11316ej4v1ud 4.2 control registers 4.2.1 standby control register (stbc) stbc is a register used to set the standby mode and select the internal system clock. see chapter 24 standby function for details of the standby modes. to prevent erroneous entry into standby mode due to an inadvertent program loop, the stbc register can only be written to by a dedicated instruction. this instruction is the mov stbc, #byte instruction, and has a special code configuration (4 b ytes). a write is only performed if the 3rd and 4th bytes of the op code are mutual complements. if the 3rd and 4th bytes of the op c ode are not mutual complements, a write is not performed, and an op error interrupt is generated. in this case, the return address saved in the stack area is the address of the instruction which is the source of the error. the error source address can thus be found from the return address saved on the stack area. an endless loop will result if restore from an operand error is simply performed with an retb instruction. because the operand error interrupt occurs only when the program hangs up (only the correct dedicated instruction is generated with the nec electronics assembler ra78k4 when mov stbc, #byte is described), make sure that the operand error interrupt processing program initializes the system. other write instructions (?ov stbc, a? ?nd stbc, #byte? ?et1 stbc.7? etc.) are ignored, and no operation is performed. that is, a write is not performed on the stbc, and an interrupt such as an operand error interrupt is not generated . the stbc can be read at any time with a data transfer instruction. stbc is set by an 8-bit memory manipulation instruction. reset input sets the stbc register contents to 30h. the format of the stbc is shown in figure 4-3. figure 4-3 standby control register (stbc) format 7 0 stbc 6 0 5 ck1 4 ck0 3 2 0 1 stp 0 hlt stp address after reset r/w r/w 30h 0ffc0h operating mode normal mode halt mode stop mode idle mode 0 1 1 0 hlt 1 0 1 0 ck1 ck0 intermal system clock selection f xx /2 (16 mhz) f xx /4 (8 mhz) f xx /8 (4 mhz) f xx /16 (2 mhz) 0 1 1 0 1 0 1 0 caution if the stop mode is used when external clock input is used, the extc bit of the oscillation stabilization time specification register (osts) must be set (to 1) before setting the stop mode. if the stop mode is used when the extc bit of the osts is in the cleared (to 0) state when external clock input is used, the pd784038 may be damaged or suffer reduced reliability. when setting the extc bit to 1, be sure to input a clock in phase reverse to that of the clock input to the x1 pin, to the x2 pin. chapter 4 clock generator 107 user s manual u11316ej4v1ud 4.2.2 oscillation stabilization time specification register (osts) osts is a register used to specify the operation of the oscillator. the extc bit of the osts specifies whether a crystal/ ceramic resonator or an external clock is used. the stop mode can be set during use of external clock input, only when the extc bit is set (to 1). the osts can be written to only by an 8-bit transfer instruction. reset input clears the osts register contents to 00h. the format of the osts is shown in figure 4-4. figure 4-4 oscillation stabilization time specification register (osts) format 7 extc osts 6 0 5 0 4 0 3 0 2 osts2 1 osts1 0 osts0 oscillation stabilization time selection (see figure 24-4 for details) address after reset r/w r/w 00h 0ffcfh extc external clock selection crystal/ceramic oscillation used external clock (drives x1 only) external clock (drives x1 and x2) 1 0 cautions 1. when using a crystal/ceramic oscillation, the extc bit must be cleared (to 0). if the extc bit is set (to 1), oscillation will stop. 2. if the stop mode is used with external clock input, the extc bit must be set (to 1) before setting the stop mode. if the stop mode is used when the extc bit is in the cleared (to 0) state, the pd784038 may be damaged or suffer reduced reliability. 3. when setting the extc bit to 1 during external clock input, be sure to input a clock in phase reverse to that of the clock input to the x1 pin, to the x2 pin. when the extc bit is set to 1, the pd784038 operates on only the clock input to the x2 pin. chapter 4 clock generator 108 user s manual u11316ej4v1ud 4.3 clock generator operation 4.3.1 clock oscillator (1) when using crystal/ceramic oscillation the clock oscillation circuit starts oscillating when the reset signal is input, and stops oscillation when the stop mode is set by the standby control register (stbc). oscillation is resumed when the stop mode is released. (2) when using external clock the clock oscillation circuits supplies the clock input from the x1 pin to the internal circuitry when the reset signal is inpu t. the oscillation circuit operates as follows when the extc bit of the oscillation stabilization time specification register (ost s) is set to 1. the clock oscillation circuit is set in the external clock input mode. the clock oscillation circuit supplies the clock input to the x2 pin to the internal circuitry. the necessary circuit stops operating during the crystal/ceramic oscillation of the clock oscillation circuit, to reduce the power dissipation. the stop mode can be used even when the external clock is input. the oscillation stabilization time is shortened when the system is released from the stop mode. cautions 1. when using a crystal/ceramic oscillation, the extc bit of the oscillation stabilization time specification register (osts) must be cleared (to 0). if the extc bit is set (to 1), oscillation will stop. 2. if the stop mode is used with external clock input, the extc bit of the osts must be set (to 1) before setting the stop mode. if the stop mode is used when the extc bit is in the cleared (to 0) state, not only will the clock generator consumption current not be reduced, but the pd784038 may also be damaged or suffer reduced reliability. 3. when setting the extc bit of osts to 1, be sure to input a clock in phase reverse to that of the clock input to the x1 pin, to the x2 pin. 4.3.2 divider the divider performs 1/2, 1/4, 1/8, or 1/16 scaling of the clock oscillator output, and supplies the resulting clock to the cpu , watchdog timer, noise elimination circuit, clocked serial interface (csi), a/d converter, pwm, interrupt control circuit, and l ocal bus interface. the division ratio is specified by the ck0 and ck1 bits of the standby control register (stbc). controlling the division ratio to match the speed required by the cpu enables the overall power consumption to be reduced. also, the operating speed can be selected to match the supply voltage. when reset is input, the lowest speed (1/16) is selected. if the division ratio of the divider circuit is changed, the maximum time shown in table 4-1 is required to change the division ratio, depending on the clock selected before change. instruction execution continues even while the division ratio is changed, and the clock is supplied with the previous division ratio until the division ratio has been completely changed. table 4-1 time required to change division ratio previous division ratio maximum time required for change 1/2 22/f xx 1/4 24/f xx 1/8 16/f xx 1/16 16/f xx chapter 4 clock generator 109 user s manual u11316ej4v1ud 4.4 cautions the following cautions apply to the clock generator. 4.4.1 when an external clock is input (1) if the stop mode is used with external clock input, the extc bit of the oscillation stabilization time specification registe r (osts) must be set (to 1). if the stop mode is used when the extc bit is in the cleared (to 0) state, the pd784038 may be damaged or suffer reduced reliability. (2) when setting the extc bit of the osts to 1, be sure to input a clock in phase reverse to that of the clock input to the x1 pin, to the x2 pin. (3) even when inputting the external clock by clearing the extc bit of the oscillation stabilization time specification register (osts) to 0, input a signal in phase reverse to that of the signal input to the x1 pin, to the x2 pin, whenever possible. otherwise, more malfunctioning may occur due to noise. (4) when an external clock is input, this should be performed with a hcmos device, or a device with the equivalent drive capability. (5) a signal should not be extracted from the x1 and x2 pins. if a signal is extracted, it should be extracted from point a in figure 4-5. figure 4-5 signal extraction with external clock input x1 pd784038 x2 a (6) the wiring connecting the x1 pin to the x2 pin via an inverter, in particular, should be made as short as possible. chapter 4 clock generator 110 user s manual u11316ej4v1ud 4.4.2 when crystal/ceramic oscillation is used (1) as the oscillator is a high-frequency analog circuit, considerable care is required. the following points, in particular, require attention. the wiring should be kept as short as possible. no other signal lines should be crossed. avoid lines carrying a high fluctuating current. the oscillator capacitor grounding point should always be at the same potential as the v ss1 pin. do not ground to a ground pattern carrying a high current. a signal should not be taken from the oscillator. if oscillation is not performed normally and stably, the microcontroller will not be able to operate normally and stably, either. also, if a high-precision oscillation frequency is required, consultation with the oscillator manufacturer is recommended. figure 4-6 cautions on resonator connection v ss1 x2 x1 pd784038 cautions 1. the oscillator should be as close as possible to the x1 and x2 pins. 2. no other signal lines should pass through the area enclosed by the dotted line. chapter 4 clock generator 111 user s manual u11316ej4v1ud figure 4-7 incorrect example of resonator connection (a) wiring of connected circuits is too long (b) crossed signal lines pd748038 x1 x2 v ss1 pd784038 x1 pnm x2 v ss1 (c) wiring near high alternating current (d) current flowing through ground line of oscillation circuit (potentials at points a, b, and c fluctuate) pd784038 x1 x2 v ss1 high alternating current pd78038 x1 x2 v ss1 b ac v dd0 pnm high current (e) signal extracted pd784038 x1 x2 v ss1 chapter 4 clock generator 112 user s manual u11316ej4v1ud (2) when the device is powered on, and when restoring from the stop mode, sufficient time must be allowed for the oscillation to stabilize. generally speaking, the time required for oscillation stabilization is several milliseconds when a crystal resonator is used, and several hundred microseconds when a ceramic resonator is used. an adequate oscillation stabilization period should be secured by the following means: <1> when powering-on : reset input (reset period) <2> when returning from stop mode : (i) reset input (reset period) (ii) time of the oscillation stabilization timer that automatically starts at the valid edge of nmi, intp4, or intp5 signal note (set by the oscillation stabilization time specification register (osts)) note for intp4 and intp5, when masking is released and macro service is disabled. (3) the extc bit of the oscillation stabilization time specification register (osts) must be cleared (to 0). if the extc bit is set (to 1), oscillation will stop. 113 user? manual u11316ej4v1ud chapter 5 port functions 5.1 digital input/output ports the pd784038 is provided with the ports shown in figure 5-1, enabling various kinds of control to be performed. the function of each port is shown in table 5-1. for ports 0 to 6, use of an internal pull-up resistor can be specified by software when us ed as input ports. figure 5-1 port configuration port 0 port 1 port 3 port 4 note port 5 note port 6 note port 7 8 port 2 p00 p07 p10 p17 p30 p37 p40 p47 p50 p57 p60 p67 p70 p77 p20 to p27 note with the pd784031, p40 to p47 serve as address/data bus pins, p50 to p57, as address bus pins, p64, as rd pin, and p65, as wr pin. p60 to p63 serve as output port pins. chapter 5 port functions 114 user s manual u11316ej4v1ud table 5-1 port functions port name pin names functions software pull-up specification port 0 p00 to p07 input or output specifiable bit-wise. input mode pins specified at once can also operate as 4-bit real-time output ports (p00 to p03, p04 to p07). transistor drive capability. port 1 p10 to p17 input or output specifiable bit-wise. led drive capability. port 2 p20 to p27 input port 6-bit unit (p22 to p27) port 3 p30 to p37 input or output specifiable bit-wise. input mode pins specified at once port 4 p40 to p47 note input or output specifiable bit-wise. led drive capability. port 5 p50 to p57 note input or output specifiable bit-wise. led drive capability. port 6 p60 to p67 note input or output specifiable bit-wise. port 7 p70 to p77 input or output specifiable bit-wise. note with the pd784031, p40 to p47 serve as address/data bus pins, p50 to p57, as address bus pins, p64, as rd pin, and p65, as wr pin. these pins therefore cannot directly drive leds or be connected to a pull-up resistor by software. p60 to p63 serve as output port pins. table 5-2 number of input/output ports input/output total input mode output mode ports software pull-up resistor direct led drive direct transistor drive input ports 8 (8) 6 (6) input/output ports 56 (34) 48 (26) 24 (8) 0 (0) output ports 0 (4) 0 (0) 8 (8) total 64 (46) 54 (32) 24 (8) 8 (8) remark ( ): pd784031 chapter 5 port functions 115 user s manual u11316ej4v1ud 5.2 port 0 port 0 is an 8-bit input/output port with an output latch, and has direct transistor drive capability. input/output can be spe cified bit-wise by means of the port 0 mode register (pm0). each pin incorporates a software programmable pull-up resistor. p00 to p03 and p04 to p07 can output the buffer register (p0l, p0h) contents at any time interval as 4-bit real-time output ports or one 8-bit real-time output port. the real-time output port control register (rtpc) is used to select whether this por t is used as a normal output port or a real-time output port. when reset is input, port 0 is set as an input port (output high-impedance state), and the output latch contents are undefined. 5.2.1 hardware configuration the port 0 hardware configuration is shown in figure 5-2. figure 5-2 port 0 block diagram wr puo pull-up resistor option register puo0 wr rtpc real-time output port control register p0ml (p0mh) wr pm0 port 0 mode register wr rtpc wr p0l buffer register pm0n (pm0m) rd p0l wr out rd p0 p0ln (p0hm) p0n (p0m) p0n (p0m) n = 0, 1, 2, 3 m = 4, 5, 6, 7 trigger output latch rd pm0 v dd0 selector internal bus chapter 5 port functions 116 user s manual u11316ej4v1ud 5.2.2 i/o mode/control mode setting the port 0 input/output mode is set by means of the port 0 mode register (pm0) as shown in figure 5-3. figure 5-3 port 0 mode register (pm0) format 7 pm07 pm0 6 pm06 5 pm05 4 pm04 3 pm03 2 pm02 1 pm01 0 pm00 address after reset r/w r/w ffh 0ff20h pm0n p0n pin input/output mode specification (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) 1 0 when port 0 is used as a real-time output port, the p0ml and p0mh bits of the real-time output port control register (rtpc) should be set (to 1). when p0ml and p0mh are set, the respective pin output buffer is turned on and the output latch contents are output to the pin irrespective of the contents of pm0. 5.2.3 operating status port 0 is an input/output port (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . writes cannot be performed to the output latch of a port specified as a real-time output port. however, the output latch contents can be read even if it is set to the real-time output port mode. note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 5-4 port specified as output port p0n n = 0 to 7 rd out wr port internal bus output latch chapter 5 port functions 117 user s manual u11316ej4v1ud (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction, etc. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the output latch contents are output to the port pin). also, the contents of the output latch of a bit specified as an i nput port cannot be loaded into an accumulator. figure 5-5 port specified as input port output latch p0n n = 0 to 7 rd in wr port internal bus caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins, the contents of the output latch of pins specified as inputs will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit manipulation instructions. chapter 5 port functions 118 user s manual u11316ej4v1ud 5.2.4 internal pull-up resistors port 0 incorporates pull-up resistors. use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the puo0 bit of the pull- up resistor option register (puo) and the port 0 mode register (pm0). when puo0 is 1, the internal pull-up resistors of the pi ns for which input is specified by pm0 are enabled (pm0n = 1, n = 0 to 7). figure 5-6 pull-up resistor option register (puo) format 7 0 puo 6 puo6 5 puo5 4 puo4 3 puo3 2 puo2 1 puo1 0 puo0 address after reset r/w r/w 00h 0ff4eh puo0 port 0 pull-up resistor specification not used in port 0 used in port 0 1 0 remark when stop mode is entered, setting 00h in puo is effective in reducing the power consumption. figure 5-7 pull-up resistor specification (port 0) p06 input buffer p07 p05 p01 p00 v dd0 port 0 mode register (pm0) puo0 (puo) internal bus chapter 5 port functions 119 user s manual u11316ej4v1ud 5.2.5 transistor drive in port 0, the output buffer high-level side drive capability has been increased, allowing active-high direct transistor drive. an example of the connection is shown in figure 5-8. figure 5-8 example of transistor drive p0n v dd0 load chapter 5 port functions 120 user s manual u11316ej4v1ud 5.3 port 1 port 1 is an 8-bit input/output port with an output latch. input/output can be specified bit-wise by means of the port 1 mode register (pm1). each pin incorporates a programmable pull-up resistor. this port has direct led drive capability. in addition to their input/output port function, p10 to p14 also have an alternate function as pwm output pins and serial interface pins. the operating mode can be specified bit-wise by means of the pwm control register (pwmc) and the port 1 mode control register (pmc1), as shown in table 5-3. the level of any pin can be read and tested at any time irrespective of the alternate-function pin operation. when reset is input, port 1 is set as an input port (output high-impedance state), and the output latch contents are undefined. table 5-3 port 1 operating modes pin name port mode control signal i/o mode operation to operate control pin p10 i/o port pwm0 output setting of en0 bit of pwmc to 1 p11 pwm1 output setting of en1 bit of pwmc to 1 p12 asck2 i/o/sck2 i/o setting pmc12 bit of pmc1 to 1 p13 rxd2 input/si2 input setting pmc13 bit of pmc1 to 1 p14 txd2 output/so2 output setting pmc14 bit of pmc1 to 1 p15 to p17 (a) port mode p10 and p11 operate as port mode pins when the en0 and en1 bits of the pwm control (pwmc) register are cleared (to 0), and p12 to p14 do the same when the relevant bits of the port 1 mode control (pmc1) register are cleared (to 0), and p15 to p17 always operate as port mode pins. input/output can be specified bit-wise by means of the port 1 mode register (pm1). (b) control signal input/output mode p10 and p11 operate as pwm signal output pins when the en0 and en1 bits, respectively, of the pwm control (pwmc) register are set (to 1). p12 to p14 can be set as control pins bit-wise by setting the port 1 mode control (pmc1) register. (i) pwm0, pwm1 pwm0 and pwm1 are pwm output pins. (ii) asck2/sck2 asck2 is the asynchronous serial interface baud rate clock input pin. sck2 is the serial clock input/output pin (in 3-wire serial i/o2 mode). (iii) rxd2/si2 rxd2 is the asynchronous serial interface serial data input pin. si2 is the serial data input pin (in 3-wire serial i/o2 mode). (iv) txd2/so2 txd2 is the asynchronous serial interface serial data output pin. so2 is the serial data output pin (in 3-wire serial i/o2 mode). chapter 5 port functions 121 user s manual u11316ej4v1ud 5.3.1 hardware configuration the port 1 hardware configuration is shown in figures 5-9 to 5-13. figure 5-9 block diagram of p10 and p11 (port 1) p1n n = 0, 1 wr puo puo1 v dd0 pull-up resistor option register rd puo wr pm1 pm1n wr p1 p1n pwm output enn (pwmc) port 1 mode register output latch rd pm1 rd p1 selector internal bus chapter 5 port functions 122 user s manual u11316ej4v1ud figure 5-10 block diagram of p12 (port 1) p12 wr puo v dd0 rd puo wr pmc1 wr p1 asck2, sck2 input rd pmc1 external sck2 wr pm1 sck2 output puo1 pmc12 p12 pm12 rd pm1 rd p1 pull-up resistor option register port 1 mode control register output latch selector internal bus port 1 mode control register chapter 5 port functions 123 user s manual u11316ej4v1ud figure 5-11 block diagram of p13 (port 1) p13 v dd0 wr puo wr p1 si2, rxd2 input rd puo wr pm1 wr pmc1 rd pmc1 puo1 pm13 p13 pmc13 rd pm1 rd p1 pull-up resistor option register port 1 mode register output latch internal bus port 1 mode control register chapter 5 port functions 124 user s manual u11316ej4v1ud figure 5-12 block diagram of p14 (port 1) wr puo rd puo wr pmc1 wr p1 rd pmc1 txd2/so2 output puo1 pmc14 p14 pm14 wr pm1 p14 v dd0 rd pm1 rd p1 pull-up resistor option register port 1 mode register output latch internal bus port 1 mode control register selector chapter 5 port functions 125 user s manual u11316ej4v1ud figure 5-13 block diagram of p15 to p17 (port 1) p1n n = 5 to 7 wr puo puo1 v dd0 rd puo wr pm1 pm1n wr p1 p1n rd pm1 rd p1 pull-up resistor option register port 1 mode register output latch internal bus chapter 5 port functions 126 user s manual u11316ej4v1ud 5.3.2 i/o mode/control mode setting the port 1 input/output mode is set for each pin by means of the port 1 mode register (pm1) as shown in figure 5-14. in addition to their input/output port function, p10 and p11 also have an alternate function as pwm signal output pins, and the control mode is specified by means of the pwm control register (pwmc) as shown in table 5-4. in addition to their input/output port function, p12 to p14 also have an alternate function as serial interface pins, and the control mode is specified by means of the port 1 mode control register (pmc1) as shown in figure 5-15. figure 5-14 port 1 mode register (pm1) format 7 pm17 pm1 6 pm16 5 pm15 4 pm14 3 pm13 2 pm12 1 pm11 0 pm10 address after reset r/w r/w ffh 0ff21h pm1n p1n pin input/output mode specification (n = 0 to 7) output mode (output buffer on) intput mode (output buffer off) 1 0 table 5-4 method of setting p10 & p11 pwm signal output function pin name function method of setting pwm signal output function p10 pwm0 set (to 1) en0 bit of pwmc p11 pwm1 set (to 1) en1 bit of pwmc figure 5-15 port 1 mode control register (pmc1) format 7 0 pmc1 6 0 5 0 4 pmc14 3 pmc13 2 pmc12 1 0 0 0 address after reset r/w r/w 00h 0ff41h pmc12 p12 pin control mode specification input/output port mode asck2/sck2 input/output mode 1 0 pmc13 p13 pin control mode specification input/output port mode rxd2/si2 input mode 1 0 pmc14 p14 pin control mode specification input/output port mode txd2/so2 output mode 1 0 chapter 5 port functions 127 user s manual u11316ej4v1ud 5.3.3 operating status port 1 is an input/output port. pins p10 and p11 have an alternate function as pwm signal output pins, and pins p12 to p14 have an alternate function as serial interface pins. (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 5-16 port specified as output port internal bus output latch p1n n = 0 to 7 rd out wr port (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction, etc. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the output latch contents are output to the port pin). also, the contents of the output latch of a bit specified as an i nput port cannot be loaded into an accumulator. figure 5-17 port specified as input port output latch p1n n = 0 to 7 rd in wr port internal bus chapter 5 port functions 128 user s manual u11316ej4v1ud caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port that has the i/o mode or port mode and control mode, the contents of the output latch of the pin set in the input mode or control mode become undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit manipulation instructions. (3) when specified as control signal input/output p10 and p11 (by setting (to 1) the enn bit (n = 0 or 1) of the pwm control register (pwmc)) and p12 to p14 (by setting (to 1) bits of the port 1 mode control register (pmc1)) can be used as control signal inputs or outputs bit-wise irrespective of the setting of the port 1 mode register (pm1). when a pin is used as a control signal, the control signal status can be seen by executing a port read instruction. figure 5-18 control specification p1n n = 0 to 4 pm1n = 0 pm1n = 1 rd control (output) internal bus control (input) (a) when port is control signal output when the port 1 mode register (pm1) is set (to 1), the control signal pin level can be read by executing a port read instruction. when pm1 is reset (to 0), the pd784038 internal control signal status can be read by executing a port read instruction. (b) when port is control signal input when the port 1 mode register (pm1) is set (to 1), control signal pin level can be read by executing a port read instruction. chapter 5 port functions 129 user s manual u11316ej4v1ud 5.3.4 internal pull-up resistors port 1 incorporates pull-up resistors. use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the puo1 bit of the pull- up resistor option register (puo) and the port 1 mode register (pm1). when puo1 is 1, the internal pull-up resistors of the pi ns for which input is specified by pm1 are enabled (pm1n = 1, n = 0 to 7). also, the specification for use of the pull-up resistor is also valid for pins specified as control signal output pins (pull-u p resistors are also connected to pins that function as control signal output pins). therefore, if you do not want to connect th e pull- up resistors with the control signal output pin, the contents of the corresponding bits of pm1 should be set to 0 (output mode) . figure 5-19 pull-up resistor option register (puo) format 7 0 puo 6 puo6 5 puo5 4 puo4 3 puo3 2 puo2 1 puo1 0 puo0 address after reset r/w r/w 00h 0ff4eh puo1 port 1 pull-up resistor specification not used in port 1 used in port 1 1 0 remark when stop mode is entered, setting 00h in puo is effective in reducing the power consumption. figure 5-20 pull-up resistor specification (port 1) p16 input buffer p17 p15 p11 p10 v dd0 port 1 mode register (pm1) puo1 (puo) internal bus chapter 5 port functions 130 user s manual u11316ej4v1ud 5.3.5 direct led drive in port 1, the output buffer low-level side drive capability has been reinforced allowing active-low direct led drive. an exam ple of such use is shown in figure 5-21. figure 5-21 example of direct led drive pd784038 p1n (n = 0 to 7) v dd0 chapter 5 port functions 131 user s manual u11316ej4v1ud 5.4 port 2 port 2 is an 8-bit input-only port. p22 to p27 incorporate a software programmable pull-up resistor. as well as operating as input ports, port 2 pins also operate as control signal input pins, such as external interrupt signal pins (see table 5-5). al l 8 pins are schmitt-triggered inputs to prevent malfunction due to noise. table 5-5 port 2 operating modes port name function p20 input port/nmi input note p21 input port/intp0 input/cr11 capture trigger input timer/counter 1 count clock/real-time output port trigger signal p22 input port/intp1 input/cr22 capture trigger input p23 input port/intp2 input/ci input p24 input port/intp3 input/cr02 capture trigger input/ timer/count 0 count clock p25 input port/intp4 input/asck input/sck1 input/output p26 input port/intp5 input/a/d converter external trigger input p27 input port/si0 input note nmi input is acknowledged regardless of whether interrupts are enabled or disabled. (a) function as port pins the pin level can always be read or tested regardless of the alternate-function pin operation. (b) functions as control signal input pins (i) nmi (non-maskable interrupt) the external non-maskable interrupt request input pin. rising edge detection or falling edge detection can be specified by means of the external interrupt mode register 0 (intm0). (ii) intp0 to intp5 (interrupt from peripherals) external interrupt request input pins. when the valid edge specified by the external interrupt mode registers 0, 1 (intm0/intm1) is detected an interrupt is generated (see chapter 21 edge detection function ). in addition, pins intp0 to intp3 and intp5 are also used as external trigger input pins with the various functions shown below. intp0 ....... timer/counter 1 capture trigger input pin external count clock input pin real-time output port trigger input pin intp1 ....... timer/counter 2 capture register (cr22) capture trigger input pin intp2 ....... timer/counter 2 external count clock input pin capture/compare register (cr21) capture trigger input pin intp3 ....... timer/counter 0 capture trigger input pin timer/counter 0 external count clock input pin intp5 ....... a/d converter external trigger input pin chapter 5 port functions 132 user s manual u11316ej4v1ud (iii) ci (clock input) the timer/counter 2 external clock input pin. (iv) asck (asynchronous serial clock) the external baud rate clock input pin. (v) sck1 (serial clock 1) the serial clock input/output pin (in 3-wire serial i/o 1 mode). (vi) si0 (serial input 0) the serial data input pin (in 3-wire serial i/o 0 mode). 5.4.1 hardware configuration the port 2 hardware configuration is shown in figure 5-22. figure 5-22 block diagram of p20 to p24, p26 and p27 (port 2) internal bus rd p2 rd puo wr puo si0 input various interrupt control signals v dd0 p27 rd p2 3-wire serial i/o mode 0 p2n n = 0 to 4, 6 puo2 edge detection circuit note pull-up resistor option register v dd0 note p20 and p21 do not have the circuitry enclosed by the dotted line. chapter 5 port functions 133 user s manual u11316ej4v1ud figure 5-23 block diagram of p25 (port 2) rd p2 v dd0 rd puo wr puo pu02 intp4 input sck1 output mode sck1 output asck/sck1 input p25/asck/sck1 internal bus edge detection circuit chapter 5 port functions 134 user s manual u11316ej4v1ud 5.4.2 input mode/control mode setting port 2 is an input-only port, and there is no register for setting the input mode. also, control signal input is always possible, and therefore the signal to be used is determined by the control registers for individual on-chip hardware items. 5.4.3 operating status port 2 is an input-only port, and pin levels can always be read or tested. figure 5-24 port specified as input port internal bus p2n n = 0 to 7 rd in 5.4.4 internal pull-up resistors p22 to p27 incorporate pull-up resistors. use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. whether or not an internal pull-up resistor is to be used can be specified for all six pins, p22 to p27, together by means of the puo2 bit of the pull-up resistor option register (puo) (bit-wise specification is not possible). p20 and p21 do not incorporate a pull-up resistor. figure 5-25 pull-up resistor option register (puo) format 7 0 puo 6 puo6 5 puo5 4 puo4 3 puo3 2 puo2 1 puo1 0 puo0 address after reset r/w r/w 00h 0ff4eh puo2 port 2 pull-up resistor specification not used in port 2 used in pins p22 to p27 1 0 remark when stop mode is entered, setting 00h in puo is effective in reducing the power consumption. chapter 5 port functions 135 user s manual u11316ej4v1ud figure 5-26 pull-up specification (port 2) p23 v dd0 pull-u p resistor o p tion re g ister ( puo ) puo2 input buffer internal bus p22 p24 p25 p26 p27 caution as p22 to p26 are not pulled up immediately after a reset, an interrupt request flag may be set depending on the function of the alternate-function pins (intp1 to intp5). therefore, the interrupt request flags should be cleared after specifying pull-up in the initialization routine. chapter 5 port functions 136 user? manual u11316ej4v1ud 5.5 port 3 port 3 is an 8-bit input/output port with an output latch. input/output can be specified bit-wise by means of the port 3 mode register (pm3). each pin incorporates a software programmable pull-up resistor. in addition to its function as an input/output port, port 3 also has various alternate-function control signal pin functions. the operating mode can be specified bit-wise by means of the port 3 mode control register (pmc3), as shown in table 5-6. the pin level of all pins can always be read or tested regardless of the alternate-function pin operation. when reset is input, port 3 is set as an input port (output high impedance state), and the output latch contents are undefined. table 5-6 port 3 operating modes (n = 0 to 7) mode port mode control signal input/output mode setting condition pmc3n = 0 pmc3n = 1 p30 input/output port rxd input/si1 input p31 txd output/so1 output p32 sck0 input/output/scl input/output p33 so0 output/sda input/output p34 to0 output p35 to1 output p36 to2 output p37 to3 output (a) port mode each port specified as port mode by the port 3 mode control register (pmc3) can be specified as input/output bit-wise by means of the port 3 mode register (pm3). (b) control signal input/output mode pins can be set as control pins bit-wise by setting the port 3 mode control register (pmc3). (i) rxd (receive data)/si1 (serial input 1) rxd is the asynchronous serial interface serial data input pin. si1 is the serial data input pin (in 3-wire serial i/o 1 mode). (ii) txd (transmit data)/so1 (serial output 1) txd is the asynchronous serial interface serial data output pin. so1 is the serial data output pin (in 3-wire serial i/o 1 mode). (iii) sck0 (serial clock 0)/scl (serial clock) sck0 is the clocked serial interface serial clock input/output pin (in 3-wire serial i/o 0 mode). scl is the serial clock i/o pin of the clocked serial interface (in 2-wire serial i/o mode/i 2 c bus mode note ). note pd784038y subseries only remark bit 2 (p32) of port 3 is reserved for the nec electronics assembler package as ?cl? it is also defined as a bit type sfr variable by the #pragma sfr command of the c compiler. chapter 5 port functions 137 user? manual u11316ej4v1ud (iv) so0 (serial output 0)/sda (serial data) so0 is the serial data output pin (in 3-wire serial i/o 0 mode), and sda is the serial data input/output pin (in 2-wire serial i/o mode/i 2 c bus mode note ). note pd784038y subseries only (v) to0 to to3 (timer output) timer output pins. 5.5.1 hardware configuration the port 3 hardware configuration is shown in figures 5-27 to 5-30. figure 5-27 block diagram of p30 (port 3) p30 v dd0 wr puo wr p3 si1, rxd input rd puo wr pm3 wr pmc3 rd pmc3 puo3 pm30 p30 pmc30 rd pm3 rd p3 pull-up resistor option register port 3 mode register output latch internal bus port 3 mode control register chapter 5 port functions 138 user s manual u11316ej4v1ud figure 5-28 block diagram of p31 and p34 to p37 (port 3) wr puo rd puo wr pmc3 wr p3 rd pmc3 to, so1, txd output puo3 pmc3n p3n pm3n wr pm3 p3n n = 1, 4, 5, 6, 7 v dd0 rd pm3 rd p3 pull-up resistor option register port 3 mode register output latch internal bus port 3 mode control register selector chapter 5 port functions 139 user s manual u11316ej4v1ud figure 5-29 block diagram of p32 (port 3) wr puo rd puo wr pm3 rd pm3 wr pmc3 rd pmc3 rd p32 rd p3 puo3 pm32 pmc32 p32 2-wire serial i/o mode or i 2 c bus mode sck0/scl input sck0/scl output sck0/scl input v dd0 v dd0 p32 pull-up resistor option register port 3 mode register output latch internal bus port 3 mode control register selector chapter 5 port functions 140 user s manual u11316ej4v1ud figure 5-30 block diagram of p33 (port 3) wr puo rd puo wr pm3 rd p3 wd pmc3 rd pmc3 wr p3 rd p3 puo3 pm33 pmc33 p33 so0/sda output so0/sda input v dd0 v dd0 p33 so0/sda input mode pmc33 pull-up resistor option register port 3 mode register output latch internal bus port 3 mode control register selector 2-wire serial i/o mode or i 2 c bus mode note always 0 in the i 2 c bus mode note chapter 5 port functions 141 user s manual u11316ej4v1ud 5.5.2 i/o mode/control mode setting the port 3 input/output mode is set for each pin by means of the port 3 mode register (pm3) as shown in figure 5-31. in addition to their input/output port function, port 3 pins also have an alternate function as various control signal pins, an d the control mode is specified by means of the port 3 mode control register (pmc3) as shown in figure 5-32. figure 5-31 port 3 mode register (pm3) format 7 pm37 pm3 6 pm36 5 pm35 4 pm34 3 pm33 2 pm32 1 pm31 0 pm30 address after reset r/w r/w ffh 0ff23h pm3n p3n pin input/output mode specification (n = 0 to 7) output mode (output buffer on) intput mode (output buffer off) 1 0 figure 5-32 port 3 mode control register (pmc3) format 7 pmc37 pmc3 6 pmc36 5 pmc35 4 pmc34 3 pmc33 2 pmc32 1 pmc31 0 pmc30 address after reset r/w r/w 00h 0ff43h pmc30 p30 pin control mode specification input/output port mode rxd/si1 input mode 1 0 pmc31 p31 pin control mode specification input/output port mode txd/so1 output mode 1 0 pmc32 p32 pin control mode specification input/output port mode sck0/scl input/output mode 1 0 pmc33 p33 pin control mode specification input/output port mode so0/sda output mode 1 0 pmc3n p3n pin control mode specification (n = 4 to 7) input/output port mode tom output mode (m = 0 to 3) 1 0 chapter 5 port functions 142 user? manual u11316ej4v1ud 5.5.3 operating status port 3 is an input/output port, with an alternate function as various control pins. (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 5-33 port specified as output port internal bus output latch p3n n = 0 to 7 rd out wr port (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all outp ut latches irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input p ort is high impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the out put latch contents are output to the port pin). also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. figure 5-34 port specified as input port output latch p3n n = 0 to 7 rd in wr port internal bus chapter 5 port functions 143 user? manual u11316ej4v1ud caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins or port mode and control mode, the contents of the output latch of pins specified as inputs and pins specified as control mode will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit manipulation instructions. (3) when specified as control signal input/output by setting (to 1) bits of the port 3 mode control register (pmc3), port 3 can be used as control signal input or output bit-wis e irrespective of the setting of the port 3 mode register (pm3). when a pin is used as a control signal, the control signal stat us can be seen by executing a port read instruction. figure 5-35 control specification p3n n = 0 to 7 pm3n = 0 pm3n = 1 rd control (output) internal bus control (input) (a) when port is control signal output when the port 3 mode register (pm3) is set (to 1), the control signal pin level can be read by executing a port read instruction. when pm3 is reset (to 0), the pd784038 internal control signal status can be read by executing a port read instruction. remark for bit 2 (p32) of port 3, the name scl is a reserved word in the nec electronics assembler package. in the c compiler, it is defined as a bit-type sfr variable by the # pragma sfr directive. (b) when port is control signal input only the port 3 mode register (pm3) is set (to 1), control signal pin levels can be read by executing a port read instruction. chapter 5 port functions 144 user s manual u11316ej4v1ud 5.5.4 internal pull-up resistors port 3 incorporates pull-up resistors. use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the puo3 bit of the pull- up resistor option register (puo) and the port 3 mode register (pm3). when puo3 is 1, the internal pull-up resistors of the pi ns for which input is specified by pm3 (pm3n = 1, n = 0 to 7) are enabled. also, the specification for use of the pull-up resistor is also valid for pins specified as control mode pins (pull-up resistor s are also connected to pins that function as output pins in the control mode). therefore, if you do not want to connect the pull-up resistors in the control mode, the contents of the corresponding bits of pm3 should be set to 0 (output mode). figure 5-36 pull-up resistor option register (puo) format 7 0 puo 6 puo6 5 puo5 4 puo4 3 puo3 2 puo2 1 puo1 0 puo0 address after reset r/w r/w 00h 0ff4eh puo3 port 3 pull-up resistor specification not used in port 3 used in port 3 1 0 remark when stop mode is entered, setting 00h in puo is effective in reducing the power consumption. figure 5-37 pull-up specification (port 3) p31 input buffer p30 p32 p36 p37 v dd0 port 3 mode register (pm3) puo3 (puo) internal bus chapter 5 port functions 145 user s manual u11316ej4v1ud 5.6 port 4 port 4 is an 8-bit input/output port with an output latch. input/output can be specified bit-wise by means of the port 4 mode register (pm4). each pin incorporates a software programmable pull-up resistor. this port has direct led drive capability. port 4 also functions as the time division address/data bus (ad0 to ad7) by the memory extension mode register (mm) when external memory or i/os are extended. with the pd784031, p40 to p47 cannot be used as port pins. these pins function only as address/data bus pins (ad0 to ad7). when reset is input, port 4 is set as an input port (output high-impedance state), and the output latch contents are undefined. table 5-7 port 4 operating modes mm bits operating mode mm3 mm2 mm1 mm0 0000 port 0011 address/data bus (ad0 to ad7) 0100 0101 0110 0111 1000 1001 5.6.1 hardware configuration the port 4 hardware configuration is shown in figure 5-38. chapter 5 port functions 146 user s manual u11316ej4v1ud figure 5-38 port 4 block diagram rd puo wr puo puo4 v dd0 p4n n = 0 to 7 wr pm4 pm4n wr p4 p4n mm0 to mm3 rd pm4 rd p4 pull-up resistor option register port 4 mode register output latch internal data bus internal address bus input/ output control circuit chapter 5 port functions 147 user s manual u11316ej4v1ud 5.6.2 i/o mode/control mode setting the port 4 input/output mode is set for each pin by means of the port 4 mode register (pm4) as shown in figure 5-39. when port 4 is used as the address/data bus, it is set by means of the memory extension mode register (mm: see figure 23-1 ) as shown in table 5-8. with the pd784031, this port functions only as the address/data bus (ad0 to ad7). figure 5-39 port 4 mode register (pm4) format 7 pm47 pm4 6 pm46 5 pm45 4 pm44 3 pm43 2 pm42 1 pm41 0 pm40 address after reset r/w r/w ffh 0ff24h pm4n p4n pin input/output mode specification (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) 1 0 table 5-8 port 4 operating modes mm bits operating mode mm3 mm2 mm1 mm0 0000 port 0011 address/data bus (ad0 to ad7) 0100 0101 0110 0111 1000 1001 chapter 5 port functions 148 user s manual u11316ej4v1ud 5.6.3 operating status port 4 is an input/output port, with an alternate function as the address/data bus (ad0 to ad7). (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 5-40 port specified as output port internal bus output latch p4n n = 0 to 7 rd out wr port chapter 5 port functions 149 user s manual u11316ej4v1ud (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all outp ut latches irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input p ort is high-impedance, the data is not output to the port pin (when a port specified as input is switched to an output port, the output latch contents are output to the port pin). also, when specified as an input port, the output latch contents cannot be loaded into an accumulator. figure 5-41 port specified as input port output latch p4n n = 0 to 7 rd in wr port internal bus caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins, the contents of the output latch of pins specified as inputs will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit manipulation instructions. (3) when used as address/data bus (ad0 to ad7) used automatically when an external access is performed. input/output instructions should not be executed on port 4. chapter 5 port functions 150 user s manual u11316ej4v1ud 5.6.4 internal pull-up resistors port 4 incorporates pull-up resistors. use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the puo4 bit of the pull- up resistor option register (puo) and the port 4 mode register (pm4). when puo4 is 1, the internal pull-up resistors of the pins for which input is specified by the pm4 for port 4 (pm4n = 1, n = 0 to 7) are enabled . figure 5-42 pull-up resistor option register (puo) format 7 0 puo 6 puo6 5 puo5 4 puo4 3 puo3 2 puo2 1 puo1 0 puo0 address after reset r/w r/w 00h 0ff4eh puo4 port 4 pull-up resistor specification not used in port 4 used in port 4 1 0 caution when using the port 4 of the pd784038 as an address/data bus pin, and with the pd784031, be sure to clear puo4 to 0 to disconnect the internal pull-up resistor. remark when stop mode is entered, setting 00h in puo is effective in reducing the power consumption. figure 5-43 pull-up specification (port 4) p41 input buffer p40 p42 p46 p47 v dd0 port 4 mode register (pm4) puo4 (puo) internal bus chapter 5 port functions 151 user s manual u11316ej4v1ud 5.6.5 direct led drive in port 4, the output buffer low-level side drive capability has been reinforced, allowing active-low direct led drive. an example of such use is shown in figure 5-44. figure 5-44 example of direct led drive pd784038 p4n (n = 0 to 7) v dd0 5.7 port 5 port 5 is an 8-bit input/output port with an output latch. input/output can be specified bit-wise by means of the port 5 mode register (pm5). each pin incorporates a software programmable pull-up resistor. this port has direct led drive capability. in addition, p50 to p57 function as the address bus (a8 to a15) when external memory or i/os are extended. with the pd784031, p50 to p57 cannot be used as port pins. these pins function only as address bus pins (a8 to a15). when reset is input, port 5 is set as an input port (output high-impedance state), and the output latch contents are undefined. table 5-9 port 5 operating modes mm bits operating mode mm3 mm2 mm1 mm0 p50 p51 p52 p53 p54 p55 p56 p57 0 0 0 0 port (p50 to p57) 00 1 1 0 1 0 0 a8 a9 port 0 1 0 1 a8 a9 a10 a11 port 0 1 1 0 a8 a9 a10 a11 a12 a13 port 0 1 1 1 a8 a9 a10 a11 a12 a13 a14 a15 10 0 0 10 0 1 5.7.1 hardware configuration the port 5 hardware configuration is shown in figure 5-45. chapter 5 port functions 152 user s manual u11316ej4v1ud figure 5-45 port 5 block diagram v dd0 p5n n = 0 to 7 mm0 to mm3 rd puo wr puo puo5 wr pm5 pm5n wr p5 p5n rd pm5 rd p5 pull-up resistor option register port 5 mode register output latch internal data bus internal address bus input/ output control circuit chapter 5 port functions 153 user s manual u11316ej4v1ud 5.7.2 i/o mode/control mode setting the port 5 input/output mode is set for each pin by means of the port 5 mode register (pm5) as shown in figure 5-46. when port 5 pins can be used as port or address pins in 2-bit units, the setting is performed by means of the memory extension mode register (mm: see figure 23-1 ) as shown in table 5-10. with the pd784031, this port functions only as the address bus (a8 to a15). figure 5-46 port 5 mode register (pm5) format 7 pm57 pm5 6 pm56 5 pm55 4 pm54 3 pm53 2 pm52 1 pm51 0 pm50 address after reset r/w r/w ffh 0ff25h pm5n p5n pin input/output mode specification (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) 1 0 table 5-10 port 5 operating modes mm bits operating mode mm3 mm2 mm1 mm0 p50 p51 p52 p53 p54 p55 p56 p57 0 0 0 0 port (p50 to p57) 00 1 1 0 1 0 0 a8 a9 port 0 1 0 1 a8 a9 a10 a11 port 0 1 1 0 a8 a9 a10 a11 a12 a13 port 0 1 1 1 a8 a9 a10 a11 a12 a13 a14 a15 10 0 0 10 0 1 chapter 5 port functions 154 user s manual u11316ej4v1ud 5.7.3 operating status port 5 is an input/output port, with an alternate function as the address bus (a8 to a15). (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 5-47 port specified as output port internal bus output latch p5n n = 0 to 7 rd out wr port chapter 5 port functions 155 user s manual u11316ej4v1ud (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all outp ut latches irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input p ort is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the out put latch contents are output to the port pin). also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. figure 5-48 port specified as input port output latch p5n n = 0 to 7 rd in wr port internal bus caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins, the contents of the output latch of pins specified as inputs will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit operation instructions. (3) when used as address bus (a8 to a15) used automatically when an external address is accessed. chapter 5 port functions 156 user s manual u11316ej4v1ud 5.7.4 internal pull-up resistors port 5 incorporates pull-up resistors. use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the puo5 bit of the pull- up resistor option register (puo) and the port 5 mode register (pm5). when puo5 is 1, the internal pull-up resistors of the pins for which input is specified by the pm5 for port 5 (pm5n = 1, n = 0 to 7) are enabled . figure 5-49 pull-up resistor option register (puo) format 7 0 puo 6 puo6 5 puo5 4 puo4 3 puo3 2 puo2 1 puo1 0 puo0 address after reset r/w r/w 00h 0ff4eh puo5 port 5 pull-up resistor specification not used in port 5 used in port 5 1 0 caution when using the port 5 of the pd784038 as an address bus, and with the pd784031, be sure to clear puo5 to 0 to disconnect the internal pull-up resistor. remark when stop mode is entered, setting 00h in puo is effective in reducing the power consumption. figure 5-50 pull-up specification (port 5) p51 input buffer p50 p52 p56 p57 v dd0 port 5 mode register (pm5) puo5 (puo) internal bus chapter 5 port functions 157 user s manual u11316ej4v1ud 5.7.5 direct led drive in port 5, the output buffer low-level side drive capability has been reinforced, allowing active-low direct led drive. an example of such use is shown in figure 5-51. figure 5-51 example of direct led drive pd784038 p5n (n = 0 to 7) v dd0 chapter 5 port functions 158 user? manual u11316ej4v1ud 5.8 port 6 with pd784031 p60 to p63 are output port pins and p66 and p67 are input/output port pins with output latch. p64 to p67 incorporate a software programmable pull-up resistor. in addition to the functions as port pins, these pins also have various alternate-function control signal pin functions, as shown in table 5-11. operations as control pins are performed by the respective function operations. p64 and p65 cannot be used as port pins and function only as rd and wr output pins. when reset is input, the level of the above pins are set as follows: p60 to p63: low p64, p65: high p66, p67: input port (output high impedance) the higher 4 bits of the contents are undefined, and the lower 4 bits are reset to 0h. with other than pd784031 port 6 is an 8-bit input/output port with an output latch. p60 to p67 incorporate a software programmable pull-up resistor. in addition to its function as a port, port 6 also has various alternate-function control signal pin functions as shown in tabl e 5-11. operations as control pins are performed by the respective function operations. when reset is input, p60 to p67 are set as input port pins (output high-impedance state), and the output latch contents are undefined. table 5-11 port 6 operating modes pin name port mode control signal input/ operation to operate as control pins output mode p60 to p63 input/output ports note a16 to a19 outputs specified by bits mm3 to mm0 of the mm in 2-bit units p64 rd output p65 wr output p66 wait input specified by bits pwn1 & pwn0 (n = 0 to 7) of the pwc1 & pwc2 or setting p66 in the input mode hldrq input bus hold enabled by the hlde bit of the hldm p67 hldak output refrq output set (to 1) the rfen bit of the rfm notes 1. these pins of the pd784031 are output port pins. 2. with the pd784031, this pin cannot be used as a port pin. caution p60 to p63 of the pd784031 are in the output high-impedance state while the reset signal is input, but output a low level after the reset signal has been cleared. therefore, design the external circuit so that the low level may be output as the initial status. remark for details, refer to chapter 23 local bus interface function . with the pd784031, or when external memory extension mode is specified by bits mm3 to mm0 of the mm chapter 5 port functions 159 user? manual u11316ej4v1ud table 5-12 p60 to p65 control pin specification mm bits operating mode mm3 mm2 mm1 mm0 p60 p61 p62 p63 p64 p65 0 0 0 0 port (p60 to p65) 0011 0 1 0 0 port (p60 to p63) rd wr 0101 0110 0111 1 0 0 0 a16 a17 port 1 0 0 1 a16 a17 a18 a19 (a) port mode with pd784031 each port not specified as control mode, p66 and p67 serve as output port pins, and p66 and p67 can be specified as input/output bit-wise by means of the port 6 mode register (pm6). with other than pd784031 each port not specified as in control mode can be specified as input/output bit-wise by means of the port 6 mode register (pm6). (b) control signal input/output mode (i) a16 to a19 (address bus) upper address bus output pins when the external memory space is expanded (10000h to fffffh). these pins operate in accordance with the memory extension mode register (mm). (ii) rd (read strobe) the strobe signal for an external memory read operation. the operation of this pin is controlled by the memory expansion mode register (mm). with the pd784031, this pin always serves as an rd pin. (iii) wr (write strobe) pin that outputs the strobe signal for an external memory write operation. the operation of this pin is controlled by the memory expansion mode register (mm). with the pd784031, this pin always serves as a wr pin. (iv) wait (wait) wait signal input pin. operates in accordance with the programmable wait control registers (pwc1, pwc2). (v) hldrq (hold request) external bus hold request signal input pin. operates in accordance with the hold mode register (hldm). (vi) hldak (hold acknowledge) bus hold acknowledge signal output pin. operates in accordance with the hold mode register (hldm). chapter 5 port functions 160 user s manual u11316ej4v1ud (vii) refrq (refresh request) this pin outputs refresh pulses to pseudo-static memory when this memory is connected to it externally. operates in accordance with the refresh mode register (rfm). 5.8.1 hardware configuration the port 6 hardware configuration is shown in figures 5-52 to 5-55. figure 5-52 block diagram of p60 to p63 (port 6) v dd0 p6n n = 0 to 3 mm0 to mm3 rd puo wr puo puo6 wr pm6 pm6n wr p6 p6n rd pm6 rd p6 pull-up resistor option register port 6 mode register output latch internal data bus internal address bus input/ output control circuit remark the pd784031 does not have a function for input operation. chapter 5 port functions 161 user s manual u11316ej4v1ud figure 5-53 block diagram of p64 and p65 (port 6) wr puo rd puo wr p6 puo6 p64 (p65) wr pm6 p64 (p65) v dd0 external extension mode pm64 (pm65) rd signal (wr signal) rd pm6 rd p6 pull-up resistor option register port 6 mode register output latch internal bus selector chapter 5 port functions 162 user s manual u11316ej4v1ud figure 5-54 block diagram of p66 (port 6) p66 wr puo puo6 v dd0 rd puo wr pm6 pm66 wr p6 p66 hold enabled mode external wait specification wait input hold request input rd p6 rd pm6 pull-up resistor option register port 6 mode register output latch internal bus chapter 5 port functions 163 user s manual u11316ej4v1ud figure 5-55 block diagram of p67 (port 6) pm67 wr puo rd puo wr p6 puo6 p67 wr pm6 p67 v dd0 rd pm6 rd p6 hold enabled mode refresh mode pull-up resistor option register port 6 mode register output latch internal bus refresh signal hold acknowledge signal selector chapter 5 port functions 164 user s manual u11316ej4v1ud 5.8.2 i/o mode/control mode setting the port 6 input/output mode is set by means of the port 6 mode register (pm6) as shown in figure 5-56. operations for operating port 6 as control pins are shown in table 5-13. with the pd784031, p64 functions only as rd signal output pin, and p65, as wr signal output pin. table 5-13 port 6 operating modes pin name control signal i/o mode port mode operation to operate as control pins p60 a16 input/output port note p61 a17 p62 a18 p63 a19 p64 rd input/output port p65 wr p66 wait external wait input is specified by setting bits pwn1 and pwn0 (n = 0 to 7) and p66 of the pwc1 and pwc2 hldrq bus hold enabled by the hlde bit of the hldm p67 hldak refrq set (to 1) the rfen bit of the rfm note these pins of the pd784031 are output port pins. table 5-14 p60 to p65 control pin specification mm bits operating mode mm3 mm2 mm1 mm0 p60 p61 p62 p63 p64 p65 0 0 0 0 port (p60 to p65) 0011 0 1 0 0 port (p60 to p63) rd wr 0101 0110 0111 1 0 0 0 a16 a17 port 1 0 0 1 a16 a17 a18 a19 external memory extension mode specified by bits mm3 to mm0 of the mm (see table 5-14 ) with the pd784031, external memory extension mode specified by bits mm3 to mm0 of the mm (see table 5-14 ) chapter 5 port functions 165 user s manual u11316ej4v1ud figure 5-56 port 6 mode register (pm6) format 7 pm67 pm6 6 pm66 5 pm65 4 pm64 3 pm63 2 pm62 1 pm61 0 pm60 address after reset r/w r/w ffh 0ff26h pm6n p6n pin input/output mode specification (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) 1 0 remark the lower 4 bits (p60 to p63) of the pd784031 are output port pins. 5.8.3 operating status port 6 is an input/output port, with an alternate function as various control pins. (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 5-57 port specified as output port internal bus output latch p6n n = 0 to 7 rd out wr port chapter 5 port functions 166 user s manual u11316ej4v1ud (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all outp ut latches irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input p ort is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the out put latch contents are output to the port pin). also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. figure 5-58 port specified as input port output latch p6n n = 4 to 7 rd in wr port internal bus caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins, or port mode and control mode, the contents of the output latch of pins specified as inputs or pins specified as in the control mode will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit manipulation instructions. (3) when used as control pins cannot be manipulated or tested by software. chapter 5 port functions 167 user s manual u11316ej4v1ud 5.8.4 internal pull-up resistors p60 to p67 (p64 to p67 with the pd784031) incorporate pull-up resistors. use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the puo6 bit of the pull- up resistor option register (puo) and the port 6 mode register (pm6). when puo6 is 1, the internal pull-up resistors of the pins for which input is specified by the pm6 (pm6n = 1, n = 0 to 7) are enabled . p60 to p63 of the pd784031 are not connected to a pull-up resistor. figure 5-59 pull-up resistor option register (puo) format 7 0 puo 6 puo6 5 puo5 4 puo4 3 puo3 2 puo2 1 puo1 0 puo0 address after reset r/w r/w 00h 0ff4eh puo6 port 6 pull-up resistor specification not used in port 6 used in port 6 1 0 remark when stop mode is entered, setting 00h in puo is effective in reducing the power consumption. figure 5-60 pull-up specification (port 6) p65 p64 p66 p67 v dd0 port 6 mode register (pm6) puo6 (puo) internal bus input buffer chapter 5 port functions 168 user s manual u11316ej4v1ud 5.9 port 7 port 7 is an 8-bit input/output port. in addition to operating as an input/output port, it also operates as the a/d converter analog input pins (ani0 to ani7). input/output can be specified bit-wise by means of the port 7 mode register (pm7). pin levels can be read or tested at any time irrespective of alternate-function pin operations. when reset is input, port 7 is set as an input port (output high-impedance state), and the output latch contents are undefined. 5.9.1 hardware configuration the port 7 hardware configuration is shown in figure 5-61. figure 5-61 port 7 block diagram p7n (n = 0 to 7) wr p7 p7n rd pm7 pm7n wr pm7 a/d converter rd p7 port 7 mode register output latch internal bus chapter 5 port functions 169 user s manual u11316ej4v1ud 5.9.2 i/o mode/control mode setting the port 7 input/output mode is set for each pin by means of the port 7 mode register (pm7) as shown in figure 5-62. in addition to the operation of port 7 as an input/output port, analog signal input can be performed at any time. mode setting is not necessary. specification of the a/d conversion operation is performed by adm of the a/d converter (see chapter 14 a/d converter for details). figure 5-62 port 7 mode register (pm7) format 7 pm77 pm7 6 pm76 5 pm75 4 pm74 3 pm73 2 pm72 1 pm71 0 pm70 address after reset r/w r/w ffh 0ff27h pm7n p7n pin input/output mode specification (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) 1 0 5.9.3 operating status port 7 is an input/output port, with an alternate function as the a/d converter analog input pins (ani0 to ani7). (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 5-63 port specified as output port internal bus output latch p7n n = 0 to 7 rd out wr port chapter 5 port functions 170 user s manual u11316ej4v1ud (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all outp ut latches-irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input p ort is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the out put latch contents are output to the port pin). also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. figure 5-64 port specified as input port output latch p7n n = 0 to 7 rd in wr port internal bus caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins, the contents of the output latch of pins specified as inputs will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit operation instructions. 5.9.4 internal pull-up resistors port 7 does not incorporate pull-up resistors. 5.9.5 caution a voltage outside the range av ss to av ref1 must not be applied to pins for which p70 to p77 are used as ani0 to an17. see 14.5 cautions in chapter 14 ?/d converter for details. chapter 5 port functions 171 user s manual u11316ej4v1ud 5.10 port output check function the pd784038 has a function for reading and testing output port pin levels in order to improve the reliability of application systems. it is therefore possible to check the output data and the actual pin status as required. if there is a mismatch, app ropriate action can be taken, such as replacement with another system. special instructions, chkl and chkla, are provided to check the port status. these instructions perform a comparison by taking the exclusive or of the pin status and the output latch contents (in port mode), or the pin status and the internal cont rol output signal level (in control mode). example an example is shown below of a program that checks the pin status and output latch contents using the chkl instruction and chkla instruction. test : set1 p0.3 ; set bit 3 of port 0 chkl p0 ; check port 0 bne $ err1 ; branch to error processing (err1) in case of mismatch with output latch contents . . . err1 : chkla p0 ; faulty bit check bt a.7, $bit07 ; bit 7? bt a.6, $bit06 ; bit 6? . . . bt a.1, $bit01 ; bit 1? br $bit00 ; if none of the bits, bit 0 is faulty cautions 1. if each port is set to input mode, a comparison of the pin status with the output latch contents (or control output level) using the chkl or chkla instruction will always show a match whether the individual pins of the port are port pins or control pins. therefore, executing these instructions on a port set to input mode is actually ineffective. 2. if the output levels of a port in which control outputs and port outputs are mixed in a single port are checked with the chkl or chkla instruction, the input/output mode of control output pins should be set to input mode before executing these instructions (as the output levels of control outputs vary asynchronously, the output level cannot be checked with the chkl or chkla instruction). 3. as port 2 is an input-only port, a comparison of the pin status with the output latch contents using the chkl or chkla instruction will always show a match. therefore, executing these instructions on port 2 is actually ineffective. chapter 5 port functions 172 user s manual u11316ej4v1ud 5.11 cautions (1) all port pins become high-impedance after reset signal input (internal pull-up resistors are disconnected from the pins). if there is a problem with pins becoming high-impedance during reset input, this should be handled with external circuitry. (2) bit 7 of the pull-up resistor option register (puo) that sets the internal pull-up resistor connection is fixed at 0, but if 1 is written to bit 7 of the puo in the in-circuit emulator, 1 will be read. (3) output latch contents are not initialized by reset input. when a port is used as an output port, the output latch must be initialized without fail before turning on the output buffer. if the output latch is not initialized before turning on the output buffer, unexpected data will be output to the output port. similarly, for pins used as control pins, internal peripheral hardware initialization must be performed before performing the control pin specification. (4) as p22 to p26 are not pulled up immediately after a reset, an interrupt request flag may be set depending on the function of the alternate-function pins (intp1 to intp5). therefore, the interrupt request flags should be cleared after specifying pull-up in the initialization routine. (5) when p40 to p47 and p50 to p57 are used as the address/data bus and address bus respectively in the pd784038, and with the pd784038 bits puo4 and puo5 of the pull-up resistor option register (puo) must be set to 0 so that internal pull-up resistor connection is not performed. (6) p60 to p63 of the pd784031 are in the output high-impedance state while the reset signal is input, but output a low level after the reset signal has been cleared. therefore, design the external circuit so that the low level may be output as the initial status. (7) a voltage outside the range av ss to av ref1 must not be applied to pins for which p70 to p77 are used as ani0 to ani7. see 14.5 cautions in chapter 14 a/d converter for details. (8) a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins or port mode and control mode, the contents of the output latch of pins specified as inputs or pins specified as in control mode will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit operation instructions. (9) if each port is set to input mode, a comparison of the pin status with the output latch contents (or control output level) using the chkl or chkla instruction will always show a match whether the individual pins of the port are port pins or control pins. therefore, executing these instructions on a port set to input mode is actually ineffective. (10) if the output levels of a port in which control outputs and port outputs are mixed in a single port are checked with the chkl or chkla instruction, the input/output mode of control output pins should be set to input mode before executing these instructions (as the output levels of control outputs vary asynchronously, the output level cannot be checked with the chkl or chkla instruction). (11) as port 2 is an input-only port, a comparison of the pin status with the output latch contents using the chkl or chkla instruction will always show a match. therefore, executing these instructions on port 2 is actually ineffective. 173 user? manual u11316ej4v1ud chapter 6 real-time output function 6.1 configuration and function the real-time output function is implemented by hardware, including primarily port 0 and the port 0 buffer registers (p0h, p0l) , shown in figure 6-1. the real-time output function refers to the transfer to the output latch by hardware of data prepared in the p0h and p0l beforehand, simultaneously with the generation of an interrupt from timer/counter 1 or external interrupt, and its output off-c hip. the pins that output the data off-chip are called real-time output ports. the following two kinds of real-time output data are handled: 4 bits 2 channels 8 bits 1 channel by combining the real-time output function with the macro service function described later, the functions of a pattern generato r with programmable timing are implemented without software intermediation. this is ideally suited to stepping motor control, for example. figure 6-1 shows the block diagram of the real-time output port. chapter 6 real-time output function 174 user? manual u11316ej4v1ud figure 6-1 real-time output port block diagram internal bus selector rtpc byte p0mh extr p0ml intc11 intp0 intc10 extr trgp0 trgp0 p0ml p0mh byte 4-bit real-time output (p0h) 4-bit real-time output (p0l) 8-bit real-time output (p0) 4 4 output latch p0 p0h p0l port 0 buffer registers p07 p05 p06 p04 p03 p02 p01 p00 8 44 selector chapter 6 real-time output function 175 user s manual u11316ej4v1ud 6.2 real-time output port control register (rtpc) the rtpc is an 8-bit register that specifies the function of port 0. rtpc can be read or written to by an 8-bit manipulation instruction or bit-manipulation instruction. figure 6-2 shows the form at of rtpc. reset input clears the rtpc register to 00h. figure 6-2 real-time output port control register (rtpc) format 7 byte rtpc 6 0 5 0 4 p0mh 3 extr 2 0 1 trgp0 0 p0ml address after reset r/w r/w 00h 0ff2eh p0ml p00 to p03 function specification port mode real-time output port mode 1 0 extr trgp0 enabling of data transfer to output latch from p0h, p0l by intp0 not enabled (data transfer by intc10 only) transfer by either intp0 or intc10 transfer by intp0 only setting prohibited enabled byte = 0 : p0l only transferred byte = 1 : p0l/p0h transferred 1 1 0 0 1 01 0 p0mh p04 to p07 function specification port mode real-time output port mode 1 0 byte real-time output port operating mode 4-bit separate real-time output ports 8-bit real-time output port 1 0 caution when p0ml and p0mh bits are set (to 1), the corresponding port output buffer is turned on and the port 0 output latch contents are output irrespective of the contents of the port 0 mode register (pm0). the output latch contents should therefore be initialized before making a real-time output port specification. chapter 6 real-time output function 176 user s manual u11316ej4v1ud 6.3 real-time output port accesses the port 0 buffer registers (p0h, p0l) are mapped onto mutually independent addresses in the sfr area as shown in figure 6-3. when the 4-bit 2-channel real-time output function is specified, data can be set in the p0h, p0l independently of each other. when the 8-bit 1-channel real-time output function is specified, data can be set in p0h and p0l by writing 8-bit data to either one of the p0h or p0l. table 6-1 shows the operations when port 0, the p0h and p0l are manipulated. figure 6-3 port 0 buffer register (p0h, p0l) configuration high-order 4 bits p0h low-order 4 bits p0l 0ff0eh 0ff0fh table 6-1 operations when port 0 and port 0 buffer registers (p0h, p0l) are manipulated operating mode register read operation write operation high-order 4 bits low-order 4 bits high-order 4 bits low-order 4 bits 8-bit port mode p0 output latch output latch p0l buffer register note buffer register p0h buffer register note buffer register 8-bit real-time output p0 output latch port mode p0l buffer register buffer register p0h buffer register buffer register 4-bit separate real-time p0 output latch output port mode p0l buffer register note buffer register p0h buffer register note buffer register p00 to p03: ports p0 output latch output latch p04 to p07: real-time p0l buffer register note buffer register output port mode p0h buffer register note buffer register p00 to p03: real-time p0 output latch output latch output port mode p0l buffer register note buffer register p04 to p07: ports p0h buffer register note buffer register note the contents of p0h are read from the high-order 4 bits, and the contents of p0l from the low-order 4 bits. remark : the output latch and port 0 buffer registers are not affected. chapter 6 real-time output function 177 user s manual u11316ej4v1ud chapter 6 real-time output function 178 user s manual u11316ej4v1ud 6.4 operation when the port 0 function is specified as the real-time output port, the port 0 buffer register (p0h, p0l) contents are fetched into the output latch and output to the port 0 pins in synchronization with the generation of one of the trigger conditions sho wn in table 6-2. for example, the timer/counter 1 timer register 1 (tm1) and compare register (cr10, cr11) match signal (intc10, intc11) can be selected as the output trigger generation source. in this case, the port 0 pin output data can be changed to the p0h an d p0l values using the value set in the cr10, cr11 beforehand as the timing interval. combining this real-time output port funct ion with the macro service function enables the port 0 output pin output data to be changed sequentially at any interval time (see 22.8 macro service function ). if the intp0 external interrupt pin is selected as the output trigger source, port 0 output can be obtained in synchronization with an external event. table 6-2 real-time output port output triggers (when p0mh = p0ml = 1) rtpc output mode p0h p0l byte extr trgp0 0 0 0 4-bit real-time output intc11 intc10 0 1 0 intc11 intc10 or intp0 0 1 1 intc11 intp0 1 0 0 8-bit real-time output intc10 1 1 0 intc10 or intp0 1 1 1 intp0 chapter 6 real-time output function 179 user s manual u11316ej4v1ud figure 6-4 real-time output port operation timing intc11 interrupt request cpu operation timer/counter 1 0h ffh output latches p07 to p04 timer start port 0 buffer register p0h d01 cr11 cr11 cr11 cr11 d01 d02 d00 port 0 buffer register and compare register overwrite by software servicing or macro service (see 22.8 macro service function ) d03 d04 d02 d03 chapter 6 real-time output function 180 user s manual u11316ej4v1ud figure 6-5 real-time output port operation timing (2-channel independent control example) intc11 interrupt request cpu operation timer/counter 1 0h ffh timer start output latches p07 to p04 d00 port 0 buffer register p0h d01 cr11 cr11 cr11 cr11 cr10 cr10 cr10 intc10 interrupt request p0l d11 p03 to p00 d02 d03 d04 d14 d12 d13 d01 d02 d13 d11 d12 d10 d03 port 0 buffer register and compare register overwrite by software servicing or macro service ( see 22.8 macro service function ) chapter 6 real-time output function 181 user s manual u11316ej4v1ud 6.5 example of use the case in which p00 to p03 are used as a 4-bit real-time output port is shown here. each time the contents of timer/counter 1 timer register 1 (tm1) and compare register (cr10) match, the contents of port 0 buffer register (p0l) are output to p00 to p03. at this time, the next data to be output and the timing at which the output is to be changed next are set in the service routine for the simultaneously generated interrupt (see figure 6-6 ). see chapter 9 timer/counter 1 for the method of using timer/counter 1. the control register settings are shown in figure 6-7, the setting procedure in figure 6-8, and the processing in the interrupt service routine in figure 6-9. figure 6-6 real-time output port operation timing intc10 interrupt request timer/counter 1 0h ffh output pins p00 to p03 d01 d02 port 0 buffer register p0l d02 d03 cr10 cr10 cr10 cr10 output latches p00 to p03 d01 d02 d03 d04 d03 d01 d00 d00 p0l and cr10 overwritten by intc10 interrupt p0l contents transferred to output latch on match of tm1 and cr10 timer start output buffer turned on next data to be output is set in p0l initial output data is set in output latches p00 to p03 hi-z chapter 6 real-time output function 182 user s manual u11316ej4v1ud figure 6-7 real-time output function control register settings 7 0 rtpc 6 0 5 0 4 0 3 0 2 0 1 0 0 0 p00 to p03 used as real-time output port p04 to p07 used as normal output port 4-bit separate real-time output ports selected data transfer to output latch from p0l by intp0 disabled figure 6-8 real-time output function setting procedure real-time output port set initial value in p0 output latch set next value to be output in p0l set real-time output port control register (rtpc) set timer/counter 1 intc10 interrupt timer start chapter 6 real-time output function 183 user s manual u11316ej4v1ud figure 6-9 interrupt request servicing when real-time output function is used timer interrupt interval time setting set next value to be output in p0l return 6.6 cautions (1) when p0ml and p0mh bits are set (to 1), the corresponding port output buffer is turned on and the port 0 output latch contents are output irrespective of the contents of the port 0 mode register (pm0). the output latch contents should therefore be initialized before making a real-time output port specification. (2) when the port is specified as a real-time output port, values cannot be directly written to the output latch by software. therefore, the initial value of the output latch must be set by software before specifying use as a real-time output port. also, if the need arises to forcibly set the output data to a fixed value while the port is being used as a real-time output port, you should change the port to a normal output port by manipulating the real-time output port control register (rtpc), then write the value to be output to the output latch. 184 user? manual u11316ej4v1ud chapter 7 outline of timer/counter the pd784038 incorporates three timer/counter units and one timer unit. these timer/counter and timer units can be used as seven units of timer/counters because the pd784038 supports seven interrupt requests. table 7-1 operations of timer/counters name timer/counter 0 timer/counter 1 timer/counter 2 timer 3 item count 8 bits ?? width 16 bits ? operation interval timer 2 ch 2 ch 2 ch 1 ch mode external event counter ? one-shot timer function timer output 2 ch 2 ch toggle output pwm/ppg output one-shot pulse output note real-time output pulse width measurement 1 input 1 input 2 inputs number of interrupt requests 2 2 2 1 note in the one-shot pulse output function, the pulse output level activated by software and inactivated by hardware (an interrupt request signal). this function is different in nature from the one-shot timer function of timer/counter 2. chapter 7 outline of timer/counter 185 user? manual u11316ej4v1ud figure 7-1 timer/counter block diagram timer/counter 0 clear control intc00 compare register (cr00) pulse output control ovf intc01 to0 to1 timer register 0 (tm0) prescaler edge detection selector match match intp3 f xx /8 intp3 software trigger compare register (cr01) capture register (cr02) timer/counter 1 edge detection intp0 intp0 clear control compare register (cr10/cr10w) capture/compare register (cr11/cr11w) capture register (cr12/cr12w) ovf timer register 1 (tm1/tm1w) prescaler selector match f xx /8 event input to real-time output port intc11 intc10 match timer/counter 2 clear control intc20 compare register (cr20/cr20w) capture/compare register (cr21/cr21w) capture register (cr22/cr22w) pulse output control ovf intc21 to2 to3 timer register 2 (tm2/tm2w) prescaler edge detection selector match match intp1 f xx /8 intp2/ci intp1 intp2 edge detection timer 3 compare register (cr30/cr30w) timer register 3 (tm3/tm3w) prescaler match f xx /8 match csi intc30 remark ovf: overflow flag 186 user? manual u11316ej4v1ud chapter 8 timer/counter 0 8.1 functions timer/counter 0 is a 16-bit timer/counter. in addition to its basic functions of interval timer, programmable square-wave output, pulse width measurement and event counter, timer/counter 0 can be used for the following functions. pwm output cycle measurement ? soft triggered one-shot pulse output (1) interval timer generates internal interrupts at preset intervals. table 8-1 timer/counter 0 interval time minimum interval time maximum interval time resolution 8/f xx 2 16 8/f xx 8/f xx (0.25 s) (16.40 ms) (0.25 s) 16/f xx 2 16 16/f xx 16/f xx (0.50 s) (32.80 ms) (0.50 s) 32/f xx 2 16 32/f xx 32/f xx (1.00 s) (65.50 ms) (1.00 s) 64/f xx 2 16 64/f xx 64/f xx (2.00 s) (131 ms) (2.00 s) 128/f xx 2 16 128/f xx 128/f xx (4.00 s) (262 ms) (4.00 s) 256/f xx 2 16 256/f xx 256/f xx (8.00 s) (524 ms) (8.00 s) 512/f xx 2 16 512/f xx 512/f xx (16.00 s) (1.05 s) (16.00 s) 1,024/f xx 2 16 1,024/f xx 1,024/f xx (32.00 s) (2.10 s) (32.05 s) 2,048/f xx 2 16 2,048/f xx 2,048/f xx (64.00 s) (4.19 s) (64.00 s) ( ): when f xx = 32 mhz chapter 8 timer/counter 0 187 user? manual u11316ej4v1ud (2) programmable square-wave output outputs square waves independently to the timer output pins (to0, to1). table 8-2 timer/counter 0 programmable square-wave output setting range minimum pulse width maximum pulse width 8/f xx 2 16 8/f xx (0.25 s) (16.40 ms) 16/f xx 2 16 16/f xx (0.50 s) (32.80 ms) 32/f xx 2 16 32/f xx (1.00 s) (65.50 ms) 64/f xx 2 16 64/f xx (2.00 s) (131 ms) 128/f xx 2 16 128/f xx (4.00 s) (262 ms) 256/f xx 2 16 256/f xx (8.00 s) (524 ms) 512/f xx 2 16 512/f xx (16.00 s) (1.05 s) 1,024/f xx 2 16 1,024/f xx (32.00 s) (2.10 s) 2,048/f xx 2 16 2,048/f xx (64.00 s) (4.19 s) ( ): when f xx = 32 mhz chapter 8 timer/counter 0 188 user? manual u11316ej4v1ud (3) pulse width measurement detects the pulse width of the signal input to the external interrupt request input pin (intp3). table 8-3 timer/counter 0 pulse width measurement range measurable pulse width note resolution 8/f xx to 2 16 8/f xx 8/f xx (0.25 s) (16.40 ms) (0.25 s) 16/f xx to 2 16 16/f xx 16/f xx (0.50 s) (32.80 ms) (0.50 s) 32/f xx to 2 16 32/f xx 32/f xx (1.00 s) (65.50 ms) (1.00 s) 64/f xx to 2 16 64/f xx 64/f xx (2.00 s) (131 ms) (2.00 s) 128/f xx to 2 16 128/f xx 128/f xx (4.00 s) (262 ms) (4.00 s) 256/f xx to 2 16 256/f xx 256/f xx (8.00 s) (524 ms) (8.00 s) 512/f xx to 2 16 512/f xx 512/f xx (16.00 s) (1.05 s) (16.00 s) 1,024/f xx to 2 16 1,024/f xx 1,024/f xx (32.00 s) (2.10 s) (32.00 s) 2,048/f xx to 2 16 2,048/f xx 2,048/f xx (64.00 s) (4.19 s) (64.00 s) ( ): when f xx = 32 mhz note the minimum pulse width that can be measured differs depending on the selected value of f clk . the minimum pulse width that can be measured is the value of 4/f clk or the value in the above table, whichever is greater. (4) software triggered one-shot pulse output this is a one-shot pulse output function in which the pulse output level is activated by software and inactivated by hardware (an interrupt request signal). control can be performed for the timer output pins (to0, to1) independently. caution the software triggered one-shot pulse output function is different in nature from the one-shot timer function of timer/counter 2. chapter 8 timer/counter 0 189 user? manual u11316ej4v1ud (5) external event counter counts the clock pulses input from the external interrupt request input pin (intp3). the clocks that can be input to timer/counter 0 are shown in table 8-4. table 8-4 timer/counter 0 pulse width measurement time when counting one edge when counting both edges maximum frequency f clk /8 (2.00 mhz) f clk /8 (2.00 mhz) minimum pulse width 4/f clk (0.25 s) 4/f clk (0.25 s) (high and low levels) ( ): when f clk = 16 mhz 8.2 configuration timer/counter 0 consists of the following registers: timer register (tm0 1) compare register (cr00, cr01) 2 capture register (cr02) 1 the block diagram of timer/counter 0 is shown in figure 8-1. chapter 8 timer/counter 0 190 user? manual u11316ej4v1ud figure 8-1 timer/counter 0 block diagram internal bus 1/8 8/16 8 1/8 external interrupt mode register 1 (intm1) es31 es30 p24/intp3 edge detection circuit compare register (cr00) 16 16 16 mod1 mod0 clr01 pwm/ppg output control capture/compare control register 0 (crc0) ent01 alv1 ent00 alv0 timer output control register (toc) match p34/to0 intc00 p35/to1 intc01 reset clear overflow compare register (cr01) 16 16 16 16 16 16 8 selector prescaler f xx /2,048 f xx /1,024 f xx /512 f xx /256 f xx /128 f xx f xx /64 f xx /32 f xx /16 f xx /8 prescaler mode register 0 (prm0) prs03 prs02 prs01 prs00 capture register (cr02) timer register 0 (tm0) timer control register 1 (tmc1) ovf0 ce0 st1 rt1 os1 st0 rt0 os0 one-shot pulse control register (ospc) 1/8 1/8 internal bus capture trigger output control circuit output control circuit chapter 8 timer/counter 0 191 user s manual u11316ej4v1ud (1) timer register 0 (tm0) tm0 is a timer register that counts up using the count clock specified by the low-order 4 bits of prescaler mode register 0 (prm0). the count operation is stopped or enabled by means of timer control register 0 (tmc0). tm0 can be read only with a 16-bit manipulation instruction. when reset is input, tm0 is cleared to 0000h and the count is stopped. caution if the value of the timer register is read under the condition indicated by ?in table 8-5, the read value may be illegal. do not read the timer register under condition ? table 8-5 limits of reading timer register ( : can be read, : must not be read) f clk f xx /2 f xx /4 f xx /8 f xx /16 timer count clock f xx /8 ?? f xx /16 ??? f xx /n ??? remarks 1. f xx : oscillation frequency 2. f clk : internal system clock frequency 3. n = 32, 64, 128, 256, 512, 1,024, 2,048 (2) compare registers (cr00/cr01) cr00 and cr01 are 16-bit registers that hold the values that determine the interval timer frequency. if the cr00/cr01 contents match the contents of tm0, an interrupt request (intc00/intc01) and timer output control signal are generated. also, the count value can be cleared by a content match (cr01). cr00 and cr01 can be read or written with a 16-bit manipulation instruction. the contents of these registers are undefined after reset input. (3) capture register (cr02) cr02 is a 16-bit register that captures the contents of tm0. the capture operation is synchronized with the input of a valid edge (capture trigger) on the external interrupt request input pin (intp3). the contents of the cr02 are retained until the next capture trigger is generated. cr02 can be read only with a 16-bit manipulation instruction. reset input clears cr02 to 0000h. (4) edge detection circuit the edge detection circuit detects an external input valid edge. when the valid edge set by external interrupt mode register 1 (intm1) is detected in the intp3 pin input, the external interrupt request (intp3), a capture trigger, and a external event count clock are generated (see figure 21-2 for details of the intm1). chapter 8 timer/counter 0 192 user s manual u11316ej4v1ud (5) output control circuit it is possible to invert the timer output when the compare register (cr00, cr01) register contents and the contents of the timer register (tm0) match. a square wave can be output from the timer output pins (to0/to1) in accordance with the setting of the low-order 4 bits of the timer output control register (toc). at this time, pwm output or ppg output can be performed according to the specification of capture/compare control register 0 (crc0). in addition, one-shot pulse output can also be performed by means of a software trigger. timer output can be disabled/enabled by means of the toc. when timer output is disabled, a fixed level is output to the to0 and to1 pins (the output level is set by the toc). (6) prescaler the prescaler generates the count clock from the internal system clock. the clock generated by this prescaler is selected by the selector, and is used as the count clock by the timer register 0 (tm0) to perform count operations. (7) selector the selector selects a signal resulting from dividing the internal clock or the edge detected by the edge detection circuit as the count clock of timer register 0 (tm0). chapter 8 timer/counter 0 193 user s manual u11316ej4v1ud 8.3 timer/counter 0 control registers (1) timer control register 0 (tmc0) the timer/counter 0 tm0 count operation is controlled by the low-order 4 bits in the tmc0 (the high-order 4 bits control the count operation of the tm3/tm3w of the timer 3). tmc0 can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the format of the tmc0 is shown in figure 8-2. reset input clears tmc0 to 00h. figure 8-2 timer control register 0 (tmc0) format 7 ce3 tmc0 6 0 5 0 4 bw3 3 ce0 2 ovf0 1 0 0 0 address after reset r/w r/w 00h 0ff5dh ovf0 tm0 overflow flag no overflow overflow (count up from ffffh to 0000h) 1 0 ce0 tm0 count operation control count operation stopped with count cleared count operation enabled 1 0 controls count operation of the tm3/tm3w of the timer 3 (see figure 11-2 ). remark the ovf0 bit is reset by software only. chapter 8 timer/counter 0 194 user s manual u11316ej4v1ud (2) prescaler mode register 0 (prm0) the count clock of the timer/counter 0, tm0, is specified by the low-order 4 bits of the prm0 (the high-order 4 bits specify the count clock of the timer 3, tm3/tm3w). prm0 can be read/written with an 8-bit manipulation instruction. the format of the prm0 is shown in figure 8-3. reset input sets prm0 to 11h. figure 8-3 prescaler mode register 0 (prm0) format 7 prs3 prm0 6 prs2 5 prs1 4 prs0 3 prs03 2 prs02 1 prs01 0 prs00 address after reset r/w r/w (f xx = 32 mhz) 11h 0ff5ch prs03 prs02 prs01 prs00 timer/counter 0 tm0 count clock specification count clock [hz] specification setting prohibited f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 f xx /2,048 external clock (intp3) resolution [ s] 0.25 0.50 1.00 2.00 4.00 8.00 16.00 32.00 64.00 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 specifies count clock of the tm3/tm3w of the timer 3 (see figure 11-3 ). other than the above setting prohibited remark f xx : x1 input frequency or oscillation frequency chapter 8 timer/counter 0 195 user s manual u11316ej4v1ud (3) capture/compare control register 0 (crc0) the crc0 specifies the enabling conditions for the tm0 clear operation by a match signal between the contents of the compare register (cr01) and the timer register 0 (tm0) counter value, and the timer outputs (to0/to1) mode. crc0 can be read/written with an 8-bit manipulation instruction. the format of the crc0 is shown in figure 8-4. reset input sets crc0 to 10h. figure 8-4 capture/compare control register 0 (crc0) format 7 mod1 crc0 6 mod0 5 0 4 1 3 clr01 2 0 1 0 0 0 address after reset r/w r/w 10h 0ff30h mod1 mod0 clr01 timer output mode specification tm0 clear operation when tm0 = cr01 toggle output toggle output pwm output toggle output toggle output toggle output pwm output pwm output disabled to0 to1 setting prohibited setting prohibited setting prohibited disabled enabled disabled 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ppg output toggle output enabled chapter 8 timer/counter 0 196 user s manual u11316ej4v1ud (4) timer output control register (toc) toc is an 8-bit register that controls the active level of timer output and output enabling/disabling. the operation of the timer output pins (to0 and to1) by the timer/counter 0 is controlled by the low-order 4 bits (the high- order 4 bits control the operation of the timer output pins (to2 and to3 by the timer/counter 2). toc can be written to or read with an 8-bit manipulation instruction or bit manipulation instruction. the format of the toc is shown in figure 8-5. reset input clears toc to 00h. figure 8-5 timer output control register (toc) format 7 ento3 toc 6 alv3 5 ento2 4 alv2 3 ento1 2 alv1 1 ento0 0 alv0 address after reset r/w r/w 00h 0ff31h alv0 to0 pin active level toggle output specification or one-shot pulse output specification pwm/ppg output specification low level high level high level low level 1 0 ento0 to0 pin operation specification alv0 output pulse output enabled 1 0 ento1 to1 pin operation specification alv1 output pulse output enabled 1 0 controls timer output pins (to2, to3) by timer/ counter 2 (see figure 10-6 ). alv1 to1 pin active level toggle output specification or one-shot pulse output specification pwm/ppg output specification low level high level high level low level 1 0 chapter 8 timer/counter 0 197 user s manual u11316ej4v1ud (5) one-shot pulse output control register (ospc) the ospc is an 8-bit register that specifies enabling/disabling of one-shot pulse output by a software trigger and the output level, etc. ospc can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the format of the ospc is shown in figure 8-6. reset input clears ospc to 00h. figure 8-6 one-shot pulse output control register (ospc) format 7 st1 ospc 6 rt1 5 0 4 os1 3 st0 2 rt0 1 0 0 os0 address after reset r/w r/w 00h 0ff7dh os0 to0 pulse output type selection toggle output/pwm output/ppg output selectable software triggered one-shot pulse selectable 1 0 st0 to0 output control output not changed inactive level output to to0 0 0 rt0 1 0 active level output to to0 setting prohibited 1 1 1 0 os1 to1 pulse output type selection toggle output/pwm output/ppg output selectable software triggered one-shot pulse output 1 0 st1 to1 output control output not changed inactive level output to to1 0 0 rt1 1 0 active level output to to1 setting prohibited 1 1 1 0 remarks 1. the rt0, st0, rt1, and st1 bits are write-only, and show a value of 0 if read. 2. pin pulse output disabling/enabling and active level setting are performed by means of the timer output control register (toc). chapter 8 timer/counter 0 198 user s manual u11316ej4v1ud 8.4 16-bit timer register 0 (tm0) operation 8.4.1 basic operation in the timer/counter 0 count operation, an up-count is performed using the count clock specified by the low-order 4 bits of prescaler mode register 0 (prm0). count operation enabling/disabling is controlled by bit 3 (ce0) of timer control register 0 (tmc0). when the ce0 bit is set (to 1) by software, the contents of tm0 are cleared to 0000h on the first count clock, and then the up-count operation is perfo rmed. when the ce0 bit is cleared (to 0), tm0 becomes 0000h immediately, and capture operations and match signal generation are stopped. if the ce0 bit is set (to 1) again when it is already set (to 1), tm0 continues the count operation without being cleared. if the count clock is input when tm0 is ffffh, tm0 becomes 0000h. in this case, ovf0 bit is set (to 1) and an overflow signal is sent to the output control circuit. ovf0 bit is cleared by software only. the count operation is continued. when reset is input, tm0 is cleared to 0000h, and the count operation is stopped. chapter 8 timer/counter 0 199 user s manual u11316ej4v1ud figure 8-7 basic operation of timer register 0 (tm0) (a) count started tm0 ce0 0h 0h 1h 2h ffh 100h 101h 0h 1h 0h count started ce0 1 count stopped ce0 0 count started ce0 1 count clock f clk /8 (b) when 1 is written to the ce0 bit again after the count starts tm0 ce0 0h 0h 1h 2h 3h 4h 5h 6h count started ce0 1 rewrite ce0 1 count clock f clk /8 (c) operation when tm0 = ffffh tm0 ovf0 fffeh ffffh 0h cleared by software ovf0 0 count clock f clk /8 1h chapter 8 timer/counter 0 200 user s manual u11316ej4v1ud 8.4.2 clear operation (1) clear operation after a match with the compare register the timer register 0 (tm0) can be cleared automatically after a match with the compare register (cr01). when a clearance source arises, tm0 is cleared to 0000h on the next count clock. therefore, even if a clearance source arises, the value at the point at which the clearance source arose is retained until the next count clock arrives. figure 8-8 tm0 clearance by match with compare register (cr01) tm0 compare register (cr01) n cleared here count clock 0 1 n - 1 n tm0 and cr01 match (2) clear operation by the ce0 bit of the timer control register 0 (tmc0) the timer register 0 (tm0) is also cleared when the ce0 bit of tmc0 is cleared (to 0) by software. the clear operation is performed immediately after clearance (to 0) of the ce0 bit. chapter 8 timer/counter 0 201 user s manual u11316ej4v1ud figure 8-9 clear operation when ce0 bit is cleared (0) (a) basic operation tm0 ce0 n count clock n - 1 0 (b) restart before count clock input after clearance tm0 ce0 n 0 count clock n - 1 0 1 2 if the ce0 bit is set (to 1) before this count clock, the count starts from 0 on the count clock. (c) restart after count clock input after clearance tm0 ce0 n count clock n - 1 0 0 0 1 if the ce0 bit is set (to 1) from this count clock onward, the count starts from 0 on the count clock after the ce0 bit is set (to 1). chapter 8 timer/counter 0 202 user s manual u11316ej4v1ud 8.5 external event counter function the timer/counter 0 can count clock pulses input from the external interrupt request input pin (intp3). no special selection method is needed for the external event counter operating mode. when the timer register 0 (tm0) count clock is specified as external clock input by the setting of the low-order 4 bits of prescaler mode register 0 (prm0), tm0 oper ates as an external event counter. the maximum frequency of external clock pulses that can be counted by tm0 as the external event counter is 2.00 mhz (f clk = 16 mhz) irrespective of whether only one edge or both edges are counted on intp3 input. the pulse width of the intp3 input must be at least 4 system clocks (0.25 s: f clk = 16 mhz) for both the high level and low level. if the pulse width is shorter than this, the pulse may not be counted. the timer/counter 0 external event counter timing is shown in figure 8-10. figure 8-10 timer/counter 0 external event count timing (1/2) (1) counting one edge (maximum frequency = f clk /8) ici tm0 intp3 dn 4/f clk (min.) 4/f clk (min.) 8/f clk (min.) dn + 1 dn + 2 dn + 3 3 to 4/f clk remark ici: intp3 input signal after passing through edge detection circuit chapter 8 timer/counter 0 203 user s manual u11316ej4v1ud figure 8-10 timer/counter 0 external event count timing (2/2) (2) counting both edges (maximum frequency = f clk /8) ici tm0 intp3 dn + 1 dn dn + 2 dn + 3 dn + 4 dn + 5 4/f clk (min.) 4/f clk (min.) 8/f clk (min.) 3 to 4/f clk remark ici: intp3 input signal after passing through edge detection circuit the tm0 count operation is controlled by the ce0 bit of the timer control register 0 (tmc0) in the same way as with basic operation. when the ce0 bit is set (to 1) by software, the contents of tm0 are set to 0000h and the up-count is started on the initial cou nt clock. when the ce0 bit is cleared (to 0) by software during a tm0 count operation, the contents of tm0 are set to 0000h immediately and the stopped state is entered. the tm0 count operation is not affected if the ce0 bit is set (to 1) by software again when it is already set (to 1). caution when timer/counter 0 is used as an external event counter, it is not possible to distinguish between the case where there is no valid edge input at all and the case where there is a single valid edge input, using the timer register 0 (tm0) alone (see figure 8-11), since the contents of tm0 are 0 in both cases. if it is necessary to make this distinction, the intp3 interrupt request flag should be used. an example is shown in figure 8-12. figure 8-11 example of the case where the external event counter does not distinguish between one valid edge input and no valid edge input tm0 0 intp3 1 2 0 count start no distinction made chapter 8 timer/counter 0 204 user s manual u11316ej4v1ud figure 8-12 methods of enabling the external event counter to distinguish no valid edge input (a) processing when count is started clear intp3 interrupt request flag pif3 0 ; clear pif3 to 0 end start count start count ce0 1 ; set ce0 to 1 (b) processing when count value is read read tm0 contents ax tm0 ax ax + 1 ; check pif3 contents if 1, there is a valid edge ; number of input valid edges is set in ax register ; check tm0 value if 0, check interrupt request flag end pif3 = 1 ? yes yes no no count value read ax = 0 ? chapter 8 timer/counter 0 205 user s manual u11316ej4v1ud 8.6 compare register and capture register operation 8.6.1 compare operations timer/counter 0 performs compare operations in which the value set in compare registers (cr00, cr01) are compared with the timer register 0 (tm0) count value. if the count value of tm0 matches the preset cr0n (n = 0, 1) value as the result of the count operation, a match signal is sent to the output control circuit, and at the same time an interrupt request (intc00/intc01) is generated. after a match with the cr01 value, the tm0 count value can be cleared, and the timer functions as an interval timer that repeatedly counts up to the value set in the cr01. figure 8-13 compare operation intc00 interrupt request tm0 count value 0h ffffh count start ce0 1 cr00 value cr01 value ffffh cr00 value cr01 value intc01 interrupt request ovf0 match match match match cleared by software remark clr01 = 0 chapter 8 timer/counter 0 206 user s manual u11316ej4v1ud figure 8-14 tm0 clearance after match detection intc00 interrupt request tm0 count value 0h cr01 count start ce0 1 intc01 interrupt request cr00 clear clear cr01 cr00 remark clr01 = 0 chapter 8 timer/counter 0 207 user s manual u11316ej4v1ud 8.6.2 capture operations timer/counter 0 performs capture operations in which the timer register 0 (tm0) count value is fetched into the capture registe r in synchronization with an external trigger, and retained there. a valid edge detected from the input of the external interrupt request input pin (intp3) is used as the external trigger (capt ure trigger). the count value of tm0 in the process of being counted is fetched into the capture register (cr02) in synchronizatio n with the capture trigger, and is retained there. the contents of the cr02 are retained until the next capture trigger is gener ated. the capture trigger valid edge is set by means of external interrupt mode register 1 (intm1). if both rising and falling edges are set as capture triggers, the width of pulses input from off-chip can be measured. also, if a capture trigger is generated by a single edge, the input pulse cycle can be measured. see figure 21-2 in chapter 21 edge detection function for details of the intm1. figure 8-15 capture operation intp3 pin input intp3 interrupt request tm0 count value 0h ffffh ovf0 d0 d1 d2 count start ce0 1 d0 d1 d2 capture register (cr02) remark dn: tm0 count value (n = 0, 1, 2, ...) clr01 = 0 chapter 8 timer/counter 0 208 user s manual u11316ej4v1ud 8.7 basic operation of output control circuit the output control circuit controls the timer output pin (to0/to1) levels by means of overflow signals or match signals from the compare registers (cr00, cr01). the operation of the output control circuit is determined by the timer output control regi ster (toc), capture/compare control register 0 (crc0), and the one-shot pulse output control register (ospc) (see table 8-6 ). when to0, to1 signals are output to a pin, the relevant pin must be in control mode in the port 3 mode register (pmc3). chapter 8 timer/counter 0 209 user s manual u11316ej4v1ud table 8-6 timer output (to0/to1) operations toc ospc crc0 to1 to0 ento1 alv1 ento0 alv0 os1 os0 mod1 mod0 clr01 0 0/1 0 0/1 high/low level fixed high/low level fixed 0 0/1 1 0/1 000 high/low level fixed toggle output (active-low/high) 0 0/1 1 0/1 0010 high/low level fixed pwm output (active-high/low) 0 0/1 1 0/1 0100 high/low level fixed pwm output (active-high/low) 0 0/1 1 0/1 0111 high/low level fixed ppg output (active-high/low) 0 0/1 1 0/1 1 high/low level fixed one-shot pulse output (active-low/high) 1 0/1 0 0/1 0 0 toggle output (active-low/high) high/low level fixed 1 0/1 0 0/1 0 1 0 0 pwm output (active-high/low) high/low level fixed 1 0/1 0 0/1 0 11 toggle output (active-low/high) high/low level fixed 1 0/1 0 0/1 1 one-shot pulse output (active-low/high) high/low level fixed 10/110/10000 toggle output (active-low/high) toggle output (active-low/high) 10/110/100010 toggle output (active-low/high) pwm output (active-high/low) 10/110/100100 pwm output (active-high/low) pwm output (active-high/low) 10/110/100111 toggle output (active-low/high) ppg output (active-high/low) 1 0/1 1 0/1 0 1 0 toggle output (active-low/high) one-shot pulse output (active-low/high) 10/110/101100 pwm output (active-high/low) one-shot pulse output (active-low/high) 10/110/101111 toggle output (active-low/high) one-shot pulse output (active-low/high) 10/110/11000 one-shot pulse output (active-low/high) toggle output (active-low/high) 10/110/110010 one-shot pulse output (active-low/high) pwm output (active-high/low) 10/110/110100 one-shot pulse output (active-low/high) pwm output (active-high/low) 10/110/110111 one-shot pulse output (active-low/high) ppg output (active-high/low) 1 0/1 1 0/1 1 1 one-shot pulse output (active-low/high) one-shot pulse output (active-low/high) remarks 1. in the alvn (n = 0, 1) columns, the figures on the left and right of the slash ( / ) correspond to the items on the left and right of the slash in the ton (n = 0, 1) columns. 2. the mark indicates that the operation is the same for either 0 or 1, but some prohibited combinations are included (see figure 8-4 ). 3. use with combinations not shown in this table is prohibited. chapter 8 timer/counter 0 210 user s manual u11316ej4v1ud 8.7.1 basic operation setting (to 1) the enton (n = 0, 1) bit of the timer output control register (toc) enables timer output (ton: n = 0, 1) to be varied at a timing in accordance with the settings of mod0, mod1, and clr01 bits of capture/compare control register 0 (crc0) and the one-shot pulse output control register (ospc). clearing (to 0) enton sets the ton to a fixed level. the fixed level is determined by the alvn (n = 0, 1) bit of the toc. the level is high when alvn is 0, and low when 1. 8.7.2 toggle output toggle output is an operating mode in which the output level is inverted each time the compare register (cr00/cr01) value coincides with the timer register 0 (tm0) value. the output level of timer output (to0) is inverted by a match between cr00 and tm0, and the output level of to1 is inverted by a match between cr01 and tm0. when timer/counter 0 is stopped by clearing (to 0) the ce0 bit of the timer control register 0 (tmc0), the inactive level (alvn : n = 0, 1) is output. figure 8-16 toggle output operation ento0 tm0 count value 0h ffffh cr00 value cr01 value ffffh cr00 value cr01 value ffffh cr00 value cr01 value ffffh cr00 value cr01 value ffffh to0 output (alv0 = 1) ento1 instruction execution instruction execution instruction execution instruction execution to1 output (alv1 = 0) chapter 8 timer/counter 0 211 user s manual u11316ej4v1ud table 8-7 to0, to1 toggle output (f xx = 32 mhz) count clock minimum pulse width maximum interval time 8/f xx 0.25 s 16.40 ms 16/f xx 0.50 s 32.80 ms 32/f xx 1.00 s 65.50 ms 64/f xx 2.00 s 131 ms 128/f xx 4.00 s 262 ms 256/f xx 8.00 s 524 ms 512/f xx 16.00 s 1.05 s 1,024/f xx 32.00 s 2.10 s 2,048/f xx 64.00 s 4.19 s 8.7.3 pwm output (1) basic operation of pwm output in this mode, a pwm signal with the period in which timer register 0 (tm0) reaches a full count used as one cycle is output. the timer output (to0) pulse width is determined by the value of compare register (cr00), and the timer output (to1) pulse width is determined by the value of compare register (cr01). when this function is used, the clr01 bit of capture/compare control register 0 (crc0) must be set to 0. the pulse cycle and pulse width are as shown below. pwm cycle = 65,536 x/f xx pwm pulse width = cr0n x/f xx note ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048 note 0 cannot be set in the cr0n. duty = pwm pulse width = cr0n pwm cycle 65,536 remark n = 0, 1 figure 8-17 pwm pulse output cr00 interrupt timer count 0h ffffh count start cr00 ffffh ffffh pulse width pulse cycle to0 cr00 pulse width pulse cycle remark alv0 = 0 chapter 8 timer/counter 0 212 user s manual u11316ej4v1ud table 8-8 to0, to1 pwm cycle (f xx = 32 mhz) count clock minimum pulse width [ s] pwm cycle [s] pwm frequency [hz] f xx /8 0.25 0.02 61.0 f xx /16 0.50 0.03 30.5 f xx /32 1.00 0.07 15.3 f xx /64 2.00 0.13 7.6 f xx /128 4.00 0.26 3.8 f xx /256 8.00 0.52 1.9 f xx /512 16.00 1.05 0.8 f xx /1,024 32.00 2.10 0.5 f xx /2,048 64.00 4.19 0.2 figure 8-18 shows an example of 2-channel pwm output, and figure 8-19 shows the operation of the case where ffffh is set in the cr00. figure 8-18 example of pwm output using tm0 tm0 count value 0h cr00 ffffh intc00 cr01 cr00 ffffh cr01 cr00 ffffh intc01 to0 to1 remark alv0 = 0, alv1 = 0 chapter 8 timer/counter 0 213 user s manual u11316ej4v1ud figure 8-19 example of pwm output when cr00 = ffffh tm0 count value ffffh intc00 0 1 2 fffeh ffffh 0 1 2 fffeh count clock cycle t ffffh 0 pulse width t duty = 100 = 99.998 (%) . . 65,535 65,536 pulse c y cle = 65,536t to0 ovf flag remarks 1. alv0 = 0 2. t = x/f xx (x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048) chapter 8 timer/counter 0 214 user s manual u11316ej4v1ud (2) rewriting compare registers (cr00, cr01) the output level of the timer output (ton: n = 0, 1) does not change even if the cr0n (n = 0, 1) value matches the timer register 0 (tm0) value more than once during one pwm output cycle. figure 8-20 example of compare register (cr00) rewrite cr00 to0 tm0 count value 0h t1 t2 t1 t2 t1 t2 cr00 and tm0 values match, but to0 does not change here. cr00 rewrite ffffh t1 ffffh chapter 8 timer/counter 0 215 user s manual u11316ej4v1ud if a value smaller than that of the tm0 is set as the cr0n value, a 100% duty pwm signal will be output. cr0n rewriting should be performed by the interrupt due to a match between tm0 and the cr0n on which the rewrite is performed. figure 8-21 example of 100% duty with pwm output cr00 to0 tm0 count value 0h n1 n2 n3 n1 when value n2 which is smaller than the tm0 value n3 is written to cr00, the duty of this period will be 100%. ffffh ffffh ffffh ffffh n2 n2 n2 n1 remark alv0 = 0 chapter 8 timer/counter 0 216 user s manual u11316ej4v1ud (3) stopping pwm output if timer/counter 0 is stopped by clearing (to 0) the ce0 bit of the timer control register 0 (tmc0) during pwm signal output, the active level is output. figure 8-22 when timer/counter 0 is stopped during pwm signal output to0 tm0 count value 0h cr00 ffffh ffffh cr00 remark alv0 = 1 caution the output level of the ton (n = 0, 1) pin when timer output is disabled (enton = 0: n = 0, 1) is the inverse of the value set in alvn (n = 0, 1) bit. caution is therefore required as the active level is output when timer output is disabled when the pwm output function has been selected. chapter 8 timer/counter 0 217 user s manual u11316ej4v1ud 8.7.4 ppg output (1) basic operation of ppg output this function outputs a square-wave with the time determined by compare register cr01 value as one cycle, and the time determined by compare register cr00 value as the pulse width. the pwm cycle output by the pwm is made variable. this signal can only be output from the timer output (to0). when this function is used, the clr01 bit of capture/compare control register 0 (crc0) must be set to 1. the pulse cycle and pulse width are as shown below. ppg cycle = (cr01 + 1) x/f xx ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048 ppg pulse width = cr00 x/f xx where 1 cr00 cr01 note duty = ppg pulse width = cr00 note ppg cycle cr01 + 1 note both cr00 and cr01 cannot be cleared to 0 . figure 8-23 shows an example of ppg output using timer register 0 (tm0), figure 8-24 shows an example of the case where cr00 = cr01. figure 8-23 example of ppg output using tm0 intc01 tm0 count value 0h cr00 cr00 cr00 cr01 cr01 cr01 intc00 to0 (ppg output) pulse width count start pulse cycle to1 (timer output) remark alv0 = 0, alv1 = 0 chapter 8 timer/counter 0 218 user s manual u11316ej4v1ud table 8-9 to0 ppg output (f xx = 32 mhz) count clock minimum pulse width ppg cycle ppg frequency f xx /8 0.25 s 0.50 s to 16.40 ms 2,000 khz to 61.0 hz f xx /16 0.50 s 1.00 s to 32.80 ms 1,000 khz to 30.5 hz f xx /32 1.00 s 2.00 s to 65.50 ms 500 khz to 15.3 hz f xx /64 2.00 s 4.00 s to 0.13 s 250 khz to 7.6 hz f xx /128 4.00 s 8.00 s to 0.26 s 125 khz to 3.3 hz f xx /256 8.00 s 16.00 s to 0.52 s 62.5 khz to 1.9 hz f xx /512 16.00 s 32.00 s to 1.05 s 31.3 khz to 1.0 hz f xx /1,024 32.00 s 64.00 s to 2.10 s 15.6 khz to 0.5 hz f xx /2,048 64.00 s 128.00 s to 4.19 s 7.8 khz to 0.2 hz figure 8-24 example of ppg output when cr00 = cr01 tm0 count value n intc00 0 1 2 n - 1 n 0 1 2 n - 1 count cycle t n 0 pulse width = nt pulse cycle = (n + 1) t intc01 to0 remark alv0 = 0 t = x/f xx (x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048) chapter 8 timer/counter 0 219 user s manual u11316ej4v1ud (2) rewriting compare register (cr00) the output level of the timer output (to0) does not change even if the cr00 value matches the timer register 0 (tm0) value more than once during one ppg output cycle. figure 8-25 example of compare register (cr00) rewrite cr00 to0 tm0 count value 0h t1 t2 t1 t2 cr00 and tm0 values match, but to0 does not change here. cr00 rewrite cr01 t1 cr01 t1 t2 remark alv0 = 1 chapter 8 timer/counter 0 220 user s manual u11316ej4v1ud if a value equal to or less than the tm0 value is written to cr00 before the cr00 and tm0 match, the duty of the ppg cycle will be 100%. cr00 rewriting should be performed by the interrupt due to a match between tm0 and cr00. figure 8-26 example of 100% duty with ppg output cr00 to0 tm0 count value 0h n1 n2 n3 n1 when value n2 which is smaller than the tm0 value n3 is written to cr00 here, the duty of this period will be 100%. cr01 cr01 cr01 cr01 n2 n2 n2 n1 remark alv0 = 0 caution if the ppg cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of cr00 cannot be rewritten by interrupt processing that is performed on coincidence between tm0 and cr00. use another method (for example, to poll the interrupt request flags by software with all the interrupts masked). chapter 8 timer/counter 0 221 user s manual u11316ej4v1ud (3) rewriting compare register (cr01) if the current value of the cr01 is changed to a smaller value, and the cr01 value is made smaller than the timer register 0 (tm0) value, the ppg cycle at that time will be extended to the time equivalent to a full-count by tm0. if cr01 is rewritten after the compare register (cr00) and tm0 match, the output level at this time will be the inactive level until tm0 overflows and becomes 0, and will then return to normal ppg output. if cr01 is rewritten before cr00 and tm0 match, the active level will be output until cr00 and tm0 match. if cr00 and tm0 match before tm0 overflows and becomes 0, the inactive level is output at that point. when tm0 overflows and becomes 0, the active level will be output, and normal ppg output will be restored. cr01 rewriting should be performed by the interrupt due to a match between tm0 and cr01, etc. figure 8-27 example of extended ppg output cycle cr00 to0 tm0 count value 0h n3 n4 n2 if cr00 and tm0 match, to0 enters the inactive level. otherwise, it remains at the active level. full count value n4 n2 n3 n1 n2 cr01 n5 n3 n1 n1 n1 when value n2 which is smaller than the tm0 value n5 is written to cr01 here, the ppg cycle is extended. remark alv0 = 1 chapter 8 timer/counter 0 222 user s manual u11316ej4v1ud caution if the ppg cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of cr01 cannot be rewritten by interrupt processing that is performed on coincidence between the timer register (tm0) and compare register (cr01). use another method (for example, to poll the interrupt request flags by software with all the interrupts masked). (4) stopping ppg output if timer/counter 0 is stopped by clearing (to 0) the ce0 bit of the timer control register 0 (tmc0) during ppg signal output, the active level is output irrespective of the output level at the time it was stopped. figure 8-28 when timer/counter 0 is stopped during ppg signal output to0 tm0 count value 0h cr00 cr01 cr01 cr00 caution the output level of the ton (n = 0, 1) pin when timer output is disabled (enton = 0: n = 0, 1) is the inverse of the value set in alvn (n = 0, 1) bit. caution is therefore required as the active level is output when timer output is disabled when the ppg output function has been selected. chapter 8 timer/counter 0 223 user s manual u11316ej4v1ud 8.7.5 software triggered one-shot pulse output in the software triggered one-shot pulse output mode, a one-shot pulse is output by software. when the stn (n = 0/1) bit of the one-shot pulse output control register (ospc) is set (to 1), timer output pin (ton: n = 0, 1) is set to the active level. ton then remains at the active level until the timer register 0 (tm0) value and the compare reg ister (cr0n: n = 0, 1) value match, at which point ton changes to the inactive level. ton then remains at the inactive level until the stn bit is set again. ton can also be set to the inactive level by setting (to 1) the rtn bit (n = 0/1), and in the same way, ton remains at the inactive level until the stn bit is set again. to0 and to1 can be controlled independently. an example of software triggered one-shot pulse output is shown in figure 8-29. when timer/counter 0 is stopped by clearing (to 0) the ce0 bit of the tmc0, the level at the time was stopped is retained. figure 8-29 example of software triggered one-shot pulse output 0h ffffh count start software trigger st0 intc00 alv0 to0 active period 1 inactive level output caution 1 should not be written to stn and rtn simultaneously. chapter 8 timer/counter 0 224 user s manual u11316ej4v1ud 8.8 examples of use 8.8.1 operation as interval timer (1) when timer register 0 (tm0) is made free-running and a fixed value is added to the compare register (cr0n: n = 0, 1) in the interrupt service routine, tm0 operates as an interval timer with the added fixed value as the cycle (see figure 8-30 ). this interval timer can count within the range shown in table 8-1 (internal system clock f xx = 32 mhz). since tm0 has two compare registers, two interval timers with different cycles can be constructed. the control register settings are shown in figure 8-31, the setting procedure in figure 8-32, and the processing in the interru pt service routine in figure 8-33. figure 8-30 interval timer operation (1) timing mod (2n) intc00 interrupt request tm0 count value 0h ffffh compare register (cr00) n timer start mod (3n) mod (4n) ffffh n mod (2n) mod (3n) interval interval interval rewritten by interrupt program rewritten by interrupt program rewritten by interrupt program remark interval = n 8/f xx , 1 n ffffh chapter 8 timer/counter 0 225 user s manual u11316ej4v1ud figure 8-31 control register settings for interval timer operation (1) capture/compare control register 0 (crc0) 7 0 crc0 6 0 5 0 4 1 3 0 2 0 1 0 0 0 tm0 clearing disabled to0 & to1 both toggle outputs figure 8-32 interval timer operation (1) setting procedure interval timer (1) set count value in cr00 cr00 n intc00 interrupt ; set 1 in bit 3 of tmc0 set crc0 crc0 10h start count ce0 1 figure 8-33 interval timer operation (1) interrupt request servicing intc00 interrupt calculate timer value that will generate next interrupt cr00 cr00 + n other interrupt service program reti chapter 8 timer/counter 0 226 user s manual u11316ej4v1ud 8.8.2 operation as interval timer (2) tm0 operates as an interval timer that generates interrupts repeatedly with the preset count time as the interval (see figure 8-34 ). this interval timer can count within the range shown in table 8-1 (internal system clock f xx = 32 mhz). the control register settings are shown in figure 8-35, and the setting procedure in figure 8-36. figure 8-34 interval timer operation (2) timing n compare register (cr01) intc01 interrupt request tm0 count value 0h n n count start clear clear interrupt acknowledged interrupt acknowledged interval interval remark interval = (n + 1) 8/f xx , 0 n ffffh chapter 8 timer/counter 0 227 user s manual u11316ej4v1ud figure 8-35 control register settings for interval timer operation (2) capture/compare control register 0 (crc0) 7 0 crc0 6 0 5 0 4 1 3 1 2 0 1 0 0 0 tm0 cleared by match of cr01 & tm0 contents to0 & to1 both toggle outputs figure 8-36 interval timer operation (2) setting procedure interval timer (2) set count value in cr01 cr01 n intc01 interrupt ; set 1 in bit 3 of tmc0 set crc0 crc0 18h start count ce0 1 chapter 8 timer/counter 0 228 user s manual u11316ej4v1ud 8.8.3 pulse width measurement operation in pulse width measurement, the high-level or low-level width of external pulses input to the external interrupt request input pin (intp3) is measured. both the high-level and low-level widths of pulses input to the intp3 pin must be at least 3 system clocks (0.19 s: f clk = 16 mhz); if shorter than this, the valid edge will not be detected and a capture operation will not be performed. this pulse width measurement can be performed within the range shown in table 8-3 (f clk = 16 mhz). as shown in figure 8-37, the timer register 0 (tm0) value being counted is fetched into the capture register (cr02) in synchronization with a valid edge (specified as both rising and falling edges) in the intp3 pin input, and held there. the pul se width is obtained from the product of the difference between the tm0 count value (d n ) fetched into and held in the cr02 on detection of the nth valid edge and the count value (d n - 1 ) fetched and held on detection of valid edge n - 1, and the number of count clocks (x/f xx ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048). the control register settings are shown in figure 8-38, and the setting procedure in figure 8-39. figure 8-37 pulse width measurement timing d1 intp3 external input signal intp3 interrupt request tm0 count value 0h ffffh capture register (cr02) ovf0 d0 d0 d1 count start ffffh d2 d2 d3 capture capture capture capture (d1 to d0) 8/f xx (10,000h to d1 + d2) 8/f xx (d3 to d2) 8/f xx d3 cleared by software remark dn: tm0 count value (n = 0, 1, 2, ...) x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048 chapter 8 timer/counter 0 229 user s manual u11316ej4v1ud figure 8-38 control register settings for pulse width measurement (a) capture/compare control register 0 (crc0) 7 0 crc0 6 0 5 0 4 1 3 0 2 0 1 0 0 0 tm0 clearing disabled to0 & to1 both toggle outputs (b) external interrupt mode register 1 (intm1) 7 0 intm1 6 0 5 4 3 2 : don t care 1 1 0 1 both rising & falling edges specified as intp3 input valid edges figure 8-39 pulse width measurement setting procedure pulse width measurement set crc0 crc0 10h set intm1, set mk0l initialize capture value buffer memory x 0 0 start count ce0 1 enable interrupt ; specify both edges as intp3 input valid edges, release interrupt masking intp3 interrupt ; set 1 in bit 3 of tmc0 chapter 8 timer/counter 0 230 user s manual u11316ej4v1ud figure 8-40 interrupt request servicing that calculates pulse width intp3 interrupt calculate pulse width y n = cr02 x n store capture value in memory x n + 1 cr02 reti 8.8.4 operation as pwm output in pwm output, pulses with the duty ratio determined by the value set in the compare register (cr0n: n = 0, 1) are output (see figure 8-41 ). this pwm output duty ratio can be varied in the range 1/65,536 to 65,535/65,536 in 1/65,536 units. since timer register 0 (tm0) has two compare registers, two different pwm signals can be output. the control register settings are shown in figure 8-42, the setting procedure in figure 8-43, and the procedure for varying the duty in figure 8-44. figure 8-41 example of timer/counter 0 pwm signal output to0 (when active-low) tm0 count value 0h timer start ffffh cr00 ffffh cr00 ffffh cr00 chapter 8 timer/counter 0 231 user s manual u11316ej4v1ud figure 8-42 control register settings for pwm output operation (a) capture/compare control register 0 (crc0) 7 1 crc0 6 0 5 0 4 1 3 0 2 0 1 0 0 0 tm0 clearing disabled to0 & to1 both pwm outputs (b) timer output control register (toc) 7 toc 6 5 4 3 2 1 1 0 1 to0 = active-low pwm signal output to0 pwm output enabled (c) port 3 mode control register (pmc3) 7 pmc3 6 5 4 1 3 2 1 0 p34 pin set as to0 output chapter 8 timer/counter 0 232 user s manual u11316ej4v1ud figure 8-43 pwm output setting procedure pwm output set crc0 crc0 90h set toc set p34 pin to control mode pmc3.4 1 set initial value in cr00, cr01 ; set bit 3 of tmc0 start count ce0 1 chapter 8 timer/counter 0 233 user s manual u11316ej4v1ud figure 8-44 changing pwm output duty duty change processing set duty value in cr00 disable intc00 interrupts cmk00 1 reti ; set bit 4 of mk0l duty change preprocessing clear intc00 interrupt request flag cif00 0 enable intc00 interrupts cmk00 0 intc00 interrupt ; clear bit 7 of cic00 ; clear bit 4 of mk0l chapter 8 timer/counter 0 234 user s manual u11316ej4v1ud 8.8.5 operation as ppg output in ppg output, pulses with the cycle and duty ratio determined by the values set in the compare registers (cr0n: n = 0, 1) are output (see figure 8-45 ). the control register settings are shown in figure 8-46, the setting procedure in figure 8-47, and the procedure for varying the duty in figure 8-48. figure 8-45 example of timer/counter 0 ppg signal output to0 (when active-low) tm0 count value 0h timer start cr01 cr00 cr01 cr00 cr01 cr00 chapter 8 timer/counter 0 235 user s manual u11316ej4v1ud figure 8-46 control register settings for ppg output operation (a) capture/compare control register 0 (crc0) 7 1 crc0 6 1 5 0 4 1 3 1 2 0 1 0 0 0 tm0 cleared by match of tm0 & cr01 to0 = ppg output (b) timer output control register (toc) 7 toc 6 5 4 3 2 1 1 0 1 to0 = active-low ppg signal output to0 ppg output enabled (c) port 3 mode control register (pmc3) 7 pmc3 6 5 4 1 3 2 1 0 p34 pin set as to0 output chapter 8 timer/counter 0 236 user s manual u11316ej4v1ud figure 8-47 ppg output setting procedure ppg output set crc0 crc0 d8h set toc set p34 pin to control mode pmc3.4 1 set cycle in cr01 set duty in cr00 ; set bit 3 of tmc0 start count ce0 1 chapter 8 timer/counter 0 237 user s manual u11316ej4v1ud figure 8-48 changing ppg output duty duty change preprocessing clear intc00 interrupt request flag cif00 0 duty change processing set duty value in cr00 disable intc00 interrupts cmk00 1 reti intc00 interrupt ; clear bit 7 of cic00 ; clear bit 4 of mk0l ; set bit 4 of mk0l enable intc00 interrupts cmk00 0 chapter 8 timer/counter 0 238 user s manual u11316ej4v1ud 8.8.6 example of software triggered one-shot pulse output in the software triggered one-shot pulse output mode, a one-shot pulse is output in response to a trigger activated by software (see figure 8-49 ). the control register settings are shown in figure 8-50, and the setting procedure in figure 8-51. figure 8-49 example of timer/counter 0 one-shot pulse output to0 tm0 count value 0h ffffh count start cr00 ffffh set trigger chapter 8 timer/counter 0 239 user s manual u11316ej4v1ud figure 8-50 control register settings for one-shot pulse output (a) one-shot pulse output control register (ospc) 7 0 ospc 6 0 5 0 4 3 0 2 0 1 0 0 1 to0 = one-shot pulse output (b) capture/compare control register 0 (crc0) 7 0 crc0 6 0 5 0 4 1 3 0 2 0 1 0 0 0 tm0 clearing disabled to0 & to1 both toggle outputs (c) timer output control register (toc) 7 toc 6 5 4 3 2 1 1 0 1 to0 = active-high one-shot pulse signal output to0 one-shot pulse output enabled (d) port 3 mode control register (pmc3) 7 pmc3 6 5 4 1 3 2 1 0 p34 pin set as to0 output chapter 8 timer/counter 0 240 user s manual u11316ej4v1ud figure 8-51 one-shot pulse output setting procedure one-shot pulse output set ospc os0 1 ; set bit 3 of tmc0 ; set to one-shot pulse output mode set crc0 crc0 10h set p34 pin to control mode pmc 3.4 1 start count ce0 1 one-shot pulse output st0 1 set pulse width in cr00 chapter 8 timer/counter 0 241 user s manual u11316ej4v1ud 8.9 cautions (1) while timer/counter 0 is operating (while the ce0 bit of the timer control register 0 (tmc0) is set), malfunctioning may occ ur if the contents of the following registers are rewritten. this is because it is undefined which takes precedence in a contenti on the change in the hardware functions due to rewriting the register, or the change in the status because of the function before rewriting. therefore, be sure to stop the counter operation for the sake of safety before rewriting the contents of the following register s. prescaler mode register 0 (prm0) capture/compare control register 0 (crc0) timer output control register (toc) (2) if the contents of the compare register (cr0n: n = 0 or 1) coincide with those of tm0 operation when an instruction that sto ps timer register 0 (tm0) operation is executed, the counting operation of tm0 stops, but an interrupt request is generated. in order not to generate the interrupt when stopping the operation of tm0, mask the interrupt in advance by using the interrupt mask register before stopping tm0. example program that may generate interrupt request program that does not generate interrupt request clr1 ce0 or mk0l, #30h or mk0l, #30h clr1 ce0 clr1 cif00 clr1 cif01 interrupt request from timer/counter 0 occurs between these instructions disables interrupt from timer/counter 0 clears interrupt request flag for timer/counter 0 chapter 8 timer/counter 0 242 user s manual u11316ej4v1ud (3) up to 1 count clock is required after an operation to start timer/counter 0 (ce0 1) has been performed before timer/counter 0 actually starts (refer to figure 8-52 ). for example, when using timer/counter 0 as an interval timer, the first interval time is delayed by up to 1 clock. the second and those that follow are at the specified interval. figure 8-52 operation when counting is started count clock tm0 ce0 timing to start actual counting count start command (ce0 1) by software 0 0 123 (4) while an instruction that writes data to the compare register (cr0n: n = 0, 1) is executed, coincidence between cr0n, to which the data is to be written, and timer register 0 (tm0) is not detected. for example, if the contents of cr0n do not chang e before and after the writing, the interrupt request is not generated even if the value of tm0 coincides with the value of cr0n, nor does the timer output (ton: n = 0, 1) change. write data to cr0n when timer/counter 0 is executing counting operation, in the timing that the contents of tm0 do not coincide with the value of cr0n before and after writing (e.g., immediately after an interrupt request has been generated because tm0 and cr0n have coincided). (5) coincidence between timer register 0 (tm0) and compare register (cr0n: n = 0, 1) is detected only when tm0 is incremented. therefore, the interrupt request is not generated even if the same value as tm0 is written to cr0n, and the timer output (ton: n = 0, 1) does not change. (6) if the ppg cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of the cr0n cannot be rewritten by interrupt processing that is performed on coincidence between the timer register 0 (tm0) and the compare register (cr0n: n = 0, 1). use another method (for example, to poll the interrupt request flags by software with all the interrupts masked). chapter 8 timer/counter 0 243 user s manual u11316ej4v1ud (7) the output level of the ton (n = 0, 1) when the timer output is disabled (enton = 0: n = 0, 1) is the reverse value of the value set to the alvn (n = 0, 1) bit. note, therefore, that an active level is output when the timer output is disabled with t he pwm output function or ppg output function selected. (8) if the value of the timer register is read under the condition indicated by in table 8-10, the read value may be illegal. do not read the timer register under condition . table 8-10 limits of reading timer register ( : can be read, : must not be read) f clk f xx /2 f xx /4 f xx /8 f xx /16 timer count clock f xx /8 ?? f xx /16 ??? f xx /n ??? f xx : oscillation frequency 2. f clk : internal system clock frequency 3. n = 32, 64, 128, 256, 512, 1,024, 2,048 (9) when timer/counter 0 is used as an external event counter, it is not possible to distinguish between the case where there is no valid edge input at all and the case where there is a single valid edge input, using the timer register 0 (tm0) alone (refer to figure 8-53 ), since the contents of tm0 are 0 in both cases. if it is necessary to make this distinction, the intp3 interrupt request flag should be used. to make a distinction, use the interrupt request flag of intp3, as shown in figure 8-54. figure 8-53 example of the case where the external event counter does not distinguish between one valid edge input and no valid edge input intp3 tm0 0 1 2 0 cannot be distinguished count start chapter 8 timer/counter 0 244 user s manual u11316ej4v1ud figure 8-54 to distinguish whether one or no valid edge has been input with external event counter (a) processing on starting counting ; set ce3 to 1 ; clear pif3 to 0 clear intp3 interrupt request flag pif3 0 start count ce3 1 start count end (b) processing on reading count value number of input valid edges is set to ax register count value read read tm0 contents ax tm0 ax ax + 1 end ax = 0? pif3 = 1? ; ; check tm0 value. if 0, check interrupt request flag. check pif3 contents. if 1, valid edge is input. yes no yes no chapter 8 timer/counter 0 245 user? manual u11316ej4v1ud (10) if the count operation of tm0 stops at the timing at which compare register (cr00) and timer register 0 (tm0) match, the cr00/tm0 match interrupt may not be generated after timer/counter 0 is next started. if the tm0 count operation is stopped within 1.5 count clocks after a match between cr00 and tm0, the first match interrupt after timer/counter 0 is next started will not be generated. the second and subsequent interrupts operate normally. note that the timer output is unaffected by this bug. this bug occurs because the timer interrupt controller inadvertently masks interrupts if timer/counter 0 is stopped in the period indicated by the shaded area in the figure below. the interrupt controller is initialized by an overflow of timer/counter 0 or a match between cr01 and tm0. count clocks 1.5 count clocks not generated tm0 m + 1 m m ? 1 1 0 0 m mm nn m ? 1 cr00 cr01 ce0 cr00/tm0 match interrupt remark m < n do not stop timer/counter 0 within 1.5 count clocks after a match between cr00 and tm0. disable all interrupt requests (including macro servicing), read the value of the timer to be stopped, and wait until at least 1.5 count clocks have elapsed after a match between cr00 and tm0 before stopping timer/counter 0. 246 user? manual u11316ej4v1ud chapter 9 timer/counter 1 9.1 functions timer/counter 1 is 16-bit or 8-bit timer/counter. in addition to its basic functions of interval timer, pulse width measurement and event counter, timer/counter 1 can be used as a real-time output port output trigger generation timer. (1) interval timer generates internal interrupts at preset intervals. table 9-1 timer/counter 1 intervals minimum interval maximum interval resolution 8/f xx 2 16 8/f xx 8/f xx (0.25 s) (16.40 ms) (0.25 s) 16/f xx 2 16 16/f xx 16/f xx (0.50 s) (32.80 ms) (0.50 s) 32/f xx 2 16 32/f xx 32/f xx (1.00 s) (65.50 ms) (1.00 s) 64/f xx 2 16 64/f xx 64/f xx (2.00 s) (131 ms) (2.00 s) 128/f xx 2 16 128/f xx 128/f xx (4.00 s) (262 ms) (4.00 s) 256/f xx 2 16 256/f xx 256/f xx (8.00 s) (524 ms) (8.00 s) 512/f xx 2 16 512/f xx 512/f xx (16.00 s) (1.05 s) (16.00 s) 1,024/f xx 2 16 1,024/f xx 1,024/f xx (32.00 s) (2.10 s) (32.00 s) 2,048/f xx 2 16 2,048/f xx 2,048/f xx (64.00 s) (4.19 s) (64.00 s) ( ): when f xx = 32 mhz chapter 9 timer/counter 1 247 user? manual u11316ej4v1ud (2) pulse width measurement detects the pulse width of the signal input to the external interrupt request input pin intp0. table 9-2 timer/counter 1 pulse width measurement range measurable pulse width note resolution 8/f xx to 2 16 8/f xx 8/f xx (0.25 s) (16.40 ms) (0.25 s) 16/f xx to 2 16 16/f xx 16/f xx (0.50 s) (32.80 ms) (0.50 s) 32/f xx to 2 16 32/f xx 32/f xx (1.00 s) (65.50 ms) (1.00 s) 64/f xx to 2 16 64/f xx 64/f xx (2.00 s) (131 ms) (2.00 s) 128/f xx to 2 16 128/f xx 128/f xx (4.00 s) (262 ms) (4.00 s) 256/f xx to 2 16 256/f xx 256/f xx (8.00 s) (524 ms) (8.00 s) 512/f xx to 2 16 512/f xx 512/f xx (16.00 s) (1.05 s) (16.00 s) 1,024/f xx to 2 16 1,024/f xx 1,024/f xx (32.00 s) (2.10 s) (32.00 s) 2,048/f xx to 2 16 2,048/f xx 2,048/f xx (64.00 s) (4.19 s) (64.00 s) ( ): when f xx = 32 mhz note the minimum pulse width that can be measured changes depending on the sampling clock selected by the sampling clock select register (scs0). the minimum pulse width that can be measured is the value in the table below or above, whichever is greater. sampling clock minimum pulse width f clk f clk = f xx /2 4/f clk = 8/f xx (0.25 s) f clk = f xx /4 4/f clk = 16/f xx (0.50 s) f clk = f xx /8 4/f clk = 32/f xx (1.00 s) f clk = f xx /16 4/f clk = 64/f xx (2.00 s) f xx /64 256/f xx (8.00 s) f xx /28 512/f xx (16.00 s) f xx /256 1,024/f xx (32.00 s) chapter 9 timer/counter 1 248 user? manual u11316ej4v1ud (3) external event counter counts the clock pulses input from the external interrupt request input pin (intp0). the clocks that can be input to timer/counter 1 are shown in table 9-3. table 9-3 timer/counter 1 pulse width measurement time ( ): when f clk = 16 mhz and f xx = 32 mhz sampling clock note when counting one edge when counting both edges f clk maximum frequency f clk /8 (2.00 mhz) f clk /8 (2.00 mhz) minimum pulse width 4/f clk (0.25 s) 4/f clk (0.25 s) (high and low levels) f xx /64 maximum frequency f xx /512 (62.50 khz) f xx /512 (62.50 khz) minimum pulse width 256/f xx (8.00 s) 256/f xx (8.00 s) (high and low levels) f xx /128 maximum frequency f xx /1,024 (31.30 khz) f xx /1,024 (31.30 khz) minimum pulse width 512/f xx (16.00 s) 512/f xx (16.00 s) (high and low levels) f xx /256 maximum frequency f xx /2,048 (15.60 khz) f xx /2,048 (15.60 khz) minimum pulse width 1,024/f xx (32.00 s) 1,024/f xx (32.00 s) (high and low levels) note selected by means of the sampling clock selection register (scs0) 9.2 configuration timer/counter 1 consists of the following registers: timer register (tm1/tm1w) 1 compare register (cr10/cr10w) 1 capture/compare register (cr11/cr11w) 1 capture register (cr12/cr12w) 1 the block diagram of timer/counter 1 is shown in figure 9-1. chapter 9 timer/counter 1 249 user? manual u11316ej4v1ud figure 9-1 timer/counter 1 block diagram internal bus 1/8 8/16 8 external interrupt mode register 0 (intm0) es01 es00 p21/intp0 edge detection circuit 16 16 8/16 capture/compare register (cr11/cr11w) 16 8/16 16 16 16 8/16 8 selector prescaler f /1,024 f /512 f /256 f /128 f f /64 f /32 f /16 f /8 prescaler mode register 1 (prm1) prs13 prs12 prs11 prs10 capture register (cr12/cr12w) timer register 1 (tm1/tm1w) timer control register 1 (tmc1) ovf1 ce1 1/8 internal bus bw1 overflow cm selector 8 8 8 8 intp0 match match match match reset clr11 cm clr10 capture/compare control register 1 (crc1) intc10 real-time output port intc11 compare register (cr10/cr10w) selector capture trigger capture trigger clear chapter 9 timer/counter 1 250 user s manual u11316ej4v1ud (1) timer register 1 (tm1/tm1w) tm1//tm1w is a timer register that counts up using the count clock specified by the low-order 4 bits of prescaler mode register 1 (prm1). the count operation can be specified to stop or enable, and an 8-bit operation mode (tm1)/16-bit operation mode (tm1w) can be selected, by means of timer control register 1 (tmc1). tm1/tm1w can be read only with an 8/16-bit manipulation instruction. when reset is input, tm1/tm1w is cleared to 00h and the count is stopped. caution if the value of the timer register is read under the condition indicated by ?in table 9-4, the read value may be illegal. do not read the timer register under condition ? table 9-4 limits of reading timer register ( : can be read, : must not be read) f clk f xx /2 f xx /4 f xx /8 f xx /16 timer count clock f xx /8 ?? f xx /16 ??? f xx /n ??? remarks 1. f xx : oscillation frequency 2. f clk : internal system clock frequency 3. n = 32, 64, 128, 256, 512, 1,024, 2,048 (2) compare register (cr10/cr10w) cr10/cr10w is an 8/16-bit register that holds the value that determines the interval timer operation cycle. if the contents of the cr10/cr10w match the values of tm1/tm1w, an interrupt request (intc10) is generated. this match signal is also a real-time output port trigger signal. also, the count value can be cleared by a match. this compare register operates as cr10 in the 8-bit operating mode, and cr10w in the 16-bit operating mode. cr10/cr10w can be read or written to with an 8/16-bit manipulation instruction. the contents of this register are undefined after reset input. (3) capture/compare register (cr11/cr11w) cr11/cr11w is an 8/16-bit register that can be specified as a compare register for detecting a match with the tm1/tm1w count value or a capture register for capturing the tm1/tm1w count value according to the setting of capture/compare control register 1 (crc1). this capture/compare register operates as cr11 in the 8-bit operating mode, and cr11w in the 16-bit operating mode. cr11/cr11w can be read or written to with an 8/16-bit manipulation instruction. the contents of this register are undefined after reset input. (a) when specified as compare register cr11/cr11w functions as an 8/16-bit register that holds the value that determines the interval timer operation cycle. an interrupt request (intc11) is generated by a match between the contents of the cr11/cr11w register and the contents of tm1/tm1w. also, the count value can be cleared by a match. this match signal is also a real-time output port trigger signal. chapter 9 timer/counter 1 251 user s manual u11316ej4v1ud (b) when specified as capture register cr11/cr11w functions as an 8/16-bit register that captures the contents of tm1/tm1w in synchronization with the input of a valid edge (capture trigger) on the external interrupt request input pin (intp0). the contents of the cr11/cr11w are retained until the next capture trigger is generated. tm1/tm1w can be cleared after a capture operation. (4) capture register (cr12/cr12w) cr12/cr12w is an 8/16-bit register that captures the contents of tm1/tm1w. the capture operation is synchronized with the input of a valid edge (capture trigger) on the external interrupt request input pin (intp0). the contents of the cr12/cr12w are retained until the next capture trigger is generated. this capture/compare register operates as cr12 in the 8-bit operating mode, and cr12w in the 16-bit operating mode. cr12/cr12w can be read only with an 8/16-bit manipulation instruction. reset input clears this register to 0000h. (5) edge detection circuit the edge detection circuit detects an external input valid edge. when the valid edge set by external interrupt mode register 0 (intm0) is detected in the intp0 pin input, the external interrupt request (intp0), a capture trigger and a count clock of the external event are generated (see figure 21-1 for details of the intm0). (6) prescaler the prescaler generates the count clock from the internal system clock. the clock generated by this prescaler is selected by the selector, and is used as the count clock by the timer register 1 (tm1/tm1w) to perform count operations. (7) selector the selector selects a signal resulting from dividing the internal clock or the edge detected by the edge detection circuit as the count clock of timer register 1 (tm1/tm1w). chapter 9 timer/counter 1 252 user s manual u11316ej4v1ud 9.3 timer/counter 1 control registers (1) timer control register 1 (tmc1) tmc1 controls the timer/counter 1, tm1/tm1w, count operation by the low-order 4 bits (the high-order 4 bits control the count operation of timer/counter 2, tm2/tm2w). tmc1 can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the format of the tmc1 is shown in figure 9-2. reset input clears tmc1 to 00h. figure 9-2 timer control register 1 (tmc1) format 7 ce2 tmc1 6 ovf2 5 cmd2 4 bw2 3 ce1 2 ovf1 1 0 0 bw1 address after reset r/w r/w 00h 0ff5fh bw1 timer counter 1 bit length specification 8-bit operating mode 16-bit operating mode 1 0 ovf1 tm1/tm1w overflow flag no overflow overflow note 1 0 ce1 tm1/tm1w count operation control count operation stopped with count cleared count operation enabled 1 0 controls count operation of timer/counter 2 (tm2/tm2w) (see figure 10-2 ). note in 8-bit operating mode: count up from ffh to 00h in 16-b it operating mode: count up from ffffh to 0000h remark the ovf1 bit is reset by software only. chapter 9 timer/counter 1 253 user s manual u11316ej4v1ud (2) prescaler mode register 1 (prm1) the count clock of prm1 to timer/counter 1, tm1/tm1w, is specified by the low-order 4 bits (the high-order 4 bits specify the count clock to timer/counter 2, tm2/tm2w). prm1 can be read or written to with an 8-bit manipulation instruction. the format of the prm1 is shown in figure 9-3. reset input sets prm1 to 11h. figure 9-3 prescaler mode register 1 (prm1) format 7 prs23 prm1 6 prs22 5 prs21 4 prs20 3 prs13 2 prs12 1 prs11 0 prs10 address after reset r/w r/w (f xx = 32mhz) 11h 0ff5eh prs13 prs12 prs11 prs10 16-bit timer/counter 1 tm1/ tm1w count clock specification count clock [hz] specification setting prohibited f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 f xx /2,048 external clock (intp0) resolution [ s] 0.25 0.50 1.00 2.00 4.00 8.00 16.00 32.00 64.00 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 specifies count clock to tm2/tm2w of timer/counter 2 (see figure 10-3 ). other than the above setting prohibited remark f xx : x1 input frequency or oscillation frequency chapter 9 timer/counter 1 254 user s manual u11316ej4v1ud (3) capture/compare control register 1 (crc1) the crc1 specifies the operation of the capture/compare register (cr11/cr11w) and the enabling condition for a timer register 1 (tm1/tm1w) clear operation. crc1 can be read or written to with an 8-bit manipulation instruction. the format of the crc1 is shown in figure 9-4. reset input clears crc1 to 00h. figure 9-4 capture/compare control register 1 (crc1) format 7 0 crc1 6 0 5 0 4 0 3 clr11 2 cm 1 clr10 0 0 address after reset r/w r/w 00h 0ff32h clr10 tm1 clear operation when tm1 = cr10 tm1w clear operation when tm1w = cr10w disabled enabled 1 0 clr11 cm compare operation cr11/cr11w operation specification tm1/tm1w clearance operation disabled enabled (when tm1 & cr11 or tm1w & cr11w contents match) 1 0 0 0 capture operation disabled enabled (when tm1 contents are captured in cr11 or when tm1w contents are captured in cr11w) 1 0 1 1 caution even if an attempt is made to clear the timer register by inputting the capture request signal when the capture function of the timer is used, the timer register momentarily counts up immediately before it is cleared. consequently, if a value greater than the value of the timer register by 1 is set to the compare register when the capture request signal is input, the values of the compare register and timer register coincide, and an unnecessary interrupt will be generated (refer to figure 9-5). therefore, take the following operation into consideration when creating a program. chapter 9 timer/counter 1 255 user s manual u11316ej4v1ud chapter 9 timer/counter 1 256 user s manual u11316ej4v1ud 9.4 timer register 1 (tm1) operation 9.4.1 basic operation 8-bit operating mode/16-bit operating mode control can be performed for timer/counter 1 by means of bit 0 (bw1) of timer control register 1 (tmc1). note in the timer/counter 1 count operation, an up-count is performed using the count clock specified by the low-order 4 bits of prescaler mode register 1 (prm1). count operation enabling/disabling is controlled by bit 3 (ce1) of tmc1 (timer/counter 1 operation control is performed by the low-order 4 bits of the tmc1). when the ce1 bit is set (to 1) by software, the contents of tm1 are cleared to 0h on the fi rst count clock, and then the up-count operation is performed. when the ce1 bit is cleared (to 0), tm1 becomes 0h immediately, and capture operations and match signal generation are stopped. if the ce1 bit is set (to 1) again when it is already set (to 1), tm1 continues the count operation without being cleared. if the count clock is input when tm1 is ffh in 8-bit operating mode and when tm1w is ffffh in 16-bit operating mode, tm1/ tm1w becomes 0h. in this case, ovf1 bit is set. ovf1 bit is cleared by software only. the count operation is continued. when reset is input, tm1 is cleared to 0h, and the count operation is stopped. note unless otherwise specified, the functions of timer register 1 in the 8-bit operating mode are described hereafter. in the 16-bit operating mode, tm1, cr10, cr11, and cr12 operate as tm1w, cr10w, cr11w, and cr12w, respectively. chapter 9 timer/counter 1 257 user s manual u11316ej4v1ud figure 9-6 basic operation in 8-bit operating mode (bw1 = 0) (a) count started tm1 ce1 0h 0h 1h 2h 0fh 10h 11h 0h 1h 0h count started ce1 1 count stopped ce1 0 count started ce1 1 count clock (b) when 1 is written to the ce1 bit again after the count starts tm1 ce1 count started ce1 1 rewrite ce1 1 count clock 0h 0h 1h 2h 3h 4h 5h 6h (c) operation when tm1 = ffh tm1 ovf1 feh ffh 0h cleared by software ovf1 0 count clock 1h chapter 9 timer/counter 1 258 user s manual u11316ej4v1ud figure 9-7 basic operation in 16-bit operating mode (bw1 = 1) (a) count started tm1w ce1 0h 0h 1h 2h ffh 100h 101h 0h 1h 0h count started ce1 1 count stopped ce1 0 count started ce1 1 count clock (b) when 1 is written to the ce1 bit again after the count starts tm1w ce1 count started ce1 1 rewrite ce1 1 count clock 0h 0h 1h 2h 3h 4h 5h 6h (c) operation when tm1w = ffffh tm1w ovf1 fffeh ffffh 0h cleared by software ovf1 0 count clock 1h chapter 9 timer/counter 1 259 user s manual u11316ej4v1ud 9.4.2 clear operation (1) clear operation after match with compare register and after capture operation timer register 1 (tm1) can be cleared automatically after a match with the compare register (cr1n: n = 0, 1) and a capture operation. when a clearance source arises, tm1 is cleared to 0h on the next count clock. therefore, even if a clearance source arises, the value at the point at which the clearance source arose is retained until the next count clock arrives. figure 9-8 tm1 clearance by match with compare register (cr10, cr11) tm1 compare register (cr1n) cleared here count clock n tm1 and cr1n match n01 n - 1 figure 9-9 tm1 clearance after capture operation tm1 intp0 tm1 is captured in cr11 here cleared here count clock n01 2 n - 1 (2) clear operation by ce1 bit of timer control register 1 (tmc1) timer register 1 (tm1) is also cleared when the ce1 bit of tmc1 is cleared (to 0) by software. the clear operation is performed immediately after the clearance (to 0) of the ce1 bit. chapter 9 timer/counter 1 260 user s manual u11316ej4v1ud figure 9-10 clear operation when ce1 bit is cleared (0) (a) basic operation tm1 ce1 n count clock n - 1 0 (b) restart before count clock is input after clearance tm1 ce1 n count clock n - 1 0 0 1 2 if the ce1 bit is set (to 1) before this count clock, this count clock starts counting from 0. (c) restart after count clock is input after clearance tm1 ce1 n0 count clock n - 1 0 0 1 if the ce1 bit is set (to 1) from this count clock onward, the count clock starts counting from 0 after the ce1 bit is set (to 1). chapter 9 timer/counter 1 261 user s manual u11316ej4v1ud 9.5 external event counter function timer/counter 1 can count clock pulses input from the external interrupt request input pin (intp0) pin. no special selection method is needed for the external event counter operating mode. when the timer register 1 (tm1) count clock is specified as external clock input by the setting of the low-order 4 bits of prescaler mode register 1 (prm1), tm1 oper ates as an external event counter. the maximum frequency of the external clock pulse that can be counted by the external event counter is determined by the sampling clock select register (scs0) as shown in table 9-5. the maximum frequency is the same when both the edges of the intp0 input are counted and when only one edge is counted. the pulse width of the intp0 input must be three or more sampling clocks selected by scs0, regardless of whether the level is high or low. if the width is shorter than this, the pulse may not be counted. figure 9-11 shows the timing of the external event count by timer/counter 1. table 9-5 maximum input frequency and minimum input pulse width that can be counted as events ( ): f xx = 32 mhz, f clk = 16 mhz sampling clock selected by scs0 maximum input frequency minimum pulse width f clk f clk /8 (2.00 mhz) 4/f clk (0.25 s) f clk /64 f clk /512 (31.30 khz) 256/f xx (8.00 s) f clk /128 f clk /1,024 (15.60 khz) 512/f xx (16.00 s) f clk/ 256 f clk /2,048 (7.81 khz) 1,024/f xx (32.00 s) figure 9-11 timer/counter 1 external event count timing (1) counting one edge (maximum frequency = f clk /8) ici tm1 intp0 dn dn + 1 dn + 2 dn + 3 4/f smp (min.) 4/f smp (min.) 8/f smp (min.) 3 to 4/f smp remarks 1. ici: intp0 input signal after passing through edge detection circuit 2. f smp is selected by the sampling clock selection register (scs0). chapter 9 timer/counter 1 262 user s manual u11316ej4v1ud (2) counting both edges (maximum frequency = f clk /8) ici tm1 intp0 dn + 1 dn dn + 2 dn + 3 dn + 4 dn + 5 4/f smp (min.) 4/f smp (min.) 8/f smp (min.) 3 to 4/f smp remarks 1. ici: intp0 input signal after passing through edge detection circuit 2. f smp is selected by the sampling clock selection register (scs0). the tm1 count operation is controlled by the ce1 bit of the timer control register 1 (tmc1) in the same way as with the basic operation. when the ce1 bit is set (to 1) by software, the contents of tm1 are set to 0h and the up-count operation is started on the initial count clock. when the ce1 bit is cleared (to 0) by software during a tm1 count operation, the contents of tm1 are set to 0h immediately and the stopped state is entered. the tm1 count operation is not affected if the ce1 bit is set (to 1) by software again when it is already set (to 1). caution when timer/counter 1 is used as an external event counter, it is not possible to distinguish between the case where there is no valid edge input at all and the case where there is a single valid edge input using the timer register 1 (tm1) alone (see figure 9-12), since the contents of tm1 are 0 in both cases. if it is necessary to make this distinction, the intp0 interrupt request flag should be used. an example is shown in figure 9-13. figure 9-12 example of the case where the external event counter does not distinguish between one valid edge input and no valid edge input tm1 0 intp0 1 2 0 count start no distinction made chapter 9 timer/counter 1 263 user s manual u11316ej4v1ud figure 9-13 methods of enabling the external event counter to distinguish no valid edge input (a) processing when count is started clear intp0 interrupt request flag pif0 0 ; clear pif0 to 0 end start count ; set ce1 to 1 start count ce1 1 (b) processing when count value is read read tm1 contents a tm1 ; check pif0 contents if 1, there is a valid edge ; number of input valid edges is set in a register ; check tm1 value if 0, check interrupt request flag end pif0 = 1 ? yes yes no no count value read a = 0 ? a a + 1 chapter 9 timer/counter 1 264 user s manual u11316ej4v1ud 9.6 compare register, capture/compare register, and capture register operation 9.6.1 compare operations timer/counter 1 performs compare operations in which the value set in a compare register (cr10), capture/compare register (cr11), specified for compare operation is compared with the timer register 1 (tm1) count value. if the count value of tm1 matches the preset value of the cr10, or the cr11 as the result of the count operation, an interrupt request signal (intc10 or intc11) is generated. after a match with the cr10 or cr11 value, the tm1 contents can be cleared, and the timer functions as an interval timer that repeatedly counts up to the value set in the cr10 or cr11. figure 9-14 compare operation in 8-bit operating mode intc10 interrupt request tm1 count value 0h count start ce1 1 cr10 value ovf1 intc11 interrupt request ffh cr11 value match match remark clr10 = 0, clr11 = 0, cm = 0, bw1 = 0 chapter 9 timer/counter 1 265 user s manual u11316ej4v1ud figure 9-15 compare operation in 16-bit operating mode intc10 interrupt request tm1w count value 0h ffffh count start ce1 1 cr10w value cr11w value ffffh cr10w value cr11w value intc11 interrupt request ovf1 cleared by software match match match match remark clr10 = 0, clr11 = 0, bw1 = 1 figure 9-16 tm1 clearance after match detection intc10 interrupt request tm1 count value 0h cr11 count start ce1 1 clr10 0 clr11 1 ce1 0 clr10 1 clr11 0 intc11 interrupt request cr10 cr10 cr10 count disabled ce1 0 count start clear clear clear chapter 9 timer/counter 1 266 user s manual u11316ej4v1ud 9.6.2 capture operations timer/counter 1 performs capture operations in which the timer register 1 (tm1) count value is fetched into the capture register in synchronization with an external trigger, and retained there. a valid edge detected from the input of the external interrupt request input pin (intp0) is used as the external trigger (captu re trigger). the count value of tm1 in the process of being counted is fetched into the capture register (cr12), or the capture/ compare register (cr11) when a capture operation is specified, in synchronization with the capture trigger, and is retained the re. the contents of the cr11 and cr12 are retained until the next capture trigger is generated. the capture trigger valid edge is set by means of external interrupt mode register 0 (intm0). if both rising and falling edges are set as capture triggers, the width of pulses input from off-chip can be measured, and if a capture trigger is generated by a single edge, the input pulse cycle can be measured. see figure 21-1 in chapter 21 edge detection function for details of the intm0 format. when cr11 is used as a capture register, tm1 can be cleared as soon as the contents of tm1 have been captured to cr11 by capture trigger. figure 9-17 capture operation in 8-bit operating mode intp0 pin input intp0 interrupt request tm1 count value 0h ffh capture/compare register (cr11) ovf1 count start d0 d1 d2 d0 d1 d2 remark dn: tm1 count value (n = 0, 1, 2, ...) clr10 = 0, clr11 = 0, cm = 1, bw1 = 0 chapter 9 timer/counter 1 267 user s manual u11316ej4v1ud figure 9-18 capture operation in 16-bit operating mode intp0 pin input intp0 interrupt request tm1w count value 0h ffffh capture register (cr12w) ovf1 count start ce1 1 d0 d1 d2 d0 d1 d2 remark dn: tm1w count value (n = 0, 1, 2, ...) clr10 = 0, clr11 = 0, cm = 1, bw1 = 1 chapter 9 timer/counter 1 268 user s manual u11316ej4v1ud figure 9-19 tm1 clearance after capture operation intp0 pin input intp0 interrupt request tm1 count value 0h capture/compare register (cr11) n1 capture capture capture capture capture n2 n3 n4 n5 n3 n2 n4 n1 remark ni: tm1 count value (n = 0, 1, 2, ...) clr10 = 0, clr11 = 1, cm = 1 caution even if an attempt is made to clear the timer register by inputting the capture request signal when the capture function of the timer is used, the timer register momentarily counts up immediately before it is cleared. consequently, if a value greater than the value of the timer register by 1 is set to the compare register when the capture request signal is input, the values of the compare register and timer register coincide, and an unnecessary interrupt will be generated (refer to figure 9-20). therefore, take the following operation into consideration when creating a program. chapter 9 timer/counter 1 269 user s manual u11316ej4v1ud chapter 9 timer/counter 1 270 user s manual u11316ej4v1ud 9.7 examples of use 9.7.1 operation as interval timer (1) when timer register 1 (tm1) is made free-running and a fixed value is added to the compare register (cr1n: n = 0, 1) in the interrupt service routine, tm1 operates as an interval timer with the added fixed value as the cycle (see figure 9-21 ). since tm1 has two compare registers, two interval timers with different intervals can be constructed. the control register settings are shown in figure 9-22, the setting procedure in figure 9-23, and the processing in the interru pt service routine in figure 9-24. figure 9-21 interval timer operation (1) timing mod (2n) intc10 interrupt request tm1 count value 0h ffh compare register (cr10) n timer start mod (3n) mod (4n) ffh n mod (2n) mod (3n) interval interval interval rewritten by interrupt program rewritten by interrupt program rewritten by interrupt program remark interval = n x/f xx , 1 n ffh x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048 chapter 9 timer/counter 1 271 user s manual u11316ej4v1ud figure 9-22 control register settings for interval timer operation (1) (a) prescaler mode register 1 (prm1) 7 prm1 6 5 4 3 prs13 2 prs12 1 prs11 0 prs10 count clock specification (x/f xx ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048) (b) capture/compare control register 1 (crc1) 7 0 crc1 6 0 5 0 4 0 3 0 2 0 1 0 0 0 tm1 clearing by match of cr10 & tm1 contents disabled cr11 specified as compare register tm1 clearing by match of cr11 & tm1 contents disabled chapter 9 timer/counter 1 272 user s manual u11316ej4v1ud figure 9-23 interval timer operation (1) setting procedure interval timer (1) set count value in cr10 cr10 n start count ce1 1 intc10 interrupt ; set 1 in bit 3 of tmc1 set prm1 set crc1 crc1 00h figure 9-24 interval timer operation (1) interrupt request servicing intc10 interrupt calculate timer value that will generate next interrupt cr10 cr10 + n other interrupt service program reti chapter 9 timer/counter 1 273 user s manual u11316ej4v1ud 9.7.2 operation as interval timer (2) tm1 operates as an interval timer that generates interrupts repeatedly with the preset count time as the interval (see figure 9-25 ). the control register settings are shown in figure 9-26, and the setting procedure in figure 9-27. figure 9-25 interval timer operation (2) timing (when cr11 is used as compare register) compare register (cr11) intc11 interrupt request tm1 count value 0h n n n count start clear clear interval match match interrupt acknowledge interrupt acknowledge interval remark interval = (n + 1) x/f xx 0 n ffh x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048 chapter 9 timer/counter 1 274 user s manual u11316ej4v1ud figure 9-26 control register settings for interval timer operation (2) (a) prescaler mode register 1 (prm1) 7 prm1 6 5 4 3 prs13 2 prs12 1 prs11 0 prs10 count clock specification (x/f xx ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048) (b) capture/compare control register 1 (crc1) 7 0 crc1 6 0 5 0 4 0 3 1 2 0 1 0 0 0 tm1 clearing by match of cr10 & tm1 contents disabled cr11 specified as compare operation tm1 clearing by match of cr11 & tm1 contents enabled figure 9-27 interval timer operation (2) setting procedure interval timer (2) set count value in cr11 cr11 n intc11 interrupt ; set 1 in bit 3 of tmc1 set prm1 set crc1 crc1 08h start count ce1 1 chapter 9 timer/counter 1 275 user s manual u11316ej4v1ud 9.7.3 pulse width measurement operation in pulse width measurement, the high-level or low-level width of external pulses input to the external interrupt request input pin (intp0) is measured. both the high-level and low-level widths of pulses input to the intp0 pin must be at least 3 sampling clocks selected by scs0; if shorter than this, the valid edge will not be detected and a capture operation will not be performed. as shown in figure 9-28, the timer register 1 (tm1) value being counted is fetched into the capture/compare register (cr11) set as a capture register in synchronization with a valid edge (set as both rising and falling edges) in the intp0 pin input, a nd held there. the pulse width is obtained from the product of the difference between the tm1 count value (d n ) fetched into and held in the cr11 on detection of the nth valid edge and the count value (d n - 1 ) fetched and held on detection of valid edge n - 1, and the number of count clocks (x/f xx ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048). the control register settings are shown in figure 9-29, and the setting procedure in figure 9-30. figure 9-28 pulse width measurement timing (when cr11 is used as capture register) intp0 external input signal intp0 interrupt request tm1 count value 0h ffh capture/compare register (cr11) ovf1 d0 d1 count start ce1 1 ffh d2 d3 (d1 to d0) x /f xx (d3 to d2) x /f xx cleared by software d1 d0 d2 d3 (100h to d1 + d2) x /f xx capture capture capture capture remark dn: tm1 count value (n = 0, 1, 2, ...) x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048 chapter 9 timer/counter 1 276 user s manual u11316ej4v1ud figure 9-29 control register settings for pulse width measurement (a) prescaler mode register 1 (prm1) 7 prm1 6 5 4 3 prs13 2 prs12 1 prs11 0 prs10 count clock specification (x/f xx ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048) (b) capture/compare control register 1 (crc1) 7 0 crc1 6 0 5 0 4 0 3 0 2 1 1 0 0 0 tm1 clearing by match of tm1 & cr10 contents disabled cr11 specified as capture operation tm1 clearing upon capture of cr11 in tm1 disabled (c) external interrupt mode register 0 (intm0) 7 intm0 6 5 4 3 1 2 1 1 0 0 both rising & falling edges specified as intp0 input valid edges chapter 9 timer/counter 1 277 user s manual u11316ej4v1ud figure 9-30 pulse width measurement setting procedure pulse width measurement initialize capture value buffer memory x 0 0 intp0 interrupt ; set 1 in bit 3 of tmc1 set prm1 set intm0 set mk0l set crc1 crc1 04h enable interrupts start count ce1 1 ; specify both edges as intp0 input valid edges, release interrupt masking figure 9-31 interrupt request servicing that calculates pulse width intp0 interrupt calculate pulse width y n = cr11 x n store capture value in memory x n + 1 cr11 reti chapter 9 timer/counter 1 278 user s manual u11316ej4v1ud 9.8 cautions (1) while timer/counter 1 is operating (while the ce1 bit of the timer control register 1 (tmc1) is set), malfunctioning may occur if the contents of the following registers are rewritten. this is because it is undefined which takes precedence in a contention, the change in the hardware functions due to rewriting the register, or the change in the status because of the function before rewriting. therefore, be sure to stop the counter operation for the sake of safety before rewriting the contents of the following register s. prescaler mode register 1 (prm1) capture/compare control register 1 (crc1) cmd2 bit of timer control register 1 (tmc1) (2) if the contents of the compare register (cr1n: n = 0 or 1) coincide with those of tm1 when an instruction that stops timer register 1 (tm1) operation is executed, the counting operation of tm1 stops, but an interrupt request is generated. in order not to generate the interrupt when stopping the operation of tm1, mask the interrupt in advance by using the interrupt mask register before stopping tm1. example program that may generate interrupt request program that does not generate interrupt request clr1 ce1 or mk0l, #c0h or mk0l, #c0h clr1 ce1 clr1 cif10 clr1 cif11 interrupt request from timer/counter 1 occurs between these instructions disables interrupt from timer/counter 1 clears interrupt request flag from timer/counter 1 chapter 9 timer/counter 1 279 user s manual u11316ej4v1ud (3) up to 1 count clock is required after an operation to start timer/counter 1 (ce1 1) has been performed before timer/counter 1 actually starts (refer to figure 9-32 ). for example, when using timer/counter 1 as an interval timer, the first interval time is delayed by up to 1 clock. the second and those that follow are at the specified interval. figure 9-32 operation when counting is started count clock tm1 ce1 timing to start actual counting count start command (ce1 1) by software 0 0 123 (4) while an instruction that writes data to the compare register (cr1n: n = 0, 1) is executed, coincidence between cr1n, to which the data is to be written, and timer register 1 (tm1) is not detected. write data to cr1n when timer/counter 1 is executing counting operation in the timing that the contents of tm1 do not coincide with the value of cr1n before and after writing (e.g., immediately after an interrupt request has been generated because tm1 and cr1n have coincided). (5) coincidence between timer register 1 (tm1) and compare register (cr1n: n = 0, 1) is detected only when tm1 is incremented. therefore, the interrupt request is not generated even if the same value as tm1 is written to cr1n. (6) if the value of the timer register is read under the condition indicated by in table 9-6, the read value may be illegal. do not read the timer register under condition . table 9-6 limits of reading timer register ( : can be read, : must not be read) f clk f xx /2 f xx /4 f xx /8 f xx /16 timer count clock f xx /8 ?? f xx /16 ??? f xx /n ??? f xx : oscillation frequency 2. f clk : internal system clock frequency 3. n = 32, 64, 128, 256, 512, 1,024, 2,048 chapter 9 timer/counter 1 280 user s manual u11316ej4v1ud (7) when timer/counter 0 is used as an external event counter, it is not possible to distinguish between the case where there is no valid edge input at all and the case where there is a single valid edge input, using the timer register 0 (tm0) alone (refer to figure 9-33 ), since the contents of tm0 are 0 in both cases. if it is necessary to make this distinction, the intp3 interrupt request flag should be used. to make a distinction, use the interrupt request flag of intp0, as shown in figure 9-34. figure 9-33 example of the case where the external event counter does not distinguish between one valid edge input and no valid edge input intp0 tm1 0 1 2 0 cannot be distinguished count start chapter 9 timer/counter 1 281 user s manual u11316ej4v1ud figure 9-34 to distinguish whether one or no valid edge has been input with external event counter (a) processing on starting counting ; set ce1 to 1 ; clear pif0 to 0 clear intp0 interrupt request flag pif0 0 start count ce1 1 start count end (b) processing on reading count value ; number of input valid edges is set to a register count value read read tm1 contents a tm1 a a + 1 end a = 0? pif0 = 1? ; check tm1 value. if 0, check interrupt request flag. ; check pif0 contents. if 1, valid edge is input. yes no yes no chapter 9 timer/counter 1 282 user s manual u11316ej4v1ud (8) even if an attempt is made to clear the timer register by inputting the capture request signal when the capture function of the timer is used, the timer register momentarily counts up immediately before it is cleared. consequently, if a value greater than the value of the timer register by 1 is set to the compare register when the capture request signal is input, the values of the compare register and timer register coincide, and an unnecessary interrupt will be generated (refer to figure 9-35). therefore, take the following operation into consideration when creating a program. chapter 9 timer/counter 1 283 user s manual u11316ej4v1ud (9) if the count operation of tm1 stops at the timing at which compare register (cr10) and timer register 1 (tm1) match, the cr10/tm1 match interrupt may not be generated after timer/counter 1 is next started. if the tm1 count operation is stopped within 1.5 count clocks after a match between cr10 and tm1, the first match interrupt after timer/counter 1 is next started will not be generated. the second and subsequent interrupts operate normally. note that the timer output is unaffected by this bug. this bug occurs because the timer interrupt controller inadvertently masks interrupts if timer/counter 1 is stopped in the period indicated by the shaded area in the figure below. the interrupt controller is initialized by an overflow of timer/counter 1 or a match between cr11 and tm1. count clocks 1.5 count clocks not generated tm1 m + 1 m m ? 1 1 0 0 m mm nn m ? 1 cr10 cr11 ce1 cr10/tm1 match interrupt remark m < n do not stop timer/counter 1 within 1.5 count clocks after a match between cr10 and tm1. disable all interrupt requests (including macro servicing), read the value of the timer to be stopped, and wait until at least 1.5 count clocks have elapsed after a match between cr10 and tm1 before stopping timer/counter 1. 284 user? manual u11316ej4v1ud chapter 10 timer/counter 2 10.1 functions timer/counter 2 is 16-bit or 8-bit timer/counter, and has the following function which the other three timer/counters do not have: one-shot timer note note the one-shot timer function is a count operation of timer/counter 2 (tm2/tm2w), and is thus different in nature from the one-shot pulse output function of timer/counter 0. in this section, the following four basic functions are described in order: interval timer programmable square-wave output pulse width measurement external event counter (1) interval timer generates internal interrupts at preset intervals. table 10-1 timer/counter 2 intervals minimum interval maximum interval resolution 8/f xx 2 16 8/f xx 8/f xx (0.25 s) (16.40 ms) (0.25 s) 16/f xx 2 16 16/f xx 16/f xx (0.50 s) (32.80 ms) (0.50 s) 32/f xx 2 16 32/f xx 32/f xx (1.60 s) (65.50 ms) (1.00 s) 64/f xx 2 16 64/f xx 64/f xx (2.00 s) (131 ms) (2.00 s) 128/f xx 2 16 128/f xx 128/f xx (4.00 s) (262 ms) (4.00 s) 256/f xx 2 16 256/f xx 256/f xx (8.00 s) (524 ms) (8.00 s) 512/f xx 2 16 512/f xx 512/f xx (16.00 s) (1.05 s) (16.00 s) 1,024/f xx 2 16 1,024/f xx 1,024/f xx (32.00 s) (2.10 s) (32.00 s) 2,048/f xx 2 16 2,048/f xx 2,048/f xx (64.00 s) (4.19 s) (64.00 s) ( ): when f xx = 32 mhz chapter 10 timer/counter 2 285 user? manual u11316ej4v1ud (2) programmable square-wave output outputs square waves independently to the timer output pins (to2 and to3). table 10-2 timer/counter 2 programmable square-wave output setting range minimum pulse width maximum pulse width 8/f xx 2 16 8/f xx (0.25 s) (16.40 ms) 16/f xx 2 16 16/f xx (0.50 s) (32.80 ms) 32/f xx 2 16 32/f xx (1.00 s) (65.50 ms) 64/f xx 2 16 64/f xx (2.00 s) (131 ms) 128/f xx 2 16 128/f xx (4.00 s) (262 ms) 256/f xx 2 16 256/f xx (8.00 s) (524 ms) 512/f xx 2 16 512/f xx (16.00 s) (1.05 s) 1,024/f xx 2 16 1,024/f xx (32.00 s) (2.10 s) 2,048/f xx 2 16 2,048/f xx (64.00 s) (4.19 s) ( ): when f xx = 32 mhz caution the above table is applicable to use of an internal clock. chapter 10 timer/counter 2 286 user? manual u11316ej4v1ud (3) pulse width measurement detects the pulse width of the signal input to an external interrupt request input pins (intp1/intp2). table 10-3 timer/counter 2 pulse width measurement range measurable pulse width note resolution 8/f xx to 2 16 8/f xx 8/f xx (0.25 s) (16.40 ms) (0.25 s) 16/f xx to 2 16 16/f xx 16/f xx (0.50 s) (32.80 ms) (0.50 s) 32/f xx to 2 16 32/f xx 32/f xx (1.00 s) (65.50 ms) (1.00 s) 64/f xx to 2 16 64/f xx 64/f xx (2.00 s) (131 ms) (2.00 s) 128/f xx to 2 16 128/f xx 128/f xx (4.00 s) (262 ms) (4.00 s) 256/f xx to 2 16 256/f xx 256/f xx (8.00 s) (524 ms) (8.00 s) 512/f xx to 2 16 512/f xx 512/f xx (16.00 s) (1.05 s) (16.00 s) 1,024/f xx to 2 16 1,024/f xx 1,024/f xx (32.00 s) (2.10 s) (32.00 s) 2,048/f xx to 2 16 2,048/f xx 2,048/f xx (64.00 s) (4.19 s) (64.00 s) ( ): when f xx = 32 mhz note the minimum pulse width that can be measured differs depending on the selected value of f clk . the minimum pulse width that can be measured is the value of 4/f clk or the value in the above table, whichever greater. (4) external event counter counts the clock pulses input from the external interrupt request input pin (intp2) (ci pin input pulses). the clocks that can be input to timer/counter 2 are shown in table 10-4. table 10-4 clocks enabled to be input to timer/counter 2 when counting one edge when counting both edges maximum frequency f clk /8 (2.00 mhz) f clk /8 (2.00 mhz) minimum pulse width 4/f clk (0.25 s) 4/f clk (0.25 s) (high and low levels) ( ): when f clk = 16 mhz and f xx = 32 mhz chapter 10 timer/counter 2 287 user? manual u11316ej4v1ud 10.2 configuration timer/counter 2 consists of the following registers. timer register (tm2/tm2w) 1 compare register (cr20/cr20w) 1 capture/compare register (cr21/cr21w) 1 capture register (cr22/cr22w) 1 the block diagram of timer/counter 2 is shown in figure 10-1. chapter 10 timer/counter 2 288 user? manual u11316ej4v1ud figure 10-1 timer/counter 2 block diagram internal bus 1/8 8/16 8 external interrupt mode register 0 (intm0) es21 es11 compare register (cr20/cr20w) 16 16 8/16 capture/compare register (cr21/cr21w) 16 8/16 16 16 16 8/16 8 selector f xx /1,024 f xx /512 f xx /256 f xx /128 f xx f xx /64 f xx /32 f xx /16 f xx /8 prescaler mode register 1 (prm1) prs23 prs22 prs21 prs20 capture register (cr22/cr22w) timer register 2 (tm2/tm2w) timer control register 1 (tmc1) ovf2 ce2 1/8 internal bus p22/intp1 edge detection circuit edge detection circuit cmd2 overflow selector 8 8 8 8 intp2 match match match match reset capture/compare control register 2 (crc2) p23/intp2/ci intp1 p36/to2 es20 es10 f xx /2,048 prescaler capture trigger capture trigger mod1 mod0 clr22 clr21 cm21 ent03 alv3 ent02 alv2 timer output control register (toc) output control circuit output control circuit intc20 p37/to3 intc21 bw2 intp2 8 pwm/ppg output control selector selector chapter 10 timer/counter 2 289 user s manual u11316ej4v1ud (1) timer register 2 (tm2/tm2w) tm2/tm2w is a timer register that counts up the count clock specified by the high-order 4 bits of prescaler mode register 1 (prm1). an internal clock or external clock can be selected as the count clock. the count operation can be stopped or enabled by means of timer control register 1 (tmc1). the timer register can select to operate in an 8-bit (tm2) or 16-bit (tm2w) mode. tm2/tm2w can be read only with an 8/16-bit manipulation instruction. when reset is input, tm2/tm2w is cleared to 00h and the count is stopped. caution if the value of the timer register is read under the condition indicated by ?in table 10-5, the read value may be illegal. do not read the timer register under condition ? table 10-5 limits of reading timer register ( : can be read, : must not be read) f clk f xx /2 f xx /4 f xx /8 f xx /16 timer count clock f xx /8 ?? f xx /16 ??? f xx /n ??? remarks 1. f xx : oscillation frequency 2. f clk : internal system clock frequency 3. n = 32, 64, 128, 256, 512, 1,024, 2,048 (2) compare register (cr20/cr20w) cr20/cr20w is an 8/16-bit register that holds the value that determines the interval timer operation cycle. if the contents of the cr20/cr20w register match the contents of tm2/tm2w, an interrupt request (intc20) and a timer output control signal are generated. this compare register operates as cr20 in the 8-bit mode, and cr20w in the 16-bit mode. cr20/cr20w can be read or written to with an 8/16-bit manipulation instruction. the contents of this register are undefined after reset input. (3) capture/compare register (cr21/cr21w) cr21/cr21w is an 8/16-bit register that can be specified as a compare register for detecting a match with the tm2/ tm2w count value or a capture register for capturing the tm2/tm2w count value according to the setting of the capture/ compare control register 2 (crc2). this capture/compare register operates as cr21 in the 8-bit mode, and cr21w in the 16-bit mode. cr21/cr21w can be read or written to with an 8/16-bit manipulation instruction. the contents of this register are undefined after reset input. (a) when specified as compare register cr21/cr21w functions as an 8/16-bit register that holds the value that determines the interval timer operation cycle. an interrupt request (intc21) and a timer output control signal are generated by a match between the contents of the cr21/cr21w register and the contents of tm2/tm2w. also, the count value can be cleared by a match of the contents. chapter 10 timer/counter 2 290 user s manual u11316ej4v1ud (b) when specified as capture register cr21/cr21w functions as an 8/16-bit register that captures the contents of tm2/tm2w in synchronization with the input of a valid edge on the external interrupt input pin (intp2) (capture trigger). the contents of the cr21/cr21w register are retained until the next capture trigger is generated. also, tm2/tm2w can be cleared after a capture operation. (4) capture register (cr22/cr22w) cr22/cr22w is an 8/16-bit register that captures the contents of tm2/tm2w. the capture operation is synchronized with the input of a valid edge to the external interrupt request input pin (intp1) (capture trigger). the contents of the cr22/cr22w register are retained until the next capture trigger is generated. also, tm2/tm2w can be cleared after a capture operation. this capture register operates as cr22 in the 8-bit mode, and cr22w in the 16-bit mode. cr22/cr22w can be read only with an 8/16-bit manipulation instruction. reset input clears this register to 0000h. (5) edge detection circuit the edge detection circuit detects an external input valid edge. this circuit generates an external interrupt request (intp1) and capture trigger by detecting the valid edge of the intp1 pin input specified by the external interrupt mode register 0 (intm0). it also generates a capture trigger, the count clock of an external event, and external interrupt request (intp2) by detecting the valid edge from an external interrupt request input pin (intp2). (6) output control circuit it is possible to invert the timer output when the cr20/cr21 register contents and the contents of tm2 match or the cr20w/cr21w contents and the contents of tm2w match. a square wave can be output from the timer output pins (to2/to3) in accordance with the setting of the high-order 4 bits of the timer output control register (toc). at this time, pwm output or ppg output can be performed according to the specification of the capture/compare control register 2 (crc2). timer output can be disabled/enabled by means of the toc register. when timer output is disabled, a fixed level is output to the to2 and to3 pins (the output level is set by the toc register). (7) prescaler the prescaler generates the count clock from the internal system clock. the clock generated by the prescaler is selected by the selector, and is used as the count clock by the timer register 2 (tm2/tm2w) to perform count operations. (8) selector the selector selects a signal resulting from dividing the internal clock or the edge detected by the edge detection circuit as the count clock of timer register 2 (tm2/tm2w). chapter 10 timer/counter 2 291 user s manual u11316ej4v1ud 10.3 timer/counter 2 control registers (1) timer control register 1 (tmc1) in tmc1 the timer/counter 2, tm2/tm2w, count operation is controlled by the high-order 4 bits (the low-order 4 bits control the count operation of timer/counter 1, tm1/tm1w). tmc1 can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the format of the tmc1 is shown in figure 10-2. reset input clears tmc1 to 00h. figure 10-2 timer control register 1 (tmc1) format 7 ce2 tmc1 6 ovf2 5 cmd2 4 bw2 3 ce1 2 ovf1 1 0 0 bw1 address after reset r/w r/w 00h 0ff5fh bw2 timer/counter 2 bit length specification 8-bit operating mode 16-bit operating mode 1 0 cmd2 tm2/tm2w operating mode specification normal mode one-shot mode 1 0 ovf2 tm2/tm2w overflow flag no overflow overflow note 1 0 ce2 tm2/tm2w count operation control count operation stopped with count cleared count operation enabled 1 0 controls count operation of timer/counter 1 (tm1/tm1w) (see figure 9-2 ). note 8-bit operating mode: count up from ffh to 00h in 16-bit operating mode: count up from ffffh to 0000h remark the ovf2 bit is reset by software only. chapter 10 timer/counter 2 292 user s manual u11316ej4v1ud (2) prescaler mode register 1 (prm1) in prm1 the count clock to timer/counter 2, tm2/tm2w, is specified by the high-order 4 bits (the low-order 4 bits specify the count clock to timer/counter 1, tm1/tm1w). prm1 can be read or written with an 8-bit manipulation instruction. the format of the prm1 is shown in figure 10-3. reset input sets prm1 to 11h. figure 10-3 prescaler mode register 1 (prm1) format 7 prs23 prm1 6 prs22 5 prs21 4 pr20 3 prs13 2 prs12 1 prs11 0 prs10 address after reset r/w r/w (f xx = 32mhz) 11h 0ff5eh prs23 prs22 prs21 prs20 timer/counter 2 (tm2/tm2w) count clock specification count clock [hz] specification setting prohibited f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 f xx /2,048 external clock (ci/intp2) resolution [ s] 0.25 0.50 1.00 2.00 4.00 8.00 16.00 32.00 64.00 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 specifies count clock to timer/counter 1 (tm1/tm1w) (see figure 9-3 ). other than the above setting prohibited remark f xx : x1 input frequency or oscillation frequency chapter 10 timer/counter 2 293 user s manual u11316ej4v1ud (3) capture/compare control register 2 (crc2) the crc2 specifies the enabling condition for a timer register 2 (tm2/tm2w) clear operation by the capture/compare register (cr21/cr21w) or the capture register (cr22/cr22w) and the timer output (to2/to3) mode. crc2 can be read or written with an 8-bit manipulation instruction. the format of the crc2 is shown in figure 10- 4. reset input sets crc2 to 10h. figure 10-4 capture/compare control register 2 (crc2) format 7 mod1 crc2 6 mod0 5 clr22 4 1 3 clr21 2 cm21 1 0 0 0 address after reset r/w r/w 10h 0ff33h mod1 mod0 clr22 clr21 timer output mode specification compare operations capture operations cr21 operation specification tm2 clear operation toggle output toggle output toggle output toggle output toggle output to2 to3 setting prohibited other than the above not cleared pwm output toggle output not cleared pwm output ppg output pwm output toggle output not cleared not cleared pwm output not cleared 0000 cm21 0 00010 toggle output toggle output toggle output 00100 toggle output toggle output 00110 01000 10000 11010 00001 00011 01001 cleared if tm2 and cr21 match cleared if tm2 and cr21 match cleared after tm2 contents are captured in cr22 by intp1 cleared after tm2 contents are captured in cr21 by intp2 cleared by match of tm2 and cr21 or after tm2 contents are captured in cr22 by intp1 remark the register names in the 8-bit operating mode are shown in this figure. in the 16-bit operating mode, the register names tm2, cr20, cr21, and cr22 are tm2w, cr20w, cr21w, and cr22w, respectively. caution even if an attempt is made to clear the timer register by inputting the capture request signal when the capture function of the timer is used, the timer register momentarily counts up immediately before it is cleared. consequently, if a value greater than the value of the timer register by 1 is set to the compare register when the capture request signal is input, the values of the compare register and timer register coincide, and an unnecessary interrupt will be generated (refer to figure 10-5). therefore, take the following operation into consideration when creating a program. chapter 10 timer/counter 2 294 user s manual u11316ej4v1ud chapter 10 timer/counter 2 295 user s manual u11316ej4v1ud (4) timer output control register (toc) toc is an 8-bit register that controls output enabling/disabling of the active level of timer output. the operation of the timer output pins (to2 and to3) by timer/counter 2 is controlled by the high-order 4 bits (the low- order 4 bits control the operation of the timer output pins (to0 and to1) by timer/counter 0). toc can be read or written with an 8-bit manipulation instruction or bit manipulation instruction. the format of the toc is shown in figure 10-6. reset input clears toc to 00h. figure 10-6 timer output control register (toc) format 7 ento3 toc 6 alv3 5 ento2 4 alv2 3 ento1 2 alv1 1 ento0 0 alv0 address after reset r/w r/w 0000h 0ff31h ento2 to2 pin operation specification alv2 output pulse output enabled 1 0 control operation of timer output pins (to0 & to1) by timer/counter 0 (see figure 8-5 ). alv2 to2 pin active level toggle output specification pwm/ppg output specification low level high level high level low level 1 0 ento3 to3 pin operation specification alv3 output pulse output enabled 1 0 alv3 to3 pin active level toggle output specification pwm/ppg output specification low level high level high level low level 1 0 chapter 10 timer/counter 2 296 user s manual u11316ej4v1ud 10.4 timer register 2 (tm2) operation 10.4.1 basic operation 8-bit operating mode/16-bit operating mode control can be performed for timer/counter 2 by means of bit 0 (bw2) of timer control register 2 (tmc2). note in the timer/counter 2 count operation, an up-count is performed using the count clock specified by the high-order 4 bits of prescaler mode register 1 (prm1). count operation enabling/disabling is controlled by bit 3 (ce2) of tmc2 (timer/counter 2 operation control is performed by the high-order 4 bits of the timer control register 1 (tmc1). when the ce2 bit is set (to 1) by software, the contents of tm2 are cleared to 0h on the first count clock, and then the up-count operation is performed. when the ce2 bit is cleared (to 0) by software, tm2 becomes 0h immediately, and capture operations and match signal generation are stopped. if the ce2 bit is set (to 1) again when it is already set (to 1), the tm2 count operation is not affected (see figure 10- 7 (b) ). tm2/tm2w is cleared to 0h when the count clock is input while the value of tm2 is ffh in the 8-bit operating mode or while the value of tm2w is ffffh in the 16-bit operating mode. at this time, ovf2 bit is set and the overflow signal is sent to the output control circuit. ovf2 bit is cleared by software only. the count operation is continued. when reset is input, tm2 is cleared to 0h, and the count operation is stopped. note unless otherwise specified, the functions of timer register 2 in the 8-bit operating mode are described hereafter. in the 16-bit operating mode, tm2, cr20, cr21, and cr22 operate as tm2w, cr20w, cr21w, and cr22w, respectively. chapter 10 timer/counter 2 297 user s manual u11316ej4v1ud figure 10-7 basic operation in 8-bit operating mode (bw2 = 0) (a) count started tm2 ce2 0h 0h 1h 2h 0fh 10h 11h 0h 1h 0h count started ce2 1 count stopped ce2 0 count started ce2 1 count clock (b) when 1 is written to the ce2 bit again after the count starts tm2 ce2 0h 0h 1h 2h 3h 4h 5h 6h count started ce2 1 rewrite ce2 1 count clock (c) operation when tm2 = ffh tm2 ovf2 feh ffh 0h cleared by software ovf2 0 count clock f clk /8 1h chapter 10 timer/counter 2 298 user s manual u11316ej4v1ud figure 10-8 basic operation in 16-bit operating mode (bw2 = 1) (a) count started tm2w ce2 0h 0h 1h 2h ffh 100h 101h 0h 1h 0h count started ce2 1 count started ce2 1 count stopped ce2 0 count clock (b) when 1 is written to the ce2 bit again after the count starts tm2w ce2 0h 0h 1h 2h 3h 4h 5h 6h count started ce2 1 rewrite ce2 1 count clock (c) operation when tm2w = ffffh tm2w ovf2 fffeh ffffh 0h cleared by software ovf2 0 count clock f clk /8 1h chapter 10 timer/counter 2 299 user s manual u11316ej4v1ud 10.4.2 clear operation (1) clear operation after match with compare register and capture operation timer register 2 (tm2) can be cleared automatically after a match with the compare register (cr2n: n = 0, 1) and a capture operation. when a clearance source arises, tm2 is cleared to 0h on the next count clock. therefore, even if a clearance source arises, the value at the point at which the clearance source arose is retained until the next count clock arrives. figure 10-9 tm2 clearance by match with compare register (cr20/cr21) tm2 compare register (cr2n) n cleared here count clock 0 1 n - 1 n tm2 and cr2n match figure 10-10 tm2 clearance after capture operation tm2 intp1 n tm2 is captured in cr22 here cleared here count clock 0 1 2 n - 1 (2) clear operation by ce2 bit of timer control register 2 (tmc2) timer register 2 (tm2) is also cleared when the ce2 bit of the tmc1 is cleared (to 0) by software. the clear operation is performed immediately after clearance (to 0) of the ce2 bit. chapter 10 timer/counter 2 300 user s manual u11316ej4v1ud figure 10-11 clear operation when ce2 bit is cleared (to 0) (a) basic operation tm2 ce2 n count clock n - 1 0 (b) restart before count clock is input after clearance tm2 ce2 n 0 count clock n - 1 0 1 2 if the ce2 bit is set (to 1) before this count clock, this count clock starts counting from 0. (c) restart after count clock is input after clearance tm2 ce2 n 0 count clock n - 1 0 0 1 if the ce2 bit is set (to 1) from this count clock onward, the count starts from 0 on the count clock after the ce2 bit is set (to 1). chapter 10 timer/counter 2 301 user s manual u11316ej4v1ud 10.5 external event counter function timer/counter 2 can count clock pulses input from external interrupt request input pin (intp2/ci). no special selection method is needed for the external event counter operating mode. when the timer register 2 (tm2) count clock is specified as external clock input by the setting of the high-order 4 bits of prescaler mode register 1 (prm1), tm2 operates as an external event counter. the maximum frequency of external clock pulses that can be counted by tm2 as the external event counter is 2.00 mhz (f clk = 16 mhz) irrespective of whether only one edge or both edges are counted on intp2/ci input. the pulse width of intp2/ci input must be at least 4 system clocks (0.25 s: f clk = 16 mhz) for both the high level and low level. if the pulse width is shorter than this, the pulse may not be counted. the timer/counter 2 external event count timing is shown in figure 10-12. figure 10-12 timer/counter 2 external event count timing (1/2) (1) counting one edge (maximum frequency = f clk /8) ici tm2 ci 4/f clk (min.) 4/f clk (min.) 8/f clk (min.) dn + 1 dn dn + 2 dn + 3 3 to 4/f clk remark ici: ci input signal after passing through edge detection circuit chapter 10 timer/counter 2 302 user s manual u11316ej4v1ud figure 10-12 timer/counter 2 external event count timing (2/2) (2) counting both edges (maximum frequency = f clk /8) ici tm2 ci 4/f clk (min.) 4/f clk (min.) 8/f clk (min.) dn + 1 dn dn + 2 dn + 3 dn + 4 dn + 5 3 to 4/f clk remark ici: ci input signal after passing through edge detection circuit the tm2 count operation is controlled by the ce2 bit of the timer control register 1 (tmc1) in the same way as with the basic operation. when the ce2 bit is set (to 1) by software, the contents of tm2 are set to 0h and the up-count operation is started on the initial count clock. when the ce2 bit is cleared (to 0) by software during a tm2 count operation, the contents of tm2 are set to 0h immediately and the stopped state is entered. the tm2 count operation is not affected if the ce2 bit is set (to 1) by software again when it is already set (to 1). caution when timer/counter 2 is used as an external event counter, it is not possible to distinguish between the case where there is no valid edge input at all and the case where there is a single valid edge input using timer register 2 (tm2) alone (see figure 10-13), since the contents of tm2 are 0 in both cases. if it is necessary to make this distinction, the intp2 interrupt request flag should be used (the intp2 pin and ci pin have a dual function, and both functions can be used at the same time). an example is shown in figure 10-14. figure 10-13 example of the case where the external event counter does not distinguish between one valid edge input and no valid edge input tm2 0 intp2/ci 1 2 0 count start no distinction made chapter 10 timer/counter 2 303 user s manual u11316ej4v1ud figure 10-14 methods of enabling the external event counter to distinguish no valid edge input (a) processing when count is started clear intp2 interrupt request flag pif2 0 ; clear pif2 to 0 end start count start count ce2 1 ; set ce2 to 1 (b) processing when count value is read read tm2 contents a tm2 a a + 1 ; check pif2 contents if 1, there is a valid edge ; number of input valid edges is set in a register ; check tm2 value if 0, check interrupt request flag end pif2 = 1 ? yes yes no no count value read a = 0 ? chapter 10 timer/counter 2 304 user s manual u11316ej4v1ud 10.6 one-shot timer function timer/counter 2 has an operating mode in which it stops automatically when a full count value is reached (ffh/ffffh) as a result of counting by timer register 2 (tm2/tm2w). figure 10-15 one-shot timer operation intc21 interrupt request tm2/tm2w count value 0h ffh or ffffh count start ce2 1 cr21/cr21w value ovf2 clear ovf2 0 as shown in figure 10-15, the respective one-shot interrupt is generated when the value (0h to ffh/ffffh) set beforehand in the cr20, cr21/cr21w or cr21w and the timer register 2 (tm2/tm2w) value match. the one-shot timer operating mode is specified by setting (to 1) bit 5 (cmd2) of timer control register 1 (tmc1) by software. the tm2/tm2w count operation is controlled by the ce2 bit of the tmc1 as with the basic operation. when the ce2 bit is set (to 1) by software, the contents of tm2/tm2w are set to 0h and the up-count operation is started on the initial count clock. when the contents of tm2/tm2w reach ffh/ffffh (full count) as a result of the up-count operation, bit 6 (ovf2) of the tmc1 are set (to 1), and tm2/tm2w stops with the count at ffh/ffffh. the one-shot timer operation is started again from the count-stopped state by clearing (to 0) the ovf2 bit by software. when the ovf2 bit is cleared (to 0), the contents of tm2/tm2w become 0h and the up-count operation is restarted on the next count clock. if the ce2 bit is cleared (to 0) by software during a tm2/tm2w count operation, the contents of tm2/tm2w are set to 0h immediately and the stopped state is entered. the tm2/tm2w count operation is not affected if the ce2 bit is set (to 1) by software again when it is already set (to 1). chapter 10 timer/counter 2 305 user s manual u11316ej4v1ud 10.7 compare register, capture/compare register, and capture register operation 10.7.1 compare operations timer/counter 2 performs compare operations in which the value set in the compare register (cr20) and the capture/ compare register (cr21) specified for compare operation is compared with the timer register 2 (tm2) count value. if the count value of tm2 matches the preset value of the cr20, and cr21 when a compare operation is performed, as the result of the count operation, a match signal is sent to the output control circuit, and an interrupt request signal (in tc20 or intc21) is generated at the same time. after a match with the cr20 or cr21 value, the tm2 contents can be cleared, and the timer functions as an interval timer that repeatedly counts up to the value set in the cr20 or cr21. figure 10-16 compare operation in 8-bit operating mode intc20 interrupt request tm2 count value 0h ffh count start ce2 1 cr20 value cr21 value ffh cr20 value cr21 value intc21 interrupt request to2 pin output ento2 = 1 alv2 = 1 ovf2 match match match match to3 pin output ento2 = 1 alv3 = 0 cleared by software inactive level inactive level remark clr21 = 0, clr22 = 0, bw2 = 0 chapter 10 timer/counter 2 306 user s manual u11316ej4v1ud figure 10-17 compare operation in 16-bit operating mode intc20 interrupt request tm2w count value 0h ffffh count start ce2 1 cr20w value cr21w value ffffh cr20w value cr21w value intc21 interrupt request to2 pin output ento2 = 1 alv2 = 1 ovf2 match match match match to3 pin output ento2 = 1 alv3 = 0 cleared by software inactive level inactive level remark clr21 = 0, clr22 = 0, bw2 = 1 chapter 10 timer/counter 2 307 user s manual u11316ej4v1ud figure 10-18 tm2 clearance after match detection intc20 interrupt request tm2 count value 0h ffh count start ce2 1 clr21 0 intc21 interrupt request to2 pin output ento2 1 alv2 1 ovf2 to3 pin output ento3 1 alv3 1 cleared by software cr20 cr21 cr21 cr21 inactive level inactive level count start ce2 1 clr21 1 count disabled ce2 0 clear clear remark clr22 = 0 10.7.2 capture operations timer/counter 2 performs capture operations in which the timer register 2 (tm2) count value is fetched into the capture register in synchronization with an external trigger, and retained there. a valid edge detected from the input of the external interrupt request input pins (intp1/intp2) is used as the external trigger (capture trigger). the count value of tm2 in the process of being counted in synchronization with the capture trigger is fetched into the capture register (cr22) in synchronization with intp1, or into the capture/compare register (cr21) when a capture operation is specified in synchronization with intp2, and is retained there. the contents of cr21 and cr22 are retained until the next capture triggers corresponding to cr21 and cr22 are generated. the capture trigger valid edge is set by means of external interrupt mode register 0 (intm0). if both rising and falling edges are set as capture triggers, the width of pulses input from off-chip can be measured, and if a capture trigger is generated by a single edge, the input pulse cycle can be measured. see figure 21-1 in chapter 21 edge detection function for details of the intm0 format. when cr21 is used as a capture register, tm2 can be cleared as soon as the contents of tm2 have been captured by capture trigger to cr21 or cr22. chapter 10 timer/counter 2 308 user s manual u11316ej4v1ud figure 10-19 capture operation in 8-bit operating mode tm2 count value count starts ce 1 0h intp2 pin input intp2 interrupt request capture register (cr21) intp1 pin input intp1 interrupt request capture register (cr22) ovf2 d0 d3 d6 d1 d2 d4 d5 d7 d0 d1 d2 d3 d4 d6 d7 d5 ffh remark dn: tm2 count value (n = 0, 1, 2, ...) cm21 = 1, clr21 = 0, clr22 = 0, bw2 = 0 chapter 10 timer/counter 2 309 user s manual u11316ej4v1ud figure 10-20 capture operation in 16-bit operating mode tm2w count value count starts ce 1 0h intp2 pin input intp2 interrupt request capture register (cr21w) intp1 pin input intp1 interrupt request capture register (cr22w) ovf2 d0 d3 d6 d1 d2 d4 d5 d7 d0 d1 d2 d3 d4 d6 d7 d5 ffffh remark dn: tm2w count value (n = 0, 1, 2, ...) cm21 = 1, clr21 = 0, clr22 = 0, bw2 = 0 chapter 10 timer/counter 2 310 user s manual u11316ej4v1ud figure 10-21 tm2 clearance after capture operation n3 intp1 pin input intp1 interrupt request tm2 count value 0h capture/compare register (cr22) n2 n1 n4 capture capture capture capture capture n1 n2 n3 n4 n5 remark clr21 = 0, clr22 = 1 caution even if an attempt is made to clear the timer register by inputting the capture request signal when the capture function of the timer is used, the timer register momentarily counts up immediately before it is cleared. consequently, if a value greater than the value of the timer register by 1 is set to the compare register when the capture request signal is input, the values of the compare register and timer register coincide, and an unnecessary interrupt will be generated (refer to figure 10-22). therefore, take the following operation into consideration when creating a program. chapter 10 timer/counter 2 311 user s manual u11316ej4v1ud chapter 10 timer/counter 2 312 user s manual u11316ej4v1ud 10.8 basic operation of output control circuit the output control circuit controls the timer output pins (to2/to3) level by means of match signals from the compare register (cr22). the operation of the output control circuit is determined by the timer output control register (toc) and capture/compare control register 2 (crc2) (see table 10-6 ). when to2/to3 signal is output to a pin, the relevant pin must be in control mode in the port 3 mode register (pmc3). chapter 10 timer/counter 2 313 user s manual u11316ej4v1ud table 10-6 timer output (to2/to3) operations toc crc2 tmc1 to3 to2 ento3 alv3 ento2 alv2 mod1, mod1, clr22 clr21 cmd2 0 0/1 0 0/1 high/low level fixed high/low level fixed 0 0/1 1 0/1 0 0 high/low level fixed toggle output (active-low/high) 1 0/1 0 0/1 0 0 toggle output (active-low/high) high/low level fixed 1 0/1 1 0/1 0 0 toggle output (active-low/high) toggle output (active-low/high) 00/110/101000 high/low level fixed pwm output (active-high/low) 10/100/101000 toggle output (active-low/high) high/low level fixed 10/110/101000 toggle output (active-low/high) pwm output (active-high/low) 00/110/110000 high/low level fixed pwm output (active-high/low) 10/100/110000 pwm output (active-high/low) high/low level fixed 10/110/110000 pwm output (active-high/low) pwm output (active-high/low) 00/110/111010 high/low level fixed ppg output (active-high/low) 10/100/111010 toggle output (active-low/high) high/low level fixed 10/110/111010 toggle output (active-low/high) ppg output (active-high/low) note clr22 is normally set to 0 in this case. remarks 1. 0/1 in the alvn (n = 2, 3) columns correspond to the items on the left and right of the slash ( / ) in the ton (n = 2, 3) columns respectively. 2. indicates 0 or 1. 3. combinations not shown in this table are prohibited to use in that combination. chapter 10 timer/counter 2 314 user s manual u11316ej4v1ud 10.8.1 basic operation setting (to 1) the enton (n = 2, 3) bit of the timer output control register (toc) enables timer output (ton: n = 2, 3) to be varied at a timing in accordance with the settings of mod0, mod1, and clr21 bits of capture/compare control register 2 (crc2). clearing (to 0) enton sets the ton to a fixed level. the fixed level is determined by the alvn (n = 2/3) bit of the toc. the level is high when alvn is 0, and low when 1. 10.8.2 toggle output toggle output is an operating mode in which the output level is inverted each time the compare register (cr20/cr21) value coincides with the timer register 2 (tm2) value. the output level of timer output (to2) is inverted by a match between cr20 and tm2, and the output level of timer output (to3) is inverted by a match between cr21 and tm2. when timer/counter 2 is stopped by clearing (to 0) the ce2 bit of the timer control register 1 (tmc1), the inactive level (alvn: n = 0, 1) is output. figure 10-23 toggle output operation ento0 tm2 count value 0h ffh instruction execution cr20 value cr21 value ffh cr20 value cr21 value ffh cr20 value cr21 value ffh cr20 value cr21 value ffh to2 output (alv2 = 1) ento3 to3 output (alv3 = 0) instruction execution instruction execution instruction execution chapter 10 timer/counter 2 315 user s manual u11316ej4v1ud table 10-7 to2/to3 toggle output (f xx = 32 mhz) count clock minimum pulse width maximum pulse width f xx /8 8/f xx 2 16 8/f xx (0.25 s) (16.40 ms) f xx /16 16/f xx 2 16 16/f xx (0.50 s) (32.80 ms) f xx /32 32/f xx 2 16 32/f xx (1.00 s) (65.50 ms) f xx /64 64/f xx 2 16 64/f xx (2.00 s) (131 ms) f xx /128 128/f xx 2 16 128/f xx (4.00 s) (262 ms) f xx /256 256/f xx 2 16 256/f xx (8.00 s) (524 ms) f xx /512 512/f xx 2 16 512/f xx (16.00 s) (1.05 s) f xx /1024 1,024/f xx 2 16 1,024/f xx (32.00 s) (2.10 s) f xx /2048 2,048/f xx 2 16 2,048/f xx (64.00 s) (4.19 s) chapter 10 timer/counter 2 316 user s manual u11316ej4v1ud 10.8.3 pwm output (1) basic operation of pwm output in this mode, a pwm signal with the period in which timer register 2 (tm2) reaches a full count used as one cycle is output. the timer output (to2) pulse width is determined by the value of compare register (cr20), and the timer output (to3) pulse width is determined by the value of compare register (cr21). when this function is used, the clr21 bit and clr22 bit of capture/compare control register 2 (crc2) and the cmd2 bit of timer control register 1 (tmc1) must be set to 0. the pulse cycle and pulse width are as shown below. (a) bw2 = 0 pwm cycle = 256 x/f xx pwm pulse width = cr2n x/f xx note ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048 note 0 cannot be set in the cr2n. duty = pwm pulse width pwm = cr n 2 256 (b) bw2 = 1 pwm cycle = 65,536 x/f xx pwm pulse width = cr2n x/f xx note ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048 note 0 cannot be set in the cr2n. duty = pwm pulse width pwm cycle = cr2n 65,536 chapter 10 timer/counter 2 317 user s manual u11316ej4v1ud figure 10-24 pwm pulse output (bw2 = 0) cr20 interrupt tm2 count value 0h ffh count start cr20 ffh ffh pulse width pulse cycle pulse width to2 cr20 pulse cycle remark alv2 = 0 table 10-8 to2/to3 pwm cycle (f xx = 32 mhz, bw2 = 0) count clock minimum pulse width [ s] pwm cycle [ms] pwm frequency [hz] f xx /8 0.25 0.06 15,625 f xx /16 0.50 0.13 7,813 f xx /32 1.00 0.26 3,906 f xx /64 2.00 0.51 1,953 f xx /128 4.00 1.02 977 f xx /256 8.00 2.05 488 f xx /512 16.00 4.10 244 f xx /1,024 32.00 8.19 122 f xx /2,048 64.00 16.40 61 chapter 10 timer/counter 2 318 user s manual u11316ej4v1ud figure 10-25 pwm pulse output (bw2 = 1) cr20 interrupt tm2 count value 0h ffffh count start cr20 ffffh ffffh pulse width pulse cycle to2 cr20 pulse width pulse cycle remark alv2 = 0 table 10-9 to2/to3 pwm cycle (f xx = 32 mhz, bw2 = 1) count clock minimum pulse width [ s] pwm cycle [s] pwm frequency [hz] f xx /8 0.25 0.02 61.0 f xx /16 0.50 0.03 30.5 f xx /32 1.00 0.07 15.3 f xx /64 2.00 0.13 7.6 f xx /128 4.00 0.26 3.8 f xx /256 8.00 0.52 1.9 f xx /512 16.00 1.05 1.0 f xx /1,024 32.00 2.10 0.5 f xx /2,048 64.00 4.19 0.2 chapter 10 timer/counter 2 319 user s manual u11316ej4v1ud figure 10-26 shows an example of 2-channel pwm output, and figure 10-27 shows the case where ffffh is set in the cr20w. figure 10-26 example of pwm output using tm2w tm2w count value 0h cr20w ffffh intc20 cr21w cr20w ffffh cr21w cr20w ffffh intc21 to2 to3 remark alv2 = 0, alv3 = 0 figure 10-27 example of pwm output when cr20w = ffffh tm2w count value ffffh intc20 0 1 2 fffeh ffffh 0 1 2 fffeh count clock cycle t ffffh 0 pulse width t duty = 100 = 99.6 (%) . . 255 256 pulse cycle = 256t ovf2 to2 remarks 1. alv2 = 0 2. t = x/f xx (x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048) chapter 10 timer/counter 2 320 user s manual u11316ej4v1ud (2) rewriting compare registers (cr20, cr21) the output level of the timer output (ton + 2: n + 2 = 2, 3) is not inverted even if the cr2n (n = 0, 1) value matches the timer register 2 (tm2) value more than once during one pwm output cycle. figure 10-28 example of compare register (cr20w) rewrite cr20w to2 tm2w count value 0h t1 t1 t2 t1 t2 ffffh cr20w and tm2w values match, but to2 does not change here. cr20w rewrite ffffh t2 remark alv2 = 1 chapter 10 timer/counter 2 321 user s manual u11316ej4v1ud if a value smaller than that of the tm2 is set as the cr2n value, a 100% duty pwm signal will be output. cr2n rewriting should be performed by the interrupt due to a match between tm2 and the cr2n on which the rewrite is performed. figure 10-29 example of 100% duty with pwm output cr20 to2 tm2 count value 0h n1 n2 n3 n1 when value n2 which is smaller than the tm2 value n3 is written to cr20 here, the duty of this period will be 100%. ffh ffh ffh ffh n2 n2 n2 n1 remark alv2 = 0 chapter 10 timer/counter 2 322 user s manual u11316ej4v1ud (3) stopping pwm output if timer/counter 2 is stopped by clearing (to 0) the ce2 bit of the timer control register 1 (tmc1) during pwm signal output, the active level is output. figure 10-30 when timer/counter 2 is stopped during pwm signal output to2 tm2w count value 0h cr20w cr20w ffffh ffffh remark alv2 = 1 caution the output level of the ton (n = 2/3) pin when timer output is disabled (enton = 0: n = 2/3) is the inverse of the value set in alvn (n = 2/3) bits. caution is therefore required as the active level is output when timer output is disabled when the pwm output function has been selected. chapter 10 timer/counter 2 323 user s manual u11316ej4v1ud 10.8.4 ppg output (1) basic operation of ppg output this function outputs a square-wave with the time determined by compare register cr21 value as one cycle, and the time determined by compare register cr20 value as the pulse width. the pwm output pwm cycle is made variable. this signal can only be output from timer output (to2). when this function is used, it is necessary to set the clr21 bit of capture/compare control register 2 (crc2) to 1 and the clr22 bit to 0, and to set the cmd2 bit of timer control register 1 (tmc1) to 0. the pulse cycle and pulse width are as shown below. ppg cycle = (cr21 + 1) x/f xx ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048 ppg pulse width = cr20 x/f xx where 1 cr20 cr21 note duty = = cr cr 20 21 1 + neither the cr20 nor the cr21 can be cleared to 0 . figure 10-31 shows an example of ppg output using timer register 2 (tm2), figure 10-32 shows an example of the case where cr20 = cr21. ppg pulse width ppg cycle chapter 10 timer/counter 2 324 user s manual u11316ej4v1ud figure 10-31 example of ppg output using tm2 intc21 tm2 count value 0h cr20 pulse cycle cr20 cr20 cr21 cr21 cr21 intc20 to2 (ppg output) to3 (timer output) pulse width count start remark alv2 = 0, alv3 = 0 table 10-10 to2 ppg output (f xx = 32 mhz) count clock minimum pulse width ppg cycle ppg frequency f xx /8 0.25 s 0.50 s to 16.40 ms 2,000 khz to 61.0 hz f xx /16 0.50 s 1.00 s to 32.80 ms 1,000 khz to 30.5 hz f xx /32 1.00 s 2.00 s to 65.50 ms 500 khz to 15.3 hz f xx /64 2.00 s 4.00 s to 131 ms 250 khz to 7.6 hz f xx /128 4.00 s 8.00 s to 262 ms 125 khz to 3.8 hz f xx /256 8.00 s 16.00 s to 524 ms 62.5 khz to 1.9 hz f xx /512 16.00 s 32.00 s to 1.05 s 31.3 khz to 1.0 hz f xx /1,024 32.00 s 64.00 s to 2.10 s 15.6 khz to 0.5 hz f xx /2,048 64.00 s 128.00 s to 4.19 s 7.8 khz to 0.2 hz chapter 10 timer/counter 2 325 user s manual u11316ej4v1ud figure 10-32 example of ppg output when cr20 = cr21 tm2 count value n intc20 0 1 2 n-1 n 0 1 2 n - 1 count cycle t n 0 pulse width = nt pulse cycle = (n + 1)t intc21 to2 remark alv2 = 0 t = x/f xx (x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048) chapter 10 timer/counter 2 326 user s manual u11316ej4v1ud (2) rewriting compare register (cr20) the output level of the timer output (to2) is not changed even if the cr20 value matches the timer register 2 (tm2) value more than once during one ppg output cycle. figure 10-33 example of compare register rewrite cr20 to2 tm2 count value 0h t1 t2 t1 t2 t1 t2 cr20 and tm2 values match, but to2 does not change here. cr20 rewrite cr21 cr21 t1 cr21 cr21 remark alv2 = 1 chapter 10 timer/counter 2 327 user s manual u11316ej4v1ud if a value equal to or less than the tm2 value is written to cr20 before the cr20 and tm2 match, the duty of that ppg cycle will be 100%. cr20 rewriting should be performed by the interrupt due to a match between tm2 and cr20. figure 10-34 example of 100% duty with ppg output cr20 to2 tm2 count value 0h n1 n2 n3 n1 when value n2 which is smaller than the tm2 value n3 is written to cr20 here, the duty of this period will be 100%. cr21 cr21 cr21 cr21 n2 n2 n2 n1 remark alv2 = 0 caution if the ppg cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of cr20 cannot be rewritten by interrupt processing that is performed on match between tm2 and cr20. use another method (for example, to poll the interrupt request flags by software with all the interrupts masked). chapter 10 timer/counter 2 328 user s manual u11316ej4v1ud (3) rewriting compare register (cr21) if the current value of the cr21 is changed to a smaller value, and the cr21 value is made smaller than the register 2 (tm2) value, the ppg cycle at that time will be extended to the time equivalent to a full-count by tm2. if cr21 is rewritten after the compare register (cr20) and tm2 match, the output level at this time will be the inactive level until tm2 overflows and becomes 0, and will then return to normal ppg output. if cr21 is rewritten before cr20 and tm2 match, the active level will be output until cr20 and tm2 match. if cr20 and tm2 match before tm2 overflows and becomes 0, the inactive level is output at that point. when tm2 overflows and becomes 0, the active level will be output, and normal ppg output will be restored. cr21 rewriting should be performed by the interrupt due to a match between tm2 and cr21, etc. figure 10-35 example of extended ppg output cycle cr20 to2 tm2 count value 0h n3 n4 n2 to2 becomes inactive level when cr20 and tm2 match, otherwise it remains at the active level. full count value n4 n2 n3 n1 n2 cr21 n5 n3 n1 n1 n1 when value n2 smaller than the tm2 value n5 is written to cr21 here, the ppg cycle is extended. remark alv2 = 1 caution if the ppg cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of cr2n cannot be rewritten by interrupt processing that is performed on match between timer register 2 (tm2) and compare register (cr2n: n = 0, 1). use another method (for example, to poll the interrupt request flags by software with all the interrupts masked). chapter 10 timer/counter 2 329 user s manual u11316ej4v1ud (4) stopping ppg output if timer/counter 2 is stopped by clearing (to 0) the ce2 bit of the timer control register 1 (tmc1) during ppg signal output, the active level is output irrespective of the output level at the time timer/counter 2 was stopped. figure 10-36 when timer/counter 2 is stopped during ppg signal output to2 tm2 count value 0h cr20 cr21 cr21 cr20 caution the output level of the ton (n = 2/3) pin when timer output is disabled (enton = 0: n = 2/3) is the inverse value of the value set in alvn (n = 2/3) bits. caution is therefore required as the active level is output when timer output is disabled when the ppg output function has been selected. chapter 10 timer/counter 2 330 user s manual u11316ej4v1ud 10.9 examples of use 10.9.1 operation as interval timer (1) when timer register 2 (tm2) is made free-running and a fixed value is added to the compare register (cr2n: n = 0, 1) in the interrupt service routine, tm2 operates as an interval timer with the added fixed value as the cycle (see figure 10-37 ). the control register settings are shown in figure 10-38, the setting procedure in figure 10-39, and the processing in the interrupt service routine in figure 10-40. figure 10-37 interval timer operation (1) timing mod (2n) intc20 interrupt request tm2 count value 0h ffh ffh compare register (cr20) n timer start mod (3n) mod (4n) n mod (2n) mod (3n) interval interval interval rewritten by interrupt program rewritten by interrupt program rewritten by interrupt program remark interval = n x/f xx 1 n ffh, x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048 chapter 10 timer/counter 2 331 user s manual u11316ej4v1ud figure 10-38 control register settings for interval timer operation (1) (a) prescaler mode register 1 (prm1) 7 prs23 prm1 6 prs22 5 prs21 4 prs20 3 0 2 1 0 count clock specification (x/f xx ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048 or external clock) (b) capture/compare control register 2 (crc2) 7 0 crc2 6 0 5 0 4 1 3 0 2 0 1 0 0 0 tm2 clearing disabled to2 & to3 both toggle outputs (c) timer control register 1 (tmc1) 7 1 tmc1 6 0 5 0 4 0 3 2 1 00 0 normal mode overflow flag count operation enabled chapter 10 timer/counter 2 332 user s manual u11316ej4v1ud figure 10-39 interval timer operation (1) setting procedure interval timer (1) intc20 interrupt ; set 1 in bit 7 of tmc1 set normal mode (cmd2 = 0) set prm1 set count value in cr20 cr20 n set crc2 crc2 10h set tmc1 ce2 1 cmd2 0 figure 10-40 interval timer operation (1) interrupt request servicing intc20 interrupt calculate timer value that will generate next interrupt cr20 cr20 + n other interrupt service program reti chapter 10 timer/counter 2 333 user s manual u11316ej4v1ud 10.9.2 operation as interval timer (2) tm2 operates as an interval timer that generates interrupts repeatedly with the preset count time as the interval (see figure 10-41 ). the control register settings are shown in figure 10-42, and the setting procedure in figure 10-43. figure 10-41 interval timer operation (2) timing compare register (cr21) intc21 interrupt request tm2 count value 0h n n n count start clear clear interval interrupt acknowledged interrupt acknowledged interval remark interval = (n + 1) x/f xx 0 n ffh, x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048 chapter 10 timer/counter 2 334 user s manual u11316ej4v1ud figure 10-42 control register settings for interval timer operation (2) (a) prescaler mode register 1 (prm1) 7 prs23 prm1 6 prs22 5 prs21 4 prs20 3 0 2 1 0 count clock specification (x/f xx ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048 or external clock) (b) capture/compare control register 2 (crc2) 7 0 crc2 6 0 5 0 4 1 3 1 2 0 1 0 0 0 tm2 clearing by match of cr21 & tm2 contents enabled tm2 clearing by capture operation disabled to2 & to3 both toggle outputs (c) timer control register 1 (tmc1) 7 1 tmc1 6 0 5 0 4 0 3 2 1 00 0 normal mode overflow flag count operation enabled chapter 10 timer/counter 2 335 user s manual u11316ej4v1ud figure 10-43 interval timer operation (2) setting procedure interval timer set count value in cr21 cr21 n intc21 interrupt ; set 1 in bit 7 of tmc1 set normal mode (cmd2 = 0) set prm1 set crc2 crc2 18h set tmc1 ce2 1 cmd2 0 chapter 10 timer/counter 2 336 user s manual u11316ej4v1ud 10.9.3 pulse width measurement operation in pulse width measurement, the high-level or low-level width of external pulses input to the external interrupt request input pin (intp1) pin are measured. both the high-level and low-level widths of pulses input to the intp1 pin must be at least 3 system clocks (0.19 s: f clk = 16 mhz); if shorter than this, the valid edge will not be detected and a capture operation will not be performed. as shown in figure 10-44, the timer register 2 (tm2) value being counted is fetched into the capture register (cr22) in synchronization with a valid edge (specified as both rising and falling edges) in the intp1 pin input, and held there. the pulse width is obtained from the product of the difference value between the tm2 count value (d n ) fetched into and held in the cr22 on detection of the nth valid edge and the count value (d n - 1 ) fetched and held on detection of n - 1th valid edge, and the number of n - 1th count clocks (x/f xx ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048). the control register settings are shown in figure 10-45, and the setting procedure in figure 10-46. figure 10-44 pulse width measurement timing intp1 external input signal intp1 interrupt request tm2 count value 0h ffh ffh capture register (cr22) ovf2 d0 d1 count start d2 d3 capture (d1 to d0) x/f xx (100h to d1 + d2) x/f xx (d3 to d2) x/f xx cleared by software d1 d0 d2 d3 capture capture capture remark dn: tm2 count value (n = 0, 1, 2, ...) x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048 chapter 10 timer/counter 2 337 user s manual u11316ej4v1ud figure 10-45 control register settings for pulse width measurement (a) prescaler mode register 1 (prm1) 7 prs23 prm1 6 prs22 5 prs21 4 prs20 3 0 2 1 0 count clock specification (x/f xx ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048 or external clock) (b) capture/compare control register 2 (crc2) 7 0 crc2 6 0 5 0 4 1 3 0 2 0 1 0 0 0 tm2 clearing disabled (c) timer control register 1 (tmc1) 7 1 tmc1 6 0 5 0 4 0 3 2 1 00 0 normal mode overflow flag count operation enabled (d) external interrupt mode register 0 (intm0) 7 intm0 6 5 1 4 1 3 2 1 0 0 both rising and falling edges specified as intp1 input valid edges chapter 10 timer/counter 2 338 user s manual u11316ej4v1ud figure 10-46 pulse width measurement setting procedure enable interrupts pulse width measurement ; specify both edges as intp1 input valid edges, release interrupt masking set crc2 crc2 10h set tmc1 initialize capture value buffer memory x0 0 ; set 1 in bit 7 of tmc1 set normal mode (cmd2 = 0) intp1 interrupt set intm0 set mk0l ce2 1 cmd2 0 figure 10-47 interrupt request servicing that calculates pulse width intp1 interrupt store capture value in memory x n + 1 cr22 calculate pulse width yn = x n + 1 xn reti chapter 10 timer/counter 2 339 user s manual u11316ej4v1ud 10.9.4 operation as pwm output in pwm output, pulses with the duty ratio determined by the value set in the compare register (cr2n: n = 0, 1) are output (see figure 10-48). this pwm output duty ratio can be varied in the range 1/256 to 255/256 in 1/256 units. the control register settings are shown in figure 10-49, the setting procedure in figure 10-50, and the procedure for varying the duty in figure 10-51. figure 10-48 example of timer/counter 2 pwm signal output ffh or ffffh ffh or ffffh ffh or ffffh tm2 count value 0h to3 (when active-high) timer start chapter 10 timer/counter 2 340 user s manual u11316ej4v1ud figure 10-49 control register settings for pwm output operation (a) timer control register 1 (tmc1) 7 1 tmc1 6 0 5 0 4 0 3 2 1 00 0 normal mode overflow flag tm2 count enabled (b) prescaler mode register 1 (prm1) 7 prs23 prm1 6 prs22 5 prs21 4 prs20 3 2 1 0 count clock specification (x/f xx ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048) (c) capture/compare control register 2 (crc2) 7 1 crc2 6 0 5 0 4 1 3 0 2 0 1 0 0 0 tm2 clearing disabled to2 & to3 both pwm outputs (d) timer output control register (toc) 7 1 toc 6 0 5 4 3 2 1 0 to3 = active-high pmw signal output to3 pmw output enabled (e) port 3 mode control register (pmc3) 7 1 pmc3 6 5 4 3 2 1 0 p37 pin set as to3 output chapter 10 timer/counter 2 341 user? manual u11316ej4v1ud figure 10-50 pwm output setting procedure pwm output set crc2 crc2 90h set toc set p37 pin to control mode pmc3.7 1 start count ce2 1 ; set bit 7 of tmc1 set count clock in prm1 set initial value in cr21 chapter 10 timer/counter 2 342 user s manual u11316ej4v1ud figure 10-51 changing pwm output duty duty change preprocessing clear intc21 interrupt request flag cif21 0 enable intc21 interrupts cmk21 0 ; clear bit 7 of cic21 ; clear bit 1 of mk0h intc21 interrupt duty change processing set duty value in cr21 disable intc21 interrupts cmk21 1 ; set bit 1 of mk0h reti chapter 10 timer/counter 2 343 user s manual u11316ej4v1ud 10.9.5 operation as ppg output in ppg output, pulses with the cycle and duty ratio determined by the value set in the compare register (cr2n: n = 0, 1) are output (see figure 10-52 ). the control register settings are shown in figure 10-53, the setting procedure in figure 10-54, and the procedure for varying the duty in figure 10-55. figure 10-52 example of timer/counter 2 ppg signal output cr21 cr20 cr21 cr20 cr21 cr20 tm2 count value 0h to2 (when active-high) timer start chapter 10 timer/counter 2 344 user s manual u11316ej4v1ud figure 10-53 control register settings for ppg output operation (a) timer control register 1 (tmc1) 7 1 tmc1 6 0 5 0 4 0 3 2 1 00 0 normal mode overflow flag tm2 count enabled (b) prescaler mode register 1 (prm1) 7 prs23 prm1 6 prs22 5 prs21 4 prs20 3 2 1 0 count clock specification (x/f xx ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048) (c) capture/compare control register 2 (crc2) 7 1 crc2 6 1 5 0 4 1 3 1 2 0 1 0 0 0 cleared by match of tm2 & cr21 clearing when tm2 is captured in cr22 disabled to2 = ppg output (d) timer output control register (toc) 7 toc 6 5 1 4 0 3 2 1 0 to2 = active-high ppg signal output to2 ppg output enabled (e) port 3 mode control register (pmc3) 7 pmc3 6 1 5 4 3 2 1 0 p36 pin set as to2 output chapter 10 timer/counter 2 345 user s manual u11316ej4v1ud figure 10-54 ppg output setting procedure ppg output set crc2 crc2 d8h set p36 pin to control mode pmc3.6 1 start count ce2 1 set toc ; set bit 7 of tmc1 set count clock in prm1 set cycle in cr21 set duty in cr21 chapter 10 timer/counter 2 346 user s manual u11316ej4v1ud figure 10-55 changing ppg output duty duty change preprocessing clear intc20 interrupt request flag cif20 0 ; clear bit 7 of cic20 enable intc20 interrupts cmk20 0 ; clear bit 0 of mk0h intc20 interrupt duty change processing set duty value in cr20 disable intc20 interrupts cmk20 1 ; set bit 0 of mk0h reti chapter 10 timer/counter 2 347 user s manual u11316ej4v1ud 10.9.6 operation as external event counter an external event counter counts clock pulses (ci pin input pulses) input from off-chip. as shown in figure 10-56, the value of timer register 2 (tm2) is incremented in synchronization with a ci pin input valid edge (specified as rising edge only). figure 10-56 external event counter operation (single edge) ci pin input tm2 n + 1 n + 2 n remark the tm2 value is one less than the number of input clock pulses. the control register settings when tm2 operates as an external event counter are shown in figure 10-57, and the setting procedure in figure 10-58. chapter 10 timer/counter 2 348 user s manual u11316ej4v1ud figure 10-57 control register settings for external event counter operation (a) prescaler mode register 1 (prm1) 7 1 prm1 6 1 5 1 4 1 3 0 2 1 0 external clock input (c1) specified (b) external interrupt mode register 0 (intm0) 7 0 intm0 6 1 5 4 3 2 1 0 rising edge specified as ci input valid edge (c) timer control register 1 (tmc1) 7 1 tmc1 6 0 5 0 4 0 3 2 1 00 0 normal mode overflow flag count operation enabled figure 10-58 external event counter operation setting procedure event counter ; set 1 in bit 7 of tmc1 set prm1 prm1 0f h start count ce2 1 specify ci pin input valid edge chapter 10 timer/counter 2 349 user s manual u11316ej4v1ud 10.9.7 operation as one-shot timer after timer register 2 (tm2) is started, it operates as a one-shot pulse that generates a single interrupt after the preset count time (see figure 10-59 ). the second and subsequent one-shot timer operations can be started by clearing the ovf2 bit of timer control register 1 (tmc1). the control register settings are shown in figure 10-60, the setting procedure in figure 10-61, and the procedure for starting the one-shot timer from the second time onward in figure 10-62. figure 10-59 one-shot timer operation ffh or ffffh cr21 value count start ce2 1 clear ovf2 0 tm2 count value 0h intc21 ovf2 chapter 10 timer/counter 2 350 user s manual u11316ej4v1ud figure 10-60 control register settings for one-shot timer operation (a) timer control register 1 (tmc1) 7 ce2 tmc1 6 ovf2 5 1 4 0 3 2 1 0 one-shot timer mode (b) prescaler mode register 1 (prm1) 7 prs23 prm1 6 prs22 5 prs21 4 prs20 3 0 2 1 0 count clock specification (x/f xx ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048 or external clock) (c) capture/compare control register 2 (crc2) 7 0 crc2 6 0 5 0 4 1 3 0 2 0 1 0 0 0 tm2 clearing disabled chapter 10 timer/counter 2 351 user s manual u11316ej4v1ud figure 10-61 one-shot timer operation setting procedure one-shot timer set one-shot timer mode cmd2 1 ; set 1 in bit 7 of tmc1 set prm1 set count value in cr21 cr21 n set crc2 crc2 10h start count ce2 1 intc21 interrupt ; set 1 in bit 5 of tmc1 figure 10-62 one-shot timer operation start procedure from second time onward one-shot timer restart set count value in cr21 cr21 n restart count ovf2 0 intc21 interrupt chapter 10 timer/counter 2 352 user s manual u11316ej4v1ud 10.10 cautions (1) while timer/counter 2 is operating (while the ce2 bit of the timer control register 1 (tmc1) is set), malfunctioning may occur if the contents of the following registers are rewritten. this is because it is undefined which takes precedence, the change in the hardware functions due to rewriting the register, or the change in the status because of the function before rewriting. therefore, be sure to stop the counter operation for the sake of safety before rewriting the contents of the following registers. prescaler mode register 1 (prm1) capture/compare control register 2 (crc2) timer output control register (toc) cmd2 bit of timer control register 1 (tmc) (2) if the contents of the compare register (cr2n: n = 0, 1) match with those of tm2 when an instruction that stops timer register 2 (tm2) operation is executed, the counting operation of tm2 stops, but an interrupt request is generated. in order not to generate the interrupt when stopping the operation of tm2, mask the interrupt in advance by using the interrupt mask register before stopping tm2. example program that may generate interrupt request program that does not generate interrupt request clr1 ce2 or mk0h, #03h or mk0h, #03h clr1 ce2 clr1 cif20 clr1 cif21 disables interrupt from timer/ counter 2 clears interrupt request flag for timer/ counter 2 interrupt request from timer/counter 2 occurs between these instructions chapter 10 timer/counter 2 353 user s manual u11316ej4v1ud (3) up to 1 count clock is required after an operation to start timer/counter 2 (ce2 1) has been performed before timer/ counter 2 actually starts (refer to figure 10-63 ). for example, when using timer/counter 2 as an interval timer, the first interval time is delayed by up to 1 clock. the second and those that follow are at the specified interval. figure 10-63 operation when counting is started count clock tm2 ce2 timing to start actual counting count start command (ce2 1) by software 0 0 123 (4) while an instruction that writes data to the compare register (cr2n: n = 0 or 1) is executed, coincidence between cr2n, to which the data is to be written, and timer register 2 (tm2) is not detected. for example, if the contents of cr2n do not change before and after the writing, the interrupt request is not generated even if the value of tm2 coincides with the value of cr2n, nor does the timer output (ton + 2: n + 2 = 2, 3) change. write data to cr2n when timer/counter 2 is executing counting operation in the manner that the contents of tm2 do not match the value of cr2n before and after writing (e.g., immediately after an interrupt request has been generated because tm2 and cr2n have matched). (5) match between timer register 2 (tm2) and compare register (cr2n: n = 0, 1) is detected only when tm2 is incremented. therefore, the interrupt request is not generated and timer output (ton + 2: n + 2 = 2, 3) does not change even if the same value as tm2 is written to cr2n. chapter 10 timer/counter 2 354 user s manual u11316ej4v1ud (6) during ppg output, if the ppg cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of the compare register (cr2n: n = 0, 1) cannot be rewritten by interrupt processing that is performed on match between timer register (tm2) and compare register (cr2n). use another method (for example, to poll the interrupt request flags by software with all the interrupts masked). (7) the output level of the ton (n = 2, 3) when the timer output is disabled (enton = 0: n = 2, 3) is the reverse value of the value set to the alvn (n = 2, 3) bit. note, therefore, that an active level is output when the timer output is disabled with the pwm output function or ppg output function selected. (8) if the value of the timer register is read under the condition indicated by in table 10-11, the read value may be illegal. do not read the timer register under condition . table 10-11 limits of reading timer register ( : can be read, : must not be read) f clk f xx /2 f xx /4 f xx /8 f xx /16 timer count clock f xx /8 ?? f xx /16 ??? f xx /n ??? f xx : oscillation frequency 2. f clk : internal system clock frequency 3. n = 32, 64, 128, 256, 512, 1,024, 2,048 (9) when using timer/counter 2 as an external event counter, the status where no valid edge is input cannot be distinguished from the status where only one valid edge has been input, by using timer register 2 (tm2) alone (refer to figure 10-64 ), because the contents of tm2 are 0 in both the cases. to make a distinction, use the interrupt request flag of intp2, as shown in figure 10-65 (the intp2 pin is multiplexed with the ci pin and both the functions can be used at the same time). figure 10-64 example where whether one or no valid edge has been input cannot be distinguished with external event counter ci tm0 0 1 2 0 cannot be distinguished count start chapter 10 timer/counter 2 355 user s manual u11316ej4v1ud figure 10-65 to distinguish whether one or no valid edge has been input with external event counter (a) processing on starting counting ; set ce2 to 1 ; clear pif2 to 0 clear intp2 interrupt request flag pif2 0 start count ce2 1 start count end (b) processing on reading count value ; number of input valid edges is set to a register count value read read tm2 contents a tm2 a a + 1 end a = 0? pif2 = 1? ; check tm2 value. if 0, check interrupt request flag. ; check pif2 contents. if 1, valid edge is input. yes no yes no chapter 10 timer/counter 2 356 user s manual u11316ej4v1ud (10) even if an attempt is mode to clear the timer register by inputting the capture request signal when the capture function of the timer is used, the timer register momentarily counts up immediately before it is cleared. consequently, if a value greater than the value of the timer register by 1 is set to the compare register when the capture request signal is input, the values of the compare register and timer register coincide, and an unnecessary interrupt will be generated (refer to figure 10-66). therefore, take the following operation into consideration when creating a program. chapter 10 timer/counter 2 357 user s manual u11316ej4v1ud (11) if the count operation of tm2 stops at the timing at which compare register (cr20) and timer register 2 (tm2) match, the cr20/tm2 match interrupt may not be generated after timer/counter 2 is next started. if the tm2 count operation is stopped within 1.5 count clocks after a match between cr20 and tm2, the first match interrupt after timer/counter 2 is next started will not be generated. the second and subsequent interrupts operate normally. note that the timer output is unaffected by this bug. this bug occurs because the timer interrupt controller inadvertently masks interrupts if timer/counter 2 is stopped in the period indicated by the shaded area in the figure below. the interrupt controller is initialized by an overflow of timer/counter 2 or a match between cr21 and tm2. count clocks 1.5 count clocks not generated tm2 m + 1 m m ? 1 1 0 0 m mm nn m ? 1 cr20 cr21 ce2 cr20/tm2 match interrupt remark m < n do not stop timer/counter 2 within 1.5 count clocks after a match between cr20 and tm2. disable all interrupt requests (including macro servicing), read the value of the timer to be stopped, and wait until at least 1.5 count clocks have elapsed after a match between cr20 and tm2 before stopping timer/counter 2. 358 user? manual u11316ej4v1ud chapter 11 timer 3 11.1 function timer 3 is a 16- or 8-bit timer. in addition to its function as an interval timer, it can be used as a counter for clocked serial interface (csi) clock generati on. the interval timer generates internal interrupts at pre-set intervals. the interval setting range is shown in table 11.1. table 11-1 timer 3 intervals minimum interval maximum interval resolution 8/f xx 2 16 8/f xx 8/f xx (0.25 s) (16.40 ms) (0.25 ms) 16/f xx 2 16 16/f xx 16/f xx (0.50 s) (32.80 ms) (0.50 ms) 32/f xx 2 16 32/f xx 32/f xx (1.00 s) (65.50 ms) (1.00 ms) 64/f xx 2 16 64/f xx 64/f xx (2.00 s) (131 ms) (2.00 ms) 128/f xx 2 16 128/f xx 128/f xx (4.00 s) (262 ms) (4.00 ms) 256/f xx 2 16 256/f xx 256/f xx (8.00 s) (524 ms) (8.00 ms) 512/f xx 2 16 512/f xx 512/f xx (16.00 s) (1.05 s) (16.00 ms) 1,024/f xx 2 16 1,024/f xx 1,024/f xx (32.00 s) (2.10 s) (32.00 ms) 2,048/f xx 2 16 2,048/f xx 2,048/f xx (64.00 s) (4.19 s) (64.00 ms) ( ): when f xx = 32 mhz chapter 11 timer 3 359 user? manual u11316ej4v1ud 11.2 configuration timer 3 consists of the following registers: timer register (tm3/tm3w) 1 compare register (cr30/cr30w) 1 the block diagram of timer 3 is shown in figure 11-1. figure 11-1 timer 3 block diagram fxx/2048 fxx/1024 fxx/512 fxx/256 fxx/128 fxx/64 fxx/32 fxx/16 fxx/8 fxx prs3 prs2 prs1 prs0 ce3 1/8 bw3 8 timer control register 0 (tmc0) internal bus internal bus compare register (cr30/cr30w) 16 16 timer register 3 (tm3/tm3w) prescaler selector 8/16 8/16 reset match clear intc30 clocked serial interface prescaler mode register 0 (prm0) chapter 11 timer 3 360 user s manual u11316ej4v1ud (1) timer register 3 (tm3/tm3w) tm3/tm3w are timer registers that count up using the count clock specified by the high-order 4 bits of prescaler mode register 0 (prm0). the count operation is stopped or enabled by the timer control register 0 (tmc0). in addition, an 8-bit mode (tm3) or 16-bit mode (tm3w) can be selected. tm3 can be read only with an 8/16-bit manipulation instruction. when reset is input, tm3 is cleared to 00h and the count is stopped. caution if the value of the timer register is read under the condition indicated by ?in table 11-2, the read value may be illegal. do not read the timer register under condition ? table 11-2 limits of reading timer register ( : can be read, : must not be read) f clk f xx /2 f xx /4 f xx /8 f xx /16 timer count clock f xx /8 ?? f xx /16 ??? f xx /n ??? remarks 1. f xx : oscillation frequency 2. f clk : internal system clock frequency 3. n = 32, 64, 128, 256, 512, 1,024, 2,048 (2) compare register (cr30/cr30w) cr30/cr30w are 8/16-bit registers that hold the value that determines the interval timer frequency. if the cr30/cr30w contents match the contents of tm3/tm3w, the contents of tm3/tm3w are cleared automatically and an interrupt request (intc30) is generated. this compare register operates as cr30 in the 8-bit mode and cr30w in the 16-bit mode. the cr30 register can be read or written to with an 8/16-bit manipulation instruction. the contents of cr30 are undefined after reset input. (3) prescaler the prescaler generates the count clock from the internal system clock. the clock generated by the prescaler is selected by the selector, and is used as the count clock by the timer to perform count operations. (4) selector the selector selects a signal resulting from dividing the internal clock or the edge detected by the edge detection circuit as the count clock of timer register 3 (tm3/tm3w). chapter 11 timer 3 361 user s manual u11316ej4v1ud 11.3 timer 3 control registers (1) timer control register 0 (tmc0) tmc0 controls the timer 3, tm3/tm3w, count operation by the high-order 4 bits (the low-order 4 bits control the count operation of timer/counter 0, tm0). tmc0 can be read or written to with an 8-bit manipulation instruction. the format of the tmc0 is shown in figure 11-2. reset input clears tmc0 to 00h. figure 11-2 timer control register 0 (tmc0) format 7 ce3 tmc0 6 0 5 0 4 bw3 3 ce0 2 ovf0 1 0 0 0 ce3 tm3/tm3w count operation control count operation stopped with count cleared count operation enabled 1 0 bw3 timer 3 bit length specification 8-bit operating mode 16-bit operating mode 1 0 controls count operation of timer/counter 0, tm0 (see figure 8-2 ). address after reset r/w r/w 00h 0ff5dh chapter 11 timer 3 362 user s manual u11316ej4v1ud (2) prescaler mode register 0 (prm0) prm0 specifies the count clock to timer/counter 3 tm3/tm3w by the high-order 4 bits (the low-order 4 bits specify the count clock to timer/counter 0, tm0). prm0 can be read and written with an 8-bit manipulation instruction. the format of the prm0 is shown in figure 11-3. reset input clears prm0 to 11h. figure 11-3 prescaler mode register 0 (prm0) format 7 prs3 prm0 6 prs2 5 prs1 4 prs0 3 prs03 2 prs02 1 prs01 0 prs00 address after reset r/w r/w (f xx = 32 mhz) 11h 0ff5ch prs3 prs2 prs1 prs0 timer 3 tm3/tm3w count clock specification count clock [hz] specification setting prohibited f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 f xx /2,048 resolution [ s] 0.25 0.50 1.00 2.00 4.00 8.00 16.00 32.00 64.00 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 specifies count clock to timer/counter 0 (tm0), tm0 (see figure 8-3 ). other than the above setting prohibited chapter 11 timer 3 363 user s manual u11316ej4v1ud 11.4 timer register 3 (tm3) operation 11.4.1 basic operation timer 3 can operate in an 8-bit or 16-bit mode. these operation modes are selected by bit 4 (bw3) of timer control register 0 (tmc0) note . in the timer 3 count operation, an up-count is performed using the count clock specified by the high-order 4 bits of prescaler mode register 0 (prm0). when reset is input, tm3 is cleared to 0000h, and the count operation is stopped. count operation enabling/disabling is controlled by bit 7 (ce3) of timer control register 0 (tmc0) (the high-order 4 bits of tmc0 control timer 3 operation). when the ce3 bit is set (to 1) by software, the contents of tm3 are immediately cleared on the first count clock, and then the up-count operation is performed. when the ce3 bit is cleared (to 0), tm3 becomes 0h immediately, and match signal generation is stopped. if the ce3 bit is set (to 1) again when it is already set (to 1), tm3 continues the count operation without being cleared. note unless there functional differences are found, the register names in the 8-bit mode are used. in the 16-bit mode, the register names tm3 and cr30 are tm3w and cr30w, respectively. chapter 11 timer 3 364 user s manual u11316ej4v1ud figure 11-4 basic operation in 8-bit operating mode (bw3 = 0) (a) count started count stopped count started 0h 0h 1h 2h 0fh 10h 11h 0h 0h 0h count started ce3 1 count clock count started ce3 1 tm3 ce3 count stopped ce3 0 (b) when 1 is written to the ce3 bit again after the count starts count started ce3 1 rewrite ce3 1 count clock tm3 ce3 0h 0h 1h 2h 3h 4h 5h 6h chapter 11 timer 3 365 user s manual u11316ej4v1ud figure 11-5 basic operation in 16-bit operating mode (bw3 = 1) (a) count started count stopped count started 0h 0h 1h 2h ffh 100h 101h 0h 0h 0h count started ce3 1 count clock count started ce3 1 tm3w ce3 count stopped ce3 0 (b) when 1 is written to the ce3 bit again after the count starts count started ce3 1 rewrite ce3 1 count clock tm3w ce3 0h 0h 1h 2h 3h 4h 5h 6h chapter 11 timer 3 366 user s manual u11316ej4v1ud 11.4.2 clear operation (1) clear operation by match with compare register (cr30) 16-bit timer 3 (tm3) is cleared automatically after a match with the compare register (cr30). when a clearance source arises, tm3 is cleared to 0h on the next count clock. therefore, even if a clearance source arises, the value at the point at which the clearance source arose is retained until the next count clock arrives. figure 11-6 tm3 clearance by match with compare register (cr30) count clock tm3 n 0 1 n - 1 compare register (cr30) n tm3 and cr30 match cleared here (2) clear operation by ce3 bit of timer/control register 0 (tmc0) timer register 3 (tm3) is also cleared when the ce3 bit of tmc0 is cleared (to 0) by software. the clear operation is performed following clearance (to 0) of the ce3 bit in the same way. chapter 11 timer 3 367 user s manual u11316ej4v1ud figure 11-7 clear operation when ce3 bit is cleared (to 0) (a) basic operation count clock tm3 n 0 n - 1 ce3 (b) restart before count clock is input after clearance count clock tm3 n n - 1 ce3 0 12 if the ce3 bit is set (to 1) before this count clock, the count starts from 0 on this count clock 0 (c) restart when count clock is input after clearance count clock tm3 n 0 n - 1 ce3 0 01 if the ce3 bit is set (to 1) from this count clock onward, the count starts from 0 on the count clock after the ce3 bit is set (to 1). chapter 11 timer 3 368 user s manual u11316ej4v1ud 11.5 compare register operation timer 3 performs compare operations in which the value set in the compare register (cr30) is compared with the timer register 3 (tm3) count value. if the count value of tm3 matches the preset cr30 value as the result of the count operation, an interrupt request (intc30) is generated. after a match, the tm3 contents are cleared automatically, and therefore tm3 functions as an interval timer that repeatedly counts up to the value set in the cr30. figure 11-8 compare operation cr30 tm3 count value 0h intc30 interrupt request count start ce 1 clear (match) clear (match) cr30 chapter 11 timer 3 369 user s manual u11316ej4v1ud 11.6 example of use operation as interval timer: tm3 operates as an interval timer that generates interrupts repeatedly with the pre-set count time as the interval (see figure 11-9 ). tm3 can also be used for baud rate generation. this interval timer can count up to a maximum of 16.40 ms at the minimum resolution of 0.25 s, and up to 4.19 s at the maximum resolution of 64.00 s (internal system clock f xx = 32 mhz). the control register settings are shown in figure 11-10, and the setting procedure in figure 11-11. figure 11-9 interval timer operation timing n count start clear clear n interrupt acknowledgment interrupt acknowledgment interval interval tm3 count value 0h intc30 interrupt request compare register (cr30) n remark interval = (n + 1) x/f xx 0 n ffh, x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048 chapter 11 timer 3 370 user s manual u11316ej4v1ud figure 11-10 control register settings for interval timer operation prescaler mode register 0 (prm0) 7 prs3 prm0 6 prs2 5 prs1 4 prs0 3 0 2 0 1 0 0 0 count clock specification (x/f xx ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048) figure 11-11 interval timer operation setting procedure interval timer ; set 1 in bit 7 of tmc0 set prm0 set count value in cr30 cr30 n start count ce3 1 intc30 interrupt chapter 11 timer 3 371 user s manual u11316ej4v1ud disables interrupts from timer 3 clears timer 3 interrupt request flag interrupt request generated by timer 3 here 11.7 cautions (1) there is a possibility of malfunction if the contents of prescaler mode register 0 (prm0) are rewritten while the timer 3 is running (when the ce3 bit of the timer control register 0 (tmc0) is set). the malfunction occurs as there is no defined order of priority in the event of contention between the timings at which the hardware function changes due to a register rewrite and the status changes in the function prior to the rewrite. when the contents of prm0 are rewritten, counter operations must be stopped first to ensure stability. (2) if the compare register (cr30) and tm3 contents match when an instruction that stops timer register 3 (tm3) operation is executed, the tm3 count operation stops, but an interrupt request is generated. if you do not want an interrupt to be generated when tm3 operation is stopped, interrupts should be masked by means of interrupt the mask register before stopping the tm3. example program in which an interrupt request may be program in which an interrupt request is not generated generated clr1 ce3 set1 cmk30 set1 cmk30 clr1 ce3 clr1 cif30 chapter 11 timer 3 372 user s manual u11316ej4v1ud (3) there is a delay of up to one count clock between the operation that starts a timer 3 (ce3 1) and the actual start of the timer/counter (see figure 11-23 ). for example, if a timer/counter is used as an interval timer, the first interval will be extended by up to one clock. the second and subsequent intervals will be as specified. figure 11-12 operation when count starts count clock tm3 0 ce3 03 1 2 timing at which count actually starts software count start directive (ce3 1) (4) while an instruction that writes data to the compare register (cr30) is executed, match between cr30, to which the data is to be written, and timer register 3 (tm3) is not detected. write data to cr30 when timer 3 is executing counting operation so that the contents of tm3 do not match the value of cr30 before and after writing (e.g., immediately after an interrupt request has been generated because tm3 and cr30 have matched). (5) match between timer register 3 (tm3) and compare register (cr30) is detected only when tm3 is incremented. therefore, the interrupt request is not generated even if the same value as tm3 is written to cr30. (6) if the value of the timer register is read under the condition indicated by in table 11-3, the read value may be illegal. do not read the timer register under condition . table 11-3 limits of reading timer register ( : can be read, : must not be read) f clk f xx /2 f xx /4 f xx /8 f xx /16 timer count clock f xx /8 ?? f xx /16 ??? f xx /n ??? remarks 1. f xx : oscillation frequency 2. f clk : internal system clock frequency 3. n = 32, 64, 128, 256, 512, 1,024, 2,048 373 user? manual u11316ej4v1ud chapter 12 watchdog timer function the watchdog timer is a timer that detects inadvertent program loops. watchdog timer interrupts are used to detect system or program errors. for this purpose, instructions that clear the watchdog timer (start the count) within a given period are inserted at various places in a program. if an instruction that clears the watchdog timer is not executed within the set time and the watchdog timer overflows, a watchdog timer interrupt (intwdt) is generated and a program error is reported. 12.1 configuration the watchdog timer block diagram is shown in figure 12-1. figure 12-1 watchdog timer block diagram watchdog timer clear signal f clk /2 17 f clk /2 19 f clk /2 20 f clk /2 21 intwdt selector f clk chapter 12 watchdog timer function 374 user? manual u11316ej4v1ud 12.2 watchdog timer mode register (wdm) the wdm is an 8-bit register that controls the watchdog timer operation. to prevent erroneous clearing of the watchdog timer by an inadvertent program loop, writing can only be performed by a dedicated instruction. this dedicated instruction, mov wdm, #byte, has a special code configuration (4 bytes), and a write is not performed unless the 3rd and 4th bytes of the operation code are mutual complements. if the 3rd and 4th bytes of the operation code are not complements, a write is not performed and an operand error interrupt is generated. in this case, the return address saved in the stack area is the address of the instruction that was the source of the error, and thus the address that was the source of the error can be identified from the return address saved in the stack area. if recovery from an operand error is simply performed by means of an retb instruction, an endless loop will result. as an operand error interrupt is only generated in the event of an inadvertent program loop (with the nec electronics assembler, ra78k4, only the correct dedicated instruction is generated when mov wdm, #byte is written), system initialization should be performed by the program. other write instructions (mov wdm, a, and wdm, #byte, set1 wdm.7, etc.) are ignored and do not perform any operation. that is, a write is not performed to the wdm, and an interrupt such as an operand error interrupt is not generated. after a system reset (reset input), once the watchdog timer has been started (by setting (to 1) the run bit), the wdm contents cannot be changed. the watchdog timer can only be stopped by a reset, but can be cleared at any time with a dedicated instruction. the wdm can be read at any time by a data transfer instruction. reset input clears the wdm to 00h. the wdm format is shown in figure 12-2. chapter 12 watchdog timer function 375 user s manual u11316ej4v1ud figure 12-2 watchdog timer mode register (wdm) format 7 run wdm 6 0 5 0 4 prc 3 0 2 wdi2 1 wdi1 0 0 address after reset r/w r/w 00h ffc2h wdi2 overflow time [ms] f clk = 16 mhz 2 17 /f clk (8.19) 0 0 wdi2 1 0 prc watchdog timer interrupt request priority specification watchdog timer interrupt request < nmi pin input interrupt request watchdog timer interrupt request > nmi pin input interrupt request 1 clear watchdog timer and start count 1 0 run watchdog timer operation specification watchdog timer stopped 0 2 19 /f clk (32.77) 10 2 20 /f clk (65.54) 11 2 21 /f clk (131.07) remark f clk : internal system clock frequency cautions 1. the watchdog timer mode register (wdm) can only be written to with a dedicated instruction (mov wdm, #byte). 2. the same value should be written each time in writes to the wdm to set (to 1) the run bit. the contents written the first time cannot be changed even if a different value is written. 3. once the run bit has been set (to 1), it cannot be reset (to 0) by software. chapter 12 watchdog timer function 376 user s manual u11316ej4v1ud 12.3 operation 12.3.1 count operation the watchdog timer is cleared, and the count started, by setting (to 1) the run bit of the watchdog timer mode register (wdm). when overflow time specified by the wdm2 and wdm1 bits of wdm has elapsed after the run bit has been set (to 1), a non-maskable interrupt (intwdt) is generated. if the run bit is set (to 1) again before the overflow time elapses, the watchdog timer is cleared and the count operation is started again. 12.3.2 interrupt priorities the watchdog timer interrupt (intwdt) is a non-maskable interrupt. other non-maskable interrupts are interrupts from the nmi pin (nmi). the order of acknowledgment when an intwdt interrupt and nmi interrupt are generated simultaneously can be specified by the setting of bit 4 of the watchdog timer mode register (wdm). even if intwdt is generated while the nmi processing program is executed when nmi acknowledgement is specified to take precedence, intwdt is not acknowledged until completion of execution of the nmi processing program. chapter 12 watchdog timer function 377 user s manual u11316ej4v1ud 12.4 cautions 12.4.1 general cautions on use of watchdog timer (1) the watchdog timer is one means of detecting inadvertent program loops, but it cannot detect all inadvertent program loops. therefore, in equipment that requires a high level of reliability, you should not rely on the on-chip watchdog timer alone, but should use external circuitry for early detection of inadvertent program loops, to enable processing to be performed that will restore the normal state or establish a stable state and then stop the operation. (2) the watchdog timer cannot detect inadvertent program loops in the following cases. <1> if watchdog timer clearance is performed in the timer interrupt service program <2> if cases where an interrupt request or macro service is held pending (see 22.9 ) occur consecutively <3> if the watchdog timer is cleared periodically when inadvertent program looping is due to an error in the program logic (if each module of the program functions normally but the overall program does not) <4> if the watchdog timer is periodically cleared by a group of instructions executed when an inadvertent program loop occurs <5> if the stop mode, halt mode, or idle mode is entered as the result of an inadvertent program loop <6> if watchdog timer runaway also occurs in the event of cpu runaway due to external noise in cases <1>, <2> and <3> the program can be amended to allow detection to be performed. in case <4>, the watchdog timer can only be cleared by a 4-byte dedicated instruction. similarly, in case <5>, the stop mode, halt mode, or idle mode cannot be set unless a 4-byte dedicated instruction is used. for state <2> to be entered as the result of an inadvertent program loop, 3 or more consecutive bytes of data must comprise a specific pattern (e.g. bt pswl.bit, $$, etc.). therefore, the establishment of state <2> as the result of <4>, <5> or an inadvertent program loop is likely to be extremely rare. 12.4.2 cautions on pd784038 subseries watchdog timer (1) the watchdog timer mode register (wdm) can only be written to with a dedicated instruction (mov wdm, #byte). (2) the same value should be written each time in writes to the watchdog timer mode register (wdm) to set (to 1) the run bit. the contents written the first time cannot be changed even if a different value is written. (3) once the run bit has been set (to 1), it cannot be reset (to 0) by software. 378 user? manual u11316ej4v1ud chapter 13 pwm output unit the pd784038 incorporates two 12-bit resolution pwm (pulse width modulation) output circuit channels. the active level of the pwm output pulses can be selected as high or low. the pwm output ports have a dual function as pins p10 and p11. 13.1 pwm output unit configuration the pwm output unit configuration is shown in figure 13-1. figure 13-1 pwm output unit configuration internal bus 16 15 87 43 0 pwmn 8 pwpr prescaler f clk 8 8-bit down-counter f pwmc 1/256 4-bit counter pwm pulse generator 4 reload control reload reload 8 pwmc output control circuit p1n/ pwmn remark n = 0, 1 (1) 8-bit down-counter generates the basic pwm signal timing. (2) pwm pulse generator (including 4-bit counter) controls addition of extra pulses and generates the pwm pulses to be output. (3) reload control controls 8-bit down counter and 4-bit count modulo value reloading. (4) output control circuit controls the active level of the pwm signal. (5) prescaler scales f clk , and generates the reference clock. chapter 13 pwm output unit 379 user s manual u11316ej4v1ud 13.2 pwm output unit control registers 13.2.1 pwm control register (pwmc) the pwmc is an 8-bit register that controls the operating status of the pwm output pins (pwmn: n = 0, 1). the pwmc can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. its format is shown in figure 13-2. when reset is input, pwmc is set to 05h, the pwmn pin is set to port mode, and the input state (output high impedance) is set. figure 13-2 pwm control register (pwmc) format 7 syn1 pwmc 6 0 5 syn0 4 0 3 en1 2 alv1 1 en0 0 alv0 address after reset r/w r/w 05h 0ff70h alvn pwmn pin pwm active level specification (n = 0, 1) active-low active-high 1 0 enn pwmn pin pwm output control output disabled. the pin level is determined by the contents of th pm1, p1 and pu0 (port mode). pwm output enabled synn pwm pulse width rewrite cycle specification rewritten every 16 pwm cycles (2 12 /f pwmc ) rewritten every pwm cycle (2 8 /f pwmc ) 1 0 1 0 chapter 13 pwm output unit 380 user s manual u11316ej4v1ud 13.2.2 pwm prescaler register (pwpr) the pwpr is an 8-bit register that selects the pwm output circuit operating clock (f pwmc ). the pwpr can be read or written to with an 8-bit manipulation instruction. its format is shown in figure 13-3. when reset is input, pwpr is cleared to 00h, and f clk is selected as f pwmc for both channels. figure 13-3 pwm prescaler register (pwpr) format 7 0 pwpr 6 pwp12 5 pwp11 4 pwp10 3 0 2 pwp02 1 pwp01 0 pwp00 address after reset r/w r/w 00h 0ff71h pwpn2 pwmn operating clock (f pwmc ) pwmn repetition frequency (f clk = 16 mhz) f clk f clk /256 (62.5 khz) (n = 0, 1) 0 0 other than the above setting prohibited pwpn1 0 0 f clk /512 (31.3 khz) 01 f clk /2 f clk /768 (20.8 khz) 01 pwpn0 1 0 0 1 f clk /3 f clk /1,024 (15.6 khz) 100 f clk /4 13.2.3 pwm modulo registers (pwm0, pwm1) the pwm modulo register 16-bit register (pwmn: n = 0, 1) is a 16-bit register that determines the pwm pulse width. reads/writes by a 16-bit manipulation instruction only are possible for data setting. the contents of bits 4 to 15 of the pwmn determines the 12-bit pwm pulse width (12-bit resolution). bits 3 to 0 have no meaning, and pwm output is not affected whether 1 or 0 is written to these bits. when reset is input, the pwmn content are undefined, and therefore data must be set by the program before pwm output is enabled. caution a value between 0000h and 00ffh should not be set in the pwm modulo registers (pwmn: n = 0, 1). a value between 0100h and ffffh should be set in the pwmn registers. outputtable pwm signal duty values are 17/4,096 to 4,096/4,096. chapter 13 pwm output unit 381 user s manual u11316ej4v1ud 13.3 pwm output unit operation 13.3.1 basic pwm output operation the pwm pulse output duty is determined by the value set in bits 4 to 15 of the pwm modulo register (pwmn: n = 0, 1) as shown below. pwm pulse output duty = note 16 (value of pwmn bits 4 to 15) 4,095 the pwm pulse output repetition frequency is the frequency obtained by division-by-256 of the pwm clock f clk /1 to f clk /4 set by the pwm prescaler register (pwpr) (= f pwmc /256), and the minimum pulse width is 1/f pwmc . in pwm pulse output, 12-bit resolution is achieved by repeating output of a f pwmc /256 repetition frequency 8-bit resolution pwm signal 16 times. the addition of extra pulses (1/f pwmc ) to the 8-bit resolution pwm pulses determined by bits 8 to 15 of the pwmn every cycle is controlled in accordance with the value of bits 4 to 7 of the pwmn to implement a pwm pulse signal once every 16 cycles. figure 13-4 basic pwm output operation pwm signal note one 12-bit pwm signal cycle note 8-bit resolution per pwm pulse cycle (value of pwmn bits 4 to 15) note + 1 4,096 chapter 13 pwm output unit 382 user s manual u11316ej4v1ud 13.3.2 pwm pulse output enabling/disabling when pwm pulses are output, the enn (n = 0, 1) bits of the pmc register are set (to 1) after data is set in the pwm prescaler register (pwpr) and pwm modulo register (pwmn: n = 0, 1). as a result, pwm pulses with the active level specified by alvn (n = 0, 1) bit of the pwm control register (pwmc) are output from the pwm output pin. when the enn bits of the pwmc are cleared (to 0), the pwm output unit immediately stops the pwm output operation and the pwm output pins are set to the state specified by the pm1, p1 and puo registers. that is, when pm1n (n = 0, 1) in the port 1 mode register (pm1) is 0, the output state is set and the contents of p1n (n = 0, 1) are specified. when pm1n = 1 (n = 0, 1) the input state is set, when puo1 in the pull-up resistor option register (puo) is 1 the high level is set by the on-chip pull-up resistor, and when puo1 = 0 the output high-impedance state is set. 13.3.3 pwm pulse active level specification the alvn (n = 0, 1) bit of the pwm control register (pwmc) specify the active level of pwm pulses output from the pwm output pins. when alvn bit is set (to 1), active-high level pulses are output, and when cleared (to 0), active-low level pulses are output. when alvn bit is rewritten, the pwm active level changes immediately. pwm output active level setting and pin states are shown in figure 13-5. figure 13-5 shows the case where alvn bit is switched when the enn (n = 0/1) bit of the pwmc is set (to 1) and pwm output is enabled. the pin state does not change if alvn is rewritten when enn bit is in the cleared (to 0) state. figure 13-5 pwm output active level setting alvn pwmn (active-high) (active-low) (alvn bit rewrite) remark enn = 1 (n = 0, 1) chapter 13 pwm output unit 383 user s manual u11316ej4v1ud 13.3.4 pwm pulse width rewrite cycle specification the start of pwm output and pulse width changes are performed in synchronization either with every 16 pwm pulse cycles (2 12 /f pwmc ) or with every pwm pulse cycle (2 8 /f pwmc ). this pwm pulse width rewrite cycle specification is performed by means of the synn bits of the pwm control register (pwmc). when the synn bit is cleared (to 0), a pulse width change is performed every 16 pwm pulse cycles (2 12 /f pwmc ). it therefore takes a maximum of 2 12 clocks (256 s when f pwmc = 16 mhz) until a pulse of a width corresponding to the data written in the pwm modulo register (pwmn: n = 0, 1) is output. an example of the pwm output timing at this time is shown in figure 13-6. when the synn bit is set (to 1), on the other hand, a pulse width change is performed every pwm pulse cycle (2 8 /f pwmc ). in this case, it takes a maximum of 2 8 clocks (16 s when f pwmc = 16 mhz) until a pulse of a width corresponding to the data written in the pwmn in is output. however, caution is required since, if the pwm pulse rewrite cycle is specified as every 2 8 /f pwmc , (if the synn bit is set (to 1)), the obtained pwm pulse precision is between 8 bits and 12 bits, and is lower than when the pwm pulse rewrite cycle is specified as 2 12 /f pwmc . an example of the pwm output timing when the rewrite timing is 2 8 /f pwmc is shown in figure 13-7. figure 13-6 pwm output timing example 1 (pwm pulse width rewrite cycle = 2 12 /f pwmc ) pwm output pin pwmn contents pwm output enabled pwm pulse width switching timing pwm pulse width switching timing pwm pulse width switching timing pwmn rewrite nm 16 pwm pulse cycles 16 pwm pulse cycles cautions 1. pulse width rewriting is performed every pwm pulse cycle. 2. the pwm pulse precision is 12 bits. chapter 13 pwm output unit 384 user s manual u11316ej4v1ud figure 13-7 pwm output timing example 2 (pwm pulse width rewrite cycle = 2 8 /f pwmc ) 1 pwm pulse cycle pwm output pin pwmn contents pwm output enabled pwmn rewrite pwmn rewrite pwmn rewrite pwm pulse width switchin g timin g ni m n cautions 1. pulse width rewriting is performed every pwm pulse cycle. 2. the pwm pulse precision is between 8 and 12 bits. remark l, m, and n mean the pwmn contents. 13.4 caution a value between 0000h and 00ffh should not be set in the pwm modulo registers (pwmn: n = 0, 1). a value between 0100h and ffffh should be set in the pwmn. outputtable pwm signal duty values are 17/4096 to 4096/4096. 385 user? manual u11316ej4v1ud chapter 14 a/d converter the pd784038 incorporates an analog/digital (a/d) converter with 8 multiplexed analog inputs (ani0 to ani7). the successive approximation conversion method is used, and the conversion result is held in the 8-bit a/d conversion result register (adcr). this allows fast, high-precision conversion to be performed (conversion time of 7.5 s when f clk = 16 mhz and high-speed conversion is used). there are two modes for starting a/d conversion, as follows: hardware start : conversion started by trigger input (intp5). software start : conversion started in accordance with a/d converter mode register (adm) bit setting. after start-up, there are two operating modes, as follows: scan mode : multiple analog inputs are selected in order, and conversion data is obtained from all pins. select mode: one pin is used as the analog input, and conversion values are obtained in succession. stoppage of all the above modes and conversion operations is specified by the adm register. when the conversion result is transferred to the adcr, an intad interrupt request is generated. this allows conversion values to be transferred to memory in succession by means of macro service. 14.1 configuration the a/d converter configuration is shown in figure 14-1. chapter 14 a/d converter 386 user? manual u11316ej4v1ud figure 14-1 a/d converter block diagram internal bus 8 8 a/d converter mode register (adm) reset 8 successive approximation register (sar) edge detection circuit intp5 ani7 ani6 ani5 ani4 ani3 ani2 ani1 ani0 sample & hold circuit ta p selector av ref1 r/2 r r/2 voltage comparator intad control circuit conversion trigger trigger enable av ss a/d conversion result register (adcr) series resistor string input selector chapter 14 a/d converter 387 user s manual u11316ej4v1ud cautions 1. a capacitor should be connected between the analog input pins (ani0 to ani7) and av ss and between the reference voltage input pin (av ref ) and av ss to prevent malfunction due to noise. be sure to connect the capacitor as closely to ani0 through ani7 and av ref1 as possible. figure 14-2 example of capacitor connection on a/d converter pins analog input reference voltage input 100 to 500 pf ani0 to ani7 av ref1 av ss pd784038 2. a voltage outside the range av ss to av ref1 should not be applied to pins used as a/d converter input pins. see 14.5 cautions for details. (1) input circuit the input circuit selects the analog input in accordance with the specification of the a/d converter mode register (adm), and sends the analog input to the sample & hold circuit according to the operating mode, (2) sample & hold circuit the sample & hold circuit samples the analog inputs arriving sequentially one by one and holds the analog input in the process of a/d conversion. (3) voltage comparator the voltage comparator determines the voltage difference between the analog input and the series resistor string value tap. (4) series resistor string the series resistor string is used to generate voltages that match the analog inputs. the series resistor string is connected between the a/d converter reference voltage pin (av ref1 ) and the a/d converter gnd pin (av ss ). to provide 256 equal voltage steps between the two pins, it is made up of 255 equal resistors and two resistors with half that resistance value. the series resistor string voltage tap is selected by a tap selector controlled by the sar successive approximation register. chapter 14 a/d converter 388 user s manual u11316ej4v1ud (5) sar: successive approximation register the sar is an 8-bit register in which the data for which the series resistor string voltage tap value matches the analog input voltage value is set bit by bit starting from the most significant bit (msb). when data has been set up to the least significant bit (lsb) of the sar (when a/d conversion is completed), the sar contents (conversion result) are stored in the a/d conversion result register (adcr). (6) adcr: a/d conversion result register the adcr is an 8-bit register that holds the a/d conversion result. the conversion result is loaded into this register from the successive approximation register (sar) each time a/d conversion finishes. the contents of this register approximation are undefined when reset is input. (7) edge detection circuit the edge detection circuit detects a valid edge from the interrupt request input pin (intp5) input, and generates an external interrupt request signal (intp5) and a/d conversion operation external trigger. the intp5 pin input valid edge is specified by external interrupt mode register 1 (intm1) (see figure 21-2 ). external trigger enabling/disabling is set by means of the a/d converter mode register (adm) (see 14.2 a/d converter mode register (adm) ). chapter 14 a/d converter 389 user s manual u11316ej4v1ud 14.2 a/d converter mode register (adm) adm is an 8-bit register that controls a/d converter operations. the adm register can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. its format is shown in figure 14-3. bit 0 (ms) controls the operating mode. bits 1, 2 and 3 (ani0, 1, 2) select the analog inputs for a/d conversion. bit 5 (scmd) controls the a/d conversion operation in scan mode. bit 6 (trg) enables external synchronization of the a/d conversion operation. if the trg bit is set (to 1) when the cs bit is set (to 1), the conversion operation is initialized with each input of a valid edge as an external trigger to the intp5 pin. when the trg bit is cleared (to 0), the conversion operation is performed without regard to the intp5 pin. bit 7 (cs) controls the a/d conversion operation. when the cs bit is set (to 1) the conversion operation is started, and when cleared (to 0), all conversion operations are stopped even if conversion is in progress. in this case, the a/d conversion result register (adcr) is not updated and an intad interrupt request is not generated. also, the power supply to the voltage comparator is stopped, and the a/d converter power consumption is reduced. reset input clears the adm register to 00h. caution when the stop mode or idle mode is used, the power consumption should be reduced by clearing (to 0) the cs bit before entering the stop or idle mode. if the cs bit remains set (to 1), the conversion operation will be stopped by entering the stop or idle mode, but the power supply to the voltage comparator will not be stopped, and therefore the a/d converter power consumption will not be reduced. chapter 14 a/d converter 390 user s manual u11316ej4v1ud figure 14-3 a/d converter mode register (adm) format 7 cs adm 6 trg 5 scmd 4 fr 3 anis2 2 anis1 1 anis0 0 ms address after reset r/w r/w 00h 0ff68h anis2 a/d conversion operating mode setting scan mode (0/1) select mode 0 0 anis1 0 0 ani0 input scanned input ani0 & ani1 scanned input ani0 to ani2 scanned input ani0 to ani3 scanned 01 01 anis0 1 0 0 1 input ani0 to ani4 scanned input ani0 & ani5 scanned input ani0 to ani6 scanned input ani0 to ani7 scanned ani0 input selected ani1 input selected ani2 input selected ani3 input selected ani4 input selected ani5 input selected ani6 input selected ani7 input selected 100 ms 0 0 0 0 0 1010 1100 0001 0011 0101 0111 1001 1011 1101 1111 1110 fr conversion speed control (f clk = 16 mhz) 1 0 242/f clk (15.125 s) low-speed conversion high-speed conversion 120/f clk (7.5 s) trg external trigger control 1 0 external trigger disabled external trigger enabled cs a/d conversion operation control stop a/d conversion operation start a/d conversion operation 1 0 scmd scan mode selection 1 0 scan mode 0 (no delay control) ms 0 0 0 select mode 1 1 setting prohibited 1 scan mode 1 (delay control) chapter 14 a/d converter 391 user s manual u11316ej4v1ud caution once the a/d converter starts operating, conversion operations are performed repeatedly until the cs bit of the a/d converter mode register (adm) is cleared (to 0). therefore, a superfluous interrupt may be generated if adm setting is performed after interrupt-related registers, etc., when a/d converter mode conversion, etc., is performed. the result of this superfluous interrupt is that the conversion result storage address appears to have been shifted when the scan mode is used. also, when the select mode is used, the first conversion result appears to have been an abnormal value, such as the conversion result for the other channel. it is therefore recommended that a/d converter mode conversion be carried out using the following procedure. <1> write to the adm (cs bit must be set (to 1)) <2> interrupt request flag (adif) clearance (to 0) <3> interrupt mask flag or interrupt service mode flag setting operations <1> to <3> should not be divided by an interrupt or macro service. when scan mode 0 (no delay control) is used, in particular, you should ensure that the time between <1> and <2> is less than the time taken by one a/d conversion operation. alternatively, the following procedure is recommended. <1> stop the a/d conversion operation by clearing (to 0) the cs bit of the adm. <2> interrupt request flag (adif) clearance (to 0). <3> interrupt mask flag or interrupt service mode flag setting <4> write to the adm chapter 14 a/d converter 392 user s manual u11316ej4v1ud 14.3 operation 14.3.1 basic a/d converter operation (1) a/d conversion operation procedure a/d conversion is performed by means of the following procedure: (a) analog pin selection and operating mode specification are set with the a/d converter mode register (adm). (b) bit 7 (cs) of the adm is set (to 1), and a/d conversion is started. (c) when conversion starts, the msb (bit 7) of the successive approximation register (sar) is set (to 1) automatically. (d) when bit 7 of the sar is set (to 1), the tap selector sets the series resistor string voltage tap to 225 512 av ref1 ( = 1/2 av ref1 ). (e) the voltage difference between the series resistor string voltage tap and the analog input is determined by the voltage comparator. if the analog input is greater than (1/2) av ref1 , the msb of the sar remains set (to 1), and if it is less than (1/2) av ref1 , the msb is cleared (to 0). (f) next, bit 6 of the sar is set (to 1) automatically, and the next comparison is performed. here, the series resistor string voltage tap is selected according to the value of bit 7 for which the result has already been set, as shown below. bit 7 = 1 ........ 383 512 av ref1 = 3 4 av ref1 bit 7 = 0 ........ 127 512 av ref1 = 1 4 av ref1 this voltage tap is compared with the analog input voltage, and bit 6 of the sar is manipulated as follows according to the result: analog input voltage voltage tap: bit 6 = 1 analog input voltage < voltage tap: bit 6 = 0 (g) the same kind of comparison is continued up to the lsb (bit 0) of the sar (binary search method). chapter 14 a/d converter 393 user s manual u11316ej4v1ud (h) when comparison of the 8 bits is completed, a valid digital result is left in the sar, and that value is transferred to the a/d conversion result register (adcr) and latched. an a/d conversion operation end interrupt request (intad) can be generated at the same time. figure 14-4 basic a/d converter operation 80h c0h or 40h conversion result conversion result undefined conversion time sampling time a/d converter operation sar adcr intad a/d conversion sampling a/d conversion operations are performed successively until the cs bit is cleared (to 0) by software. if a write operation is performed on the adm during an a/d conversion operation, the conversion operation is initialized, and if the cs bit is set (to 1), conversion will be started from the beginning. the contents of the adcr are undefined after reset input. chapter 14 a/d converter 394 user s manual u11316ej4v1ud (2) input voltage and conversion result the relationship between the analog input voltage input to an analog input pin (ani0 to ani7) and the a/d conversion result (value stored in adcr) is shown by the following expression: adcr = int ( v av in ref1 256 + 0.5) or (adcr 0.5) av ref1 256 v in < (adcr + 0.5) av ref1 256 remark int( ) : function that returns the integer part of the value in ( ) v in : analog input voltage av ref1 : av ref1 pin voltage adcr : adcr value figure 14-5 shows the relationship between the analog input voltage and the a/d conversion result in graphic form. figure 14-5 relationship between analog input voltage and a/d conversion result 255 254 253 3 2 1 0 input voltage/av ref1 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 a/d conversion result (adcr) chapter 14 a/d converter 395 user s manual u11316ej4v1ud (3) a/d conversion time the a/d conversion time is determined by the system clock frequency (f clk ) and the fr bit of the a/d converter mode register (adm). the a/d conversion time includes the entire time required for one a/d conversion operation, and the sampling time is also included in the a/d conversion time. these values are shown in table 14-2. table 14-1 a/d conversion time system clock (f clk ) range fr bit conversion time sampling time 0.25 mhz f clk 16 mhz 0 180/f clk 36/f clk (11.25 s to 90 s) (2.25 s to 18 s) 0.25 mhz f clk 16 mhz 1 120/f clk 24/f clk (7.5 s to 60 s) (1.5 s to 12 s) (4) a/d converter operating modes there are two a/d converter operating modes, scan mode and select mode. these modes are selected according to the setting of bit 0 (ms) of the a/d converter mode register (adm). in addition, scan mode 0 or 1 can be selected by bit 5 (scmd) of the adm. operation in either mode continues until the adm is rewritten. chapter 14 a/d converter 396 user s manual u11316ej4v1ud 14.3.2 select mode one analog input is specified by bits 1 to 3 (anis0 to anis2) of the a/d converter mode register (adm), and a/d conversion of the specified analog input pin is started. the conversion result is stored in the a/d conversion result register (adcr). an a/d conversion end interrupt request (intad) is generated at the end of each conversion operation. figure 14-6 select mode operation timing (a) trg bit 0 ani3 ani3 ani3 ani3 ani3 ani3 ani3 ani3 ani3 ani3 ani3 conversion start ( adcr a/d conversion intad ( cs 1 ms 1 anis2 to anis0 011 (b) trg bit 1 conversion end conversion end conversion end conversion end conversion end conversion start ( ( ani0 a/d conversion ani0 ani0 initialization initialization initialization intp5 ani0 ani0 ani0 ani0 ani0 ani0 ani0 ani0 adcr intad cs 1 ms 1 anis2 to anis0 000 chapter 14 a/d converter 397 user? manual u11316ej4v1ud 14.3.3 scan mode two scan modes, 1 and 0, are available. in scan mode 0, delay control that takes delay in reading the a/d conversion result by the cpu into consideration can be performed. in scan mode 1, no delay control is performed but the a/d conversion interval is fixed. generally, use of scan mode 1 is recommended. (1) scan mode 0 (bit 5 (scmd) of a/d converter mode register (adm) = 0) input from the analog input pins specified by bits 1 to 3 (anis0 to anis2) of the adm is selected and converted in order. for example, if anis2 to anis0 of the adm = 001, ani0 and ani1 will be scanned repeatedly (ani0 ani1 ani0 ani1 ...). in the scan mode, at the end of the conversion operation for each input the conversion value is stored in the a/d conversion result register (adcr) and an a/d conversion end interrupt request (intad) is generated. figure 14-7 scan mode 0 operation timing (a) trg bit 0 ani0 ani0 ani1 ani0 ani1 ani0 ani1 conversion end conversion end conversion end conversion end conversion end conversion end ani1 ani0 ani1 ani0 conversion start ( adcr a/d conversion intad ( cs 1 ms 0 anis2 to anis0 001 (b) trg bit 1 ani0 ani1 ani0 a/d conversion ani2 ani0 ani1 ani0 initialization initialization initialization initialization ani0 ani1 adcr ani0 conversion end conversion end conversion end conversion end conversion start ( ( intad intp5 cs 1 ms 0 anis2 to anis0 010 chapter 14 a/d converter 398 user s manual u11316ej4v1ud (2) scan mode 1 (bit 5 (scmd) of a/d converter mode register (adm) = 1) when bit 5 of the adm is set (to 1), the analog input pins specified by bits 1 to 3 (anis0 to anis2) are selected, and subjected to conversion, in order. if an a/d conversion result register (adcr) read is not performed by the cpu by the end of the next a/d conversion after a/d conversion end (intad) generation, conversion is restarted without performing intad generation, adcr updating or channel updating (see figure 14-8 ). if an adcr read is performed by the cpu before the end of the next a/d conversion, the same operation as in scan mode 0 is performed. figure 14-8 scan mode 1 operation timing ani1 a/d conversion ani2 ani2 ani3 ani0 ani0 ani0 adcr ani1 ani2 ani3 intad adcr read channel updating disabled adcr updating disabled interrupt generation disabled chapter 14 a/d converter 399 user s manual u11316ej4v1ud 14.3.4 a/d conversion operation start by software an a/d conversion operation start by software is performed by writing a value to the a/d converter mode register (adm) that sets the trg bit of the adm register to 0 and the cs bit to 1. if a value is written to the adm during an a/d conversion operation (cs bit = 1) such that the trg bit is set to 0 and the cs bit to 1 again, the a/d conversion operation being performed at that time is suspended, and a/d conversion is started immediately in accordance with the written value. once a/d conversion operation is started, as soon as one a/d conversion operation ends the next a/d conversion operation is started in accordance with the operating mode set by the adm, and conversion operations continue repeatedly until an instruction that writes to the adm is executed. when a/d conversion operation is started by software (trg bit = 0), intp5 pin (p26 pin) input does not affect the a/ d conversion operation. (1) select mode a/d conversion operation an a/d conversion operation is started on the analog input pin set by the a/d converter mode register (adm). as soon as the a/d conversion operation ends, another a/d conversion operation is performed on the same analog input pin. an a/d conversion end interrupt request (intad) is generated at the end of each a/d conversion operation. figure 14-9 software start select mode a/d conversion operation anin a/d conversion anin anim anim anim anin anin anin anim anim adm rewrite cs 1, trg 0 conversion start cs 1, trg 0 adcr intad remark n = 0, 1, , 7 m = 0, 1, , 7 chapter 14 a/d converter 400 user s manual u11316ej4v1ud (2) scan mode a/d conversion operation when conversion operation is started, an a/d conversion operation is started on the ani0 pin input. when the a/d conversion operation ends, an a/d conversion operation is started on the next analog input pin. an a/d conversion end interrupt request (intad) is generated at the end of each a/d conversion operation. figure 14-10 software start scan mode a/d conversion operation adm rewrite cs 1 trg 0 interrupt request acknowledgment ani0 ani1 ani2 ani0 ani1 ani2 ani0 ani1 ani0 ani0 ani1 ani2 ani0 ani1 ani2 ani0 conversion start cs 1 trg 0 a/d conversion (ani0 to ani2 scanned) adcr intad chapter 14 a/d converter 401 user s manual u11316ej4v1ud 14.3.5 a/d conversion operation start by hardware an a/d conversion operation start by hardware is made possible by setting both the trg bit and the cs bit of the a/d converter mode register (adm) to 1. when the trg bit and the cs bit of the adm are both set to 1, external signals are placed in the standby state, and an a/d conversion operation is started when a valid edge is input to the intp5 pin (p26 pin). if another valid edge is input to the intp5 pin after the a/d conversion operation has been started by a valid edge input to the intp5 pin, the a/d conversion operation being performed at that time is suspended, and a/d conversion is performed from the beginning in accordance with the contents set in the adm. if a value is written to the adm during an a/d conversion operation (cs bit = 1) such that the trg bit and cs bit are both set to 1 again, the a/d conversion operation being performed at that time is suspended (the standby state is also suspended), and a standby state is entered in which the a/d converter waits for input of a valid edge to the intp5 pin in the a/d conversion operation mode in accordance with the written value, and a conversion operation is started when a valid edge is input. use of this function allows a/d conversion operations to be synchronized with external signals. once a/d conversion operation is started, as soon as one a/d conversion operation ends the next a/d conversion operation is started in accordance with the operating mode set by the adm (the a/d converter does not wait for intp5 pin input), and conversion operations continue repeatedly until an instruction that writes to the adm is executed, or a valid edge is input to the intp5 pin. caution approximately 10 s is required from the time a valid edge is input to the intp5 pin until the a/d conversion operation is actually started. this delay must be taken into account in the design stage. see chapter 21 edge detection function for details of the edge detection function. chapter 14 a/d converter 402 user s manual u11316ej4v1ud (1) select mode a/d conversion operation an a/d conversion operation is started on the analog input pin set by the a/d converter mode register (adm). as soon as the a/d conversion operation ends, another a/d conversion operation is performed on the same analog input pin. an a/d conversion end interrupt request (intad) is generated at the end of each a/d conversion operation. if a valid edge is input to the intp5 pin during an a/d conversion operation, the a/d conversion operation being performed at that time is suspended, and a new a/d conversion operation is started. figure 14-11 hardware start select mode a/d conversion operation standby state anin anin anin anin anin anim anim standby state anin anin anin anim adm rewrite cs 1, trg 1 adm rewrite cs 1, trg 1 intad acknowledgment adcr intad a/d conversion intp5 pin input (rising edge valid) remark n = 0, 1, , 7 m = 0, 1, , 7 (2) scan mode a/d conversion operation when conversion operation is started, an a/d conversion operation is started on the ani0 pin input. when the a/d conversion operation ends, an a/d conversion operation is started on the next analog input pin. an a/d conversion end interrupt request (intad) is generated at the end of each a/d conversion operation. if a valid edge is input to the intp5 pin during an a/d conversion operation, the a/d conversion operation being performed at that time is suspended, and a new a/d conversion operation is started on the ani0 pin input. chapter 14 a/d converter 403 user? manual u11316ej4v1ud figure 14-12 hardware start scan mode a/d conversion operation standby state ani0 ani1 ani2 ani0 ani0 ani0 ani1 ani2 standby state ani0 ani1 ani2 ani0 ani1 ani0 ani1 ani2 ani0 ani0 ani1 ani0 ani1 ani2 adm rewrite cs 1, trg 1 adm rewrite cs 1, trg 1 a/d conversion (ani0 to anii2 scanned) adcr intad intp5 pin input (rising edge valid) intad acknowledgment chapter 14 a/d converter 404 user s manual u11316ej4v1ud 14.4 external circuit of a/d converter the a/d converter is provided with a sample & hold circuit to stabilize its conversion operation. this sample & hold circuit outputs sampling noise during sampling immediately after an a/d conversion channel has been changed. to absorb this sampling noise, an external capacitor must be connected. if the impedance of the signal source is high, an error may occur in the conversion result due to the sampling noise. especially when the scan mode is used, the impedance of the signal source must be kept low because the channel whose signal is to be converted changes one after another. one way to absorb the sampling noise is to increase the capacitance of the capacitor. however, if the capacitance is increased too much, the sampling noise is accumulated. therefore, the most effective way is to reduce the resistance component. 14.5 cautions (1) range of voltages applied to analog input pins the following must be noted concerning a/d converter analog input pins ani0 to ani7 (p70 to p77). a voltage outside the range av ss to av ref1 should not be applied to pins subject to a/d conversion during an a/ d conversion operation. if this restriction is not observed, the pd784038 may be damaged. (2) hardware start a/d conversion approximately 10 s is required from the time a valid edge is input to the intp5 pin until the a/d conversion operation is actually started. this delay must be taken into account in the design stage. see chapter 21 edge detection function for details of the edge detection function. (3) connecting capacitor to analog input pins a capacitor should be connected between the analog input pins (ani0 to ani7) and avss and between the reference voltage input pin (av ref1 ) and av ss to prevent malfunction due to noise. chapter 14 a/d converter 405 user s manual u11316ej4v1ud figure 14-13 example of capacitor connection on a/d converter pins analog input reference voltage input 100 to 500 pf ani0 to ani7 av ref1 av ss pd784038 (4) when the stop mode or idle mode is used, the power consumption should be reduced by clearing (to 0) the cs bit before entering the stop or idle mode. if the cs bit remains set (to 1), the conversion operation will be stopped by entering the stop or idle mode, but the power supply to the voltage comparator will not be stopped, and therefore the a/d converter power consumption will not be reduced. (5) once the a/d converter starts operating, conversion operations are performed repeatedly until the cs bit of the a/d converter mode (adm) is cleared (to 0). therefore, a superfluous interrupt may be generated if adm setting is performed after interrupt-related registers, etc., are set when a/d converter mode conversion, etc., is performed. the result of this superfluous interrupt is that the conversion result storage address appears to have been shifted when the scan mode is used. also, when the select mode is used, the first conversion result appears to have been an abnormal value, such as the conversion result for the other channel. it is therefore recommended that a/d converter mode conversion be carried out using the following procedure. <1> write to the adm (cs bit must be set (to 1)) <2> interrupt request flag (adif) clearance (to 0) <3> interrupt mask flag or interrupt service mode flag setting operations <1> to <3> should not be divided by an interrupt or macro service. when scan mode 0 (no delay control) is used, in particular, you should ensure that the time between <1> and <2> is less than the time taken by one a/d conversion operation. alternatively, the following procedure is recommended. <1> stop the a/d conversion operation by clearing (to 0) the cs bit of the adm. <2> interrupt request flag (adif) clearance (to 0). <3> interrupt mask flag or interrupt service mode flag setting <4> write to the adm 406 user? manual u11316ej4v1ud chapter 15 d/a converter the pd784038 incorporates an 8-bit resolution voltage output type digital/analog (d/a) converter, which uses the r- 2r resistor ladder type. 15.1 configuration the d/a converter block diagram is shown in figure 15-1. figure 15-1 d/a converter block diagram selector av ref2 av ref3 anon r r r 2r 2r 2r 2r dacsn dacen internal bus remark n = 0, 1 chapter 15 d/a converter 407 user s manual u11316ej4v1ud d/a conversion value setting registers (dacs0, dacs1) these registers are used to set the voltage values to be output to the anon pins (n = 0, 1). the voltage value output to the anon pin is given by the following expression: anon = av av ref ref 23 256 dacsn + av ref3 [v] reset input initializes these registers to 00h. 15.2 d/a converter mode register (dam) dam is an 8-bit register that controls d/a converter operations. the dam register can be read or written to with an 8- bit manipulation instruction or bit manipulation instruction. dma format is shown in figure 15-2. reset input sets the dam register to 03h, enabling d/a conversion output for both channels. figure 15-2 d/a converter mode register (dam) format 7 0 dam 6 0 5 0 4 0 3 0 2 0 1 dace1 0 dace0 address after reset r/w r/w 03h 0ff62h dace1 standby mode ano0 & ano1 pins both output high impedance ano0 pin output enabled ano1 pin output high impedance ano0 pin output high impedance ano1 pin output enabled ano0 & ano1 pins both output enabled d/a converter operation 0 0 dace0 1 0 10 11 chapter 15 d/a converter 408 user? manual u11316ej4v1ud 15.3 d/a converter operation 15.3.1 basic operation when the value to be output is written to the d/a conversion value setting register (dacsn, n = 0, 1) while the d/a conversion enable bit (dacen, n = 0, 1) of the d/a converter mode register (dam) is set (to 1), an analog voltage corresponding to the value written is output from the anon pin (n = 0, 1). the output voltage is retained until the next value is written to the dacsn. the voltage output from the anon pin is determined by the following expression: anon = av av ref ref 23 256 dacsn + av ref3 [v] while the reset input is low, anon is in the output high impedance state, and the dacsn is initialized to 00h. after reset release, the same level as the avref3 pin is output from the anon pin. connect capacitors between the reference voltage input pins (av ref2 and av ref3 ) and av ss to stabilize the operation of the d/a converter. figure 15-3 example of connecting capacitors to reference voltage input pins of d/a converter av ref2 av ref3 c1 c1 = c2 = 100 to 500 p f c2 av ss 15.3.2 d/a converter standby operation when the d/a conversion enable bit (dacen, n = 0, 1) of the d/a converter mode register (dam) is cleared (to 0), the anon pin (n = 0, 1) is set to the output high impedance state. when both dacen bits are cleared (to 0), the d/a converter enters standby mode, enabling the power consumption to be reduced. clear both dacen bits (to 0) when it is especially required to reduce the power consumption such as in stop mode. chapter 15 d/a converter 409 user s manual u11316ej4v1ud 15.4 cautions (1) as the d/a converter output impedance is high, a current cannot be taken from the anon pin (n = 0, 1). if the load input impedance is low, a buffer amplifier should be inserted between the load and the anon pin. also, the wiring to the buffer amp and load should be kept as short as possible (since the output impedance is high). if the wiring is long, measures such as enclosure with a ground pattern should be taken. (2) as the d/a converter output voltage varies in steps, the signal output by the d/a converter should generally be passed through a low-pass filter before use. (3) the d/a converter incorporated in the pd784038 is in the output high impedance state while reset is low. the design should therefore make provision for high impedance input in the load side circuitry. figure 15-4 example of buffer amp insertion (a) inverting amp pd784038 anon r 1 c r 2 + buffer amplifier input impedance = r 1 (b) voltage follower pd784038 anon r 1 c + buffer amplifier input impedance = r 1 if r 1 were omitted, the output would be undefined when reset is low. r (4) since the d/a converter output is at the same level as the av ref3 pin after reset release, the design should allow for av ref3 pin level output after reset release. 410 user? manual u11316ej4v1ud chapter 16 outline of serial interface the pd784038 subseries is provided with three independent serial interface channels. therefore, communication with an external system and local communication within the system can be simultaneously executed by using these three channels. asynchronous serial interface (uart)/3-wire serial i/o (ioe) 2 channels refer to chapter 17 . clocked serial interface (csi) 1 channel 3-wire serial i/o mode (msb/lsb first) refer to chapter 18 . 2-wire serial i/o mode (msb first) refer to chapter 18 . ? 2 c bus mode (msb first) ( pd784038y subseries only) refer to chapter 19 . chapter 16 outline of serial interface 411 user? manual u11316ej4v1ud figure 16-1 shows an example of the serial interface. figure 16-1 example of serial interface (1) uart + i 2 c rs-232-c driver/ receiver rs-232-c driver/ receiver [uart] [uart] rxd txd port rxd2 txd2 port sda scl [i 2 c] sda scl eeprom tm sda scl microcontroller (slave) lcd v dd v dd pd784038y (master) (2) uart + 3-wire serial i/o + 2-wire serial i/o rs-232-c driver/ receiver [uart] rxd txd port so1 si1 sck1 intpm port sda scl intpn port pd784038 (master) note note v dd v dd [2-wire serial i/o] si so sck port int sb0 port int sck0 microcontroller (slave) microcontroller (slave) [3-wire serial i/o] note handshake line 412 user? manual u11316ej4v1ud chapter 17 asynchronous serial interface/3-wire serial i/o the pd784038 incorporates two serial interface channels for which asynchronous serial interface (uart) mode or 3-wire serial i/o (ioe) mode can be selected. the two uart/ioe channels have completely identical functions. in this chapter, therefore, unless stated otherwise, uart/ioe1 will be described as representative of both uart/ioes. when used as uart2/ioe2, the uart/ioe1 register names, bit names and pin names should be read as their uart2/ioe2 equivalents as shown in table 17-1. table 17-1 differences between uart/ioe1 and uart2/ioe2 names item uart/ioe1 uart2/ioe2 pin names p25/asck/sck1, p30/rxd/si1, p12/asck2/sck2, p13/rxd2/si2, p31/txd/so1 p14/txd2/so2 asynchronous serial interface mode register asim asim2 asynchronous serial interface mode register bit names txe, rxe, ps1, ps0, cl, sl, txe2, rxe2, ps21, ps20, cl2, isrm, sck sl2, isrm2, sck2 asynchronous serial interface status register asis asis2 asynchronous serial interface status register bit names pe, fe, ove pe2, fe2, ove2 clocked serial interface mode register csim1 csim2 clocked serial interface mode register bit names ctxe1, crxe1, dir1, csck1 ctxe2, crxe2, dir2, csck2 baud rate generator control register brgc brgc2 baud rate generator control register bit names tps0 to tps3, mdl0 to mdl3 tps20 to tps23, mdl20 to mdl23 interrupt request names intsr/itcsi1, intser, intst intsr2/intcsi2, intser2, intst2 interrupt control registers and bit names used in this sric, csiic1, seric, stic, sric2, csiic2, seric2, stic2, chapter srif, csiif1, serif, stif srif2, csiif2, serif2, stif2 chapter 17 asynchronous serial interface/3-wire serial i/o 413 user? manual u11316ej4v1ud 17.1 switching between asynchronous serial interface mode and 3-wire serial i/o mode the asynchronous serial interface mode and 3-wire serial i/o mode cannot be used simultaneously. switching between these modes is performed in accordance with the settings of the asynchronous serial interface mode register (asim/asim2) and the clocked serial interface mode register (csim1/csim2) as shown in figure 17-1. figure 17-1 switching between asynchronous serial interface mode and 3-wire serial i/o mode 7 txe asim 6 rxe 5 ps1 4 ps0 3 cl 2 sl 1 isrm 0 sck txe2 rxe2 ps21 ps20 cl2 sl2 isrm2 sck2 asynchronous serial interface mode operation specification (see figure 17-3 ) after reset address address r/w r/w 00h 0ff88h asim2 r/w 00h 0ff89h txe txe2 rxe rxe2 ctxe1 ctxe2 crxe1 crxe2 operating mode setting prohibited other than the above operation-stopped mode 3-wire serial i/o mode asynchronous serial interface mode 0 0 0 0 00 00 0 0 1 1 1 0 0 1 01 10 11 0 0 0 0 0 0 7 ctxe1 csim1 6 crxe1 5 0 4 0 3 0 2 dir1 1 csck1 0 0 ctxe2 crxe2 0 0 0 dir2 csck2 0 after reset r/w r/w 00h 0ff84h csim2 r/w 00h 0ff85h 3-wire serial i/o mode operation specification (see figure 17-11 ) chapter 17 asynchronous serial interface/3-wire serial i/o 414 user s manual u11316ej4v1ud 17.2 asynchronous serial interface mode a uart (universal asynchronous receiver transmitter) is incorporated as the asynchronous serial interface. with this method, one byte of data is transmitted following a start bit, and full-duplex operation is possible. a baud rate generator is incorporated, enabling communication to be performed at any of a wide range of baud rates. also, the baud rate can be defined by scaling the clock input to the asck pin. 17.2.1 configuration in asynchronous serial interface mode the block diagram of the asynchronous serial interface is described in figure 17-2. see 17.4 baud rate generator for details of the baud rate generator. chapter 17 asynchronous serial interface/3-wire serial i/o 415 user s manual u11316ej4v1ud figure 17-2 asynchronous serial interface block diagram internal bus 1/8 1/8 receive buffer shift register reception control parity check fe fe2 pe pe2 ove ove2 reset asis, asis2 txe txe2 rxe rxe2 ps21 ps0 ps20 cl cl2 sl sl2 isrm isrm2 sck sck2 rxb, rxb2 p30/r x d, p13/r x d2 p31/t x d p14/t x d transmit shift register transmission control parity addition intser, intser2 intst, txs txs2 intst2 1 m intsr, intsr2 1 m 1 2 n selector p25/asck, p12/asck2 f xx /2 baud rate generator reset asim, asim2 1/8 ps1 chapter 17 asynchronous serial interface/3-wire serial i/o 416 user s manual u11316ej4v1ud (1) receive buffer (rxb/rxb2) this is the register that holds the receive data. each time one byte of data is received, the receive data is transferred from the shift register. if a 7-bit data length is specified, receive data is transferred to bits 0 to 6 of rxb/rxb2, and the msb of rxb/rxb2 is always 0 . rxb/rxb2 can be read only with an 8-bit manipulation instruction. the contents of rxb/rxb2 are undefined after reset input. (2) transmit shift register (txs/txs2) this is the register in which the data to be transmitted is set. data written to the txs/txs2 is transmitted as serial data. if a 7-bit data length is specified, bits 0 to 6 of the data written in the txs/txs2 are treated as transmit data. a transmit operation starts when a write to the txs/txs2 is performed. the txs/txs2 cannot be written to during a transmit operation. txs/txs2 can be written to only with an 8-bit manipulation instruction. the contents of txs/txs2 are undefined after reset input. (3) shift register this is the shift register that converts the serial data input to the rxd pin to parallel data. when one byte of data is received, the receive data is transferred to the receive buffer. the shift register cannot be manipulated directly by the cpu. (4) reception control parity check receive operations are controlled in accordance with the contents set in the asynchronous serial interface mode register (asim/asim2). in addition, parity error and other error checks are performed during receive operations, and if an error is detected, a value is set in the asynchronous serial interface status register (asis/asis2) according to the type of error. (5) transmission control parity addition transmission operation is controlled by appending a start bit, parity bit, and stop bit to the data written to the transmit shift registers (txs and txs2) in accordance with the contents set to the asynchronous serial interface mode registers (asim and asim2). (6) selector selects the baud rate clock source. chapter 17 asynchronous serial interface/3-wire serial i/o 417 user s manual u11316ej4v1ud 17.2.2 asynchronous serial interface control registers (1) asynchronous serial interface mode register (asim), asynchronous serial interface mode register 2 (asim2) the asim and asim2 are 8-bit registers that specify the uart mode operation. these registers can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the format of asim and asim is shown in figure 17-3. reset input clears these registers to 00h. chapter 17 asynchronous serial interface/3-wire serial i/o 418 user s manual u11316ej4v1ud figure 17-3 format of asynchronous serial interface mode register (asim) and asynchronous serial interface mode register 2 (asim2) 7 txe asim 6 rxe 5 ps1 4 ps0 3 cl 2 sl 1 isrm 0 sck txe2 rxe2 ps21 ps20 cl2 sl2 isrm2 sck2 after reset address r/w r/w 00h 0ff88h asim2 r/w 00h 0ff89h sck sck2 specification of input clock to baud rate generator external clock input (asck, asck2) 0 internal clock (fxx/2) 1 cl cl2 data character length specification 7 bits 8 bits sl sl2 stop bit length specification (transmission only) 1 bit 0 2 bits 1 0 1 ps0 ps20 parity bit specification no parity transmission = 0 parity addition reception = parity error not generated odd parity 0 1 ps1 ps21 0 01 0 even parity 11 isrm isrm2 specification of enabling/disabling of reception completion interrupt generation in case of receive error note enabled 0 disabled 1 txe txe2 transmit/receive operation transmission/reception disabled, or 3-wire serial i/o mode transmission enabled reception enabled 0 1 rxe rxe2 0 01 0 transmission/reception enabled 11 chapter 17 asynchronous serial interface/3-wire serial i/o 419 user s manual u11316ej4v1ud note to disable the reception completion interrupt on occurrence of a reception error, insert wait cycles of two clocks that serve as the reference of the baud rate clock after occurrence of the reception error and before the receive buffers (rxb and rxb2) are read. otherwise, the reception completion interrupt occurs even through the interrupt is disabled. the time equivalent to the above two clocks can be calculated by the following expression; wait time = 2 n + 3 f xx remark f xx : oscillation frequency n: value of n when 12-bit prescaler is selected by baud rate generator control register (brgc, brgc2) (n = 0 to 11). caution an asynchronous serial interface mode register (asim/asim2) rewrite should not be performed during a transmit operation. if an asim/asim2 register rewrite is performed during a transmit operation, subsequent transmit operations may not be possible (normal operation is restored by reset input). software can determine whether transmission is in progress by using a transmission completion interrupt (intst/intst2) or the interrupt request flag (stif/stif2) set by intst/intst2. chapter 17 asynchronous serial interface/3-wire serial i/o 420 user s manual u11316ej4v1ud (2) asynchronous serial interface status register (asis) asynchronous serial interface status register 2 (asis2) the asis and asis2 contain flags that indicate the error contents when a receive error occurs. flags are set (to 1) when a receive error occurs, and cleared (to 0) when data is read from the receive buffer (rxb/rxb2). if the next data is received before rxb/rxb2 is read, the overrun error flag (ove/ove2) is set (to 1), and the other error flags are cleared (to 0) (if there is an error in the next data, the corresponding error flag is set (to 1)). these registers can be read only with an 8-bit manipulation instruction or bit manipulation instruction. the format of asis and asis2 is shown in figure 17-4. reset input clears these registers to 00h. figure 17-4 format of asynchronous serial interface status register (asis) and asynchronous serial interface status register 2 (asis2) 7 0 asis 6 0 5 0 4 0 3 0 2 pe 1 fe 0 ove 0 0 0 0 0 pe2 fe2 ove2 after reset address r/w r 00h 0ff8ah asis2 r overrun error flag 00h 0ff8bh next receive completed before data is read from receive buffer 1 parity error flag transmit data parity specification and receive data parity do not match 1 framing error flag stop bit not detected 1 cautions 1. the receive buffer (rxb/rxb2) must be read even if there is a receive error. if rxb/rxb2 is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. 2. to disable the reception completion interrupt on occurrence of a reception error, insert wait cycles of two clocks that serve as the reference of the baud rate clock after occurrence of the reception error and before the receive buffers (rxb and rxb2) are read. otherwise, the reception completion interrupt occurs even through the interrupt is disabled. the time equivalent to the above two clocks can be calculated by the following expression; wait time = 2 n + 3 f xx remark f xx : oscillation frequency n: value of n when 12-bit prescaler is selected by baud rate generator control register (brgc, brgc2) (n = 0 to 11). chapter 17 asynchronous serial interface/3-wire serial i/o 421 user s manual u11316ej4v1ud 17.2.3 data format serial data transmission/reception is performed in full-duplex asynchronous mode. the transmit/receive data format is shown in figure 17-5. one data frame is made up of a start bit, character bits, parity bit, and stop bit(s). character bit length specification, parity selection and stop bit length specification for one data frame are performed by means of the asynchronous serial interface mode register (asim). figure 17-5 asynchronous serial interface transmit/receive data format 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit(s) start bit 1 bit character bits 7 bits/8 bits parity bit even parity/odd parity/0 parity/no parity stop bit s 1 bit/2 bits the serial transfer rate is selected in accordance with the asynchronous serial interface mode register and baud rate generator settings. if a serial data receive error occurs, the nature of the receive error can be determined by reading the asynchronous serial interface status register (asis) status. chapter 17 asynchronous serial interface/3-wire serial i/o 422 user s manual u11316ej4v1ud 17.2.4 parity types and operations the parity bit is used to detect a bit error in the communication data. normally, the same kind of parity bit is used on the transmission side and the reception side. with even parity and odd parity, 1 bit (odd number) errors can be detected. with 0 parity and no parity, errors cannot be detected. even parity if the number of bits with a value of 1 in the transmit data is odd, the parity bit is set to 1 , and if the number of 1 bits is even, the parity bit is set to 0 . control is thus performed to make the number of 1 bits in the transmit data plus the parity bit an even number. in reception, the number of 1 bits in the receive data plus the parity bit is counted, and if this number is odd, a parity error is generated. odd parity conversely to the case of even parity, control is performed to make the number of 1 bits in the transmit data plus the parity bit an odd number. in reception, a parity error is generated if the number of 1 bits in the receive data plus the parity bit is even. 0 parity in transmission, the parity bit is set to 0 irrespective of the receive data. in reception, parity bit detection is not performed. therefore, no parity error is generated irrespective of whether the parity bit is 0 or 1 . no parity in transmission, a parity bit is not added. in reception, reception is performed on the assumption that there is no parity bit. since there is no parity bit, no parity error is generated. chapter 17 asynchronous serial interface/3-wire serial i/o 423 user s manual u11316ej4v1ud 17.2.5 transmission the pd784038 s asynchronous serial interface is set to the transmission enabled state when the txe bit of the asynchronous serial interface mode register (asim) is set (to 1). a transmit operation is started by writing transmit data to the transmit shift register (txs) when transmission is enabled. the start bit, parity bit and stop bit(s) are added automatically. when a transmit operation is started, the data in the txs is shifted out, and a transmission completion interrupt (intst) is generated when the txs is empty. if no more data is written to the txs, the transmit operation is discontinued. if the txe bit is cleared (to 0) during a transmit operation, the transmit operation is discontinued immediately. figure 17-6 asynchronous serial interface transmission completion interrupt timing (a) stop bit length: 1 stop parity d0 start txd (output) intst d1 d2 d6 d7 (b) stop bit length: 2 parity d0 start txd (output) intst d1 d2 d6 d7 stop cautions 1. after reset input the transmit shift register (txs) is emptied but a transmission completion interrupt is not generated. a transmit operation can be started by writing transmit data to the txs. 2. an asynchronous serial interface mode register (asim) rewrite should not be performed during a transmit operation. if an asim rewrite is performed during a transmit operation, subsequent transmit operations may not be possible (normal operation is restored by reset input). software can determine whether transmission is in progress by using a transmission completion interrupt (intst) or the interrupt request flag (stif) set by intst. chapter 17 asynchronous serial interface/3-wire serial i/o 424 user s manual u11316ej4v1ud 17.2.6 reception when the rxe bit of the asynchronous serial interface mode register (asim) is set (to 1), receive operations are enabled and sampling of the rxd input pin is performed. rxd input pin sampling is performed using the serial clock (divide-by-m counter input clock) specified by asim and band rate generator control register (brgc). when the rxd pin input is driven low, the divide-by-m counter starts counting and a data sampling start timing signal is output on the m'th count. if the rxd pin input is low when sampled again by this start timing signal, the input is recogniz ed as a start bit, the divide-by-m counter is initialized and the count is started, and data sampling is performed. when the character data, parity bit and stop bit are detected following the start bit, reception of one data frame ends. when reception of one data frame ends, the receive data in the shift register is transferred to the receive buffer, rxb, and a reception completion interrupt (intsr) is generated. if an error occurs, the receive data in which the error occurred is still transferred to rxb. if bit 1 (isrm) of the asim was cleared (to 0) when the error occurred, intsr is generated. if the isrm was set (to 1), intsr is not generated. if the rxe bit is cleared (to 0) during a receive operation, the receive operation is stopped immediately. in this case the contents of rxb and asis are not changed, and no intsr or intser interrupt is generated. figure 17-7 asynchronous serial interface reception completion interrupt timing stop parity d0 start rxd (input) intsr d1 d2 d6 d7 cautions 1. the receive buffer (rxb) must be read even if there is a receive error. if rxb is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. 2. to disable the reception completion interrupt on occurrence of a reception error, insert wait cycles of two clocks that serve as the reference of the baud rate clock after occurrence of the reception error and before the receive buffers (rxb and rxb2) are read. otherwise, the reception completion interrupt occurs even through the interrupt is disabled. the time equivalent to the above two clocks can be calculated by the following expression; wait time = 2 n + 3 f xx remark f xx : oscillation frequency n: value of n when 12-bit prescaler is selected by baud rate generator control register (brgc, brgc2) (n = 0 to 11). chapter 17 asynchronous serial interface/3-wire serial i/o 425 user s manual u11316ej4v1ud 17.2.7 receive errors three kinds of errors can occur in a receive operation: parity errors, framing errors and overrun errors. as the result of data reception, an error flag is raised in the asynchronous serial interface status register (asis) and a receive error interrupt (intser) is generated. receive error causes are shown in table 17-2. it is possible to detect the occurrence of any of the above errors during reception by reading the contents of the asis (see figures 17-4 and 17-8 ). the contents of the asis register are cleared (to 0) by reading the receive buffer (rxb) or by reception of the next data (if there is an error in the next data, the corresponding error flag is set). table 17-2 receive error causes receive error cause parity error transmit data parity specification and receive data parity do not match framing error stop bit not detected overrun error reception of next data completed before data is read from receive buffer figure 17-8 receive error timing stop parity d0 start rxd (input) intsr note d1 d2 d6 d7 intser note if a receive error occurs while the isrm bit is set (to 1), intsr is not generated. remark in the pd784038, a break signal cannot be detected by hardware. as a break signal is a low-level signal of two characters or more, a break signal may be judged to have been input if software detects the occurrence of two consecutive framing errors in which the receive data was 00h. the chance occurrence of two consecutive framing errors can be distinguished from a break signal by having the rxd pin level read by software (confirmation is possible by setting 1 in bit 0 of the port 3 mode register (pm3) and reading port 3 (p3)) and confirming that it is 0 . chapter 17 asynchronous serial interface/3-wire serial i/o 426 user s manual u11316ej4v1ud cautions 1. the contents of the asynchronous serial interface status register (asis) are cleared (to 0) by reading the receive buffer (rxb) or by reception of the next data. if you want to find the details of an error, therefore, asis must be read before reading rxb. 2. the rxb must be read even if there is a receive error. if rxb is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. 3. to disable the reception completion interrupt on occurrence of a reception error, insert wait cycles of two clocks that serve as the reference of the baud rate clock after occurrence of the reception error and before the receive buffers (rxb and rxb2) are read. otherwise, the reception completion interrupt occurs even through the interrupt is disabled. the time equivalent to the above two clocks can be calculated by the following expression; wait time = 2 n + 3 f xx remark f xx : oscillation frequency n: value of n when 12-bit prescaler is selected by baud rate generator control register (brgc, brgc2) (n = 0 to 11). chapter 17 asynchronous serial interface/3-wire serial i/o 427 user s manual u11316ej4v1ud 17.3 3-wire serial i/o mode the 3-wire serial i/o mode is used to communicate with devices that incorporate a conventional clocked serial interface. basically, communication is performed using three lines: the serial clock (sck), serial data output (so), and serial data input (si). generally, a handshake line is necessary for checking the communication status. figure 17-9 example of 3-wire serial i/o system configuration 3-wire serial i/o ? ? ? ? ? 3-wire serial i/o sck so si port (interrupt) port sck si so port interrupt (port) master cpu note slave cpu note handshaking lines 17.3.1 configuration in 3-wire serial i/o mode the block diagram in the 3-wire serial i/o mode is shown in figure 17-10. chapter 17 asynchronous serial interface/3-wire serial i/o 428 user s manual u11316ej4v1ud figure 17-10 3-wire serial i/o mode block diagram internal bus reset 8 dq shift register direction control circuit 8 serial clock counter interrupt signal generator intcsi1, intcsi2 p25/sck1, p12/sck2 serial clock control circuit selector baud rate generator p30/si1, p13/si2 p31/so1, p14/so2 csck1, csck2 csck1, csck2 so latch 8 csck2 dir2 crxe2 ctxe2 csck1 dir1 crxe1 ctxe1 chapter 17 asynchronous serial interface/3-wire serial i/o 429 user s manual u11316ej4v1ud (1) shift register (sio1/sio2) the sio1 and sio2 converts 8-bit serial data to 8-bit parallel data, and vice versa. sio1/sio2 is used for both transmission and reception. actual transmit/receive operations are controlled by writing to/reading from sio1/sio2. reading/writing can be performed with an 8-bit manipulation instruction. the contents of sio1/sio2 are undefined after reset input. (2) so latch the so latch holds the so1/so2 pin output level. (3) serial clock selector selects the serial clock to be used. (4) serial clock counter counts the serial clocks output or input in a transmit/receive operation, and checks that 8-bit data transmission/reception has been performed. (5) interrupt signal generator generates an interrupt request when 8 serial clocks have been counted by the serial clock counter. (6) serial clock control circuit controls the supply of the serial clock to the shift register, and also controls the clock output to the sck1/sck2 pins when the internal clock is used. (7) direction control circuit switches between msb-first and lsb-first modes. chapter 17 asynchronous serial interface/3-wire serial i/o 430 user s manual u11316ej4v1ud 17.3.2 clocked serial interface mode registers (csim1, csim2) the csim1 and csim2 are 8-bit registers that specify operations in the 3-wire serial i/o mode. these registers can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the csim1 and csim2 format is shown in figure 17-11. reset input clears these registers to 00h. figure 17-11 format of clocked serial interface mode register 1 (csim1) and clocked serial interface mode register 2 (csim2) 7 ctxe1 csim1 6 crxe1 5 0 4 0 3 0 2 dir1 1 csck1 0 0 ctxe2 crxe2 0 0 0 dir2 csck2 0 after reset address r/w r/w 00h 0ff84h csim2 r/w (n = 1, 2) 00h 0ff85h csckn serial clock selection bit source clock in case of sckn (ctxen, crxen = 1) external input clock to sckn pin input cmos output 0 baud rate generator output 1 dirn operating mode specification (transfer bit order) msb-first lsb-first 0 1 ctxen transmit/receive operation transmission /reception disabled, or asynchronous serial interface mode transmission enabled reception enabled 0 1 crxen 0 01 0 transmission/reception enabled 11 caution specify whether data is transferred with msb or lsb first before writing the sio. even if the specification is made after writing the iso, the byte order of the data already stored in the sio cannot be changed. chapter 17 asynchronous serial interface/3-wire serial i/o 431 user s manual u11316ej4v1ud 17.3.3 basic operation timing in the 3-wire serial i/o mode, data transmission/reception is performed in 8-bit units. data is transmitted/received bit by bit in msb-first or lsb-first order in synchronization with the serial clock. msb/lsb switching is specified by the dirn bit of the clock serial interface mode register (csimn). transmit data is output in synchronization with the fall of sckn, and receive data is sampled on the rise of sckn. an interrupt request (intcsin) is generated on the 8th rise of sckn. when the internal clock is used as sckn, sckn output is stopped on the 8th rise of sckn and sckn remains high until the next data transmit or receive operation is started. 3-wire serial i/o mode timing is shown in figure 17-12. figure 17-12 3-wire serial i/o mode timing (1/2) (a) msb-first intcsin di7 di6 di5 di4 di3 di2 di1 di0 sckn note sin (input) son (output) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 transfer end interrupt generation start of transfer synchronized with fall of sckn note master cpu: output slave cpu: input execution of instruction that writes to sion remark n = 1 or 2 chapter 17 asynchronous serial interface/3-wire serial i/o 432 user s manual u11316ej4v1ud figure 17-12 3-wire serial i/o mode timing (2/2) (b) lsb-first intcsin di0 di1 di2 di3 di4 di5 di6 di7 sckn note sin (input) son (output) 12345678 do0 do1 do2 do3 do4 do5 do6 do7 transfer end interrupt generation start of transfer synchronized with fall of sckn note master cpu: output slave cpu: input execution of instruction that writes to sion remark if the pd784038 is connected to a 2-wire serial i/o device, a buffer should be connected to the son pin as shown in figure 17-13. in the example shown in figure 17-13, the output level is inverted by the buffer, and therefore the inverse of the data to be output should be written to sion (n = 1 or 2). in addition, non-connection of the internal pull-up resistor should be specified for the p31/so1 or p14/so2 pin. figure 17-13 example of connection to 2-wire serial i/o pd784038 sckn sin son 2-wire serial i/o device sio sck chapter 17 asynchronous serial interface/3-wire serial i/o 433 user? manual u11316ej4v1ud 17.3.4 operation when transmission only is enabled a transmit operation is performed when the ctxen bit of clocked serial interface mode register (csimn) is set (to 1). the transmit operation starts when a write to the shift register (sion) is performed while the ctxen bit is set (to 1). when the ctxen bit is cleared (to 0), the son pin is in the output high level. (1) when the internal clock is selected as the serial clock when transmission starts, the serial clock is output from the sckn pin and data is output in sequence from sion to the son pin in synchronization with the fall of the serial clock, and sin pin signals are shifted into sion in synchronization with the rise of the serial clock. there is a delay of up to one sckn clock cycle between the start of transmission and the first fall of sckn. if transmission is disabled during the transmit operation (by clearing (to 0) the ctxen bit), sckn clock output is stopped and the transmit operation is discontinued on the next rise of sckn. in this case an interrupt request (intcsin) is not generated, and the son pin becomes output high level. (2) when an external clock is selected as the serial clock when transmission starts, data is output in sequence from sion to the son pin in synchronization with the fall of the serial clock input to the sckn pin after the start of transmission, and sin pin signals are shifted into sion in synchronization with the rise of the sckn pin input. if transmission has not started, shift operations are not performed and the son pin output level does not change even if the serial clock is input to the sckn pin. if transmission is disabled during the transmit operation (by clearing (to 0) the ctxen bit), the transmit operation is discontinued and subsequent sckn input is ignored. in this case an interrupt request (intcsin) is not generated, and the son pin becomes output high level. remark n = 1 or 2 17.3.5 operation when reception only is enabled a receive operation is performed when the crxen bit of the clocked serial interface mode register (csimn) is set (to 1). the receive operation starts when the crxen changes from ??to ?? or when a read from shift register (sion) is performed. (1) when the internal clock is selected as the serial clock when reception starts, the serial clock is output from the sckn pin and the sin pin data is fetched in sequence into shift register (sion) in synchronization with the rise of the serial clock. there is a delay of up to one sckn clock cycle between the start of reception and the first fall of sckn. if reception is disabled during the receive operation (by clearing (to 0) the crxen bit), sckn clock output is stopped and the receive operation is discontinued on the next rise of sckn. in this case an interrupt request (intcsin) is not generated, and the contents of the sion are undefined. (2) when an external clock is selected as the serial clock when reception starts, the sin pin data is fetched into shift register (sion) in synchronization with the rise of the serial clock input to the sckn pin after the start of reception. if reception has not started, shift operations are not performed even if the serial clock is input to the sckn pin. if reception is disabled during the receive operation (by clearing (to 0) the crxen bit), the receive operation is discontinued and subsequent sckn input is ignored. in this case an interrupt request (intcsin) is not generated. remark n = 1 or 2 chapter 17 asynchronous serial interface/3-wire serial i/o 434 user s manual u11316ej4v1ud 17.3.6 operation when transmission/reception is enabled when the ctxen bit and crxen bit of the clocked serial interface mode register (csimn) register are both set (to 1), a transmit operation and receive operation can be performed simultaneously (transmit/receive operation). the transmit/ receive operation is started when the crxen bit is changed from 0 to 1 , or by performing a write to shift register (sion). when a transmit/receive operation is started for the first time, the crxen bit always changes from 0 to 1 , and there is thus a possibility that the transmit/receive operation will start immediately, and undefined data will be output. the first transmit data should therefore be written to sion beforehand when both transmission and reception are disabled (when the ctxen bit and crxen bit are both cleared (to 0)), before enabling transmission/reception. however, specify whether data is transferred with msb or lsb first before writing the sion. even if the specification is made after writing the sion, the byte order of the data already stored in the sion cannot be changed. when transmission/reception is disabled (ctxen = crxen = 0), the son pin is in the output high level. (1) when the internal clock is selected as the serial clock when transmission/reception starts, the serial clock is output from the sckn pin, data is output in sequence from shift register (sion) to the (son) pin in synchronization with the fall of the serial clock, and sin pin data is shifted in order into sion in synchronization with the rise of the serial clock. there is a delay of up to one sckn clock cycle between the start of transmission and the first fall of sckn. if either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is discontinued. if transmission only is disabled, the son pin becomes output high level. if reception only is disabled, the contents of the sion will be undefined. if transmission and reception are disabled simultaneously, sckn clock output is stopped and the transmit and receive operations are discontinued on the next rise of sckn. when transmission and reception are disabled simultaneously, the contents of sion are undefined, an interrupt request (intcsin) is not generated, and the son pin becomes output high level. (2) when an external clock is selected as the serial clock when transmission/reception starts, data is output in sequence from shift register (sion) to the son pin in synchronization with the fall of the serial clock input to the sckn pin after the start of transmission/reception, and sin pin data is shifted in order into sion in synchronization with the rise of the serial clock. if transmission/reception has not started, the sion shift operations are not performed and the son pin output level does not change even if the serial clock is input to the sckn pin. if either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is discontinued. if transmission only is disabled, the son pin becomes output high level. if reception only is disabled, the contents of the sion will be undefined. if transmission and reception are disabled simultaneously, the transmit and receive operations are discontinued and subsequent sckn input is ignored. when transmission and reception are disabled simultaneously, the contents of sion are undefined, an interrupt request (intcsin) is not generated, and the son pin becomes output high level. remark n = 1 or 2 chapter 17 asynchronous serial interface/3-wire serial i/o 435 user s manual u11316ej4v1ud 17.3.7 corrective action in case of slippage of serial clock and shift operations when an external clock is selected as the serial clock, there may be slippage between the number of serial clocks and shift operations due to noise, etc. in this case, since the serial clock counter is initialized by disabling both transmit ope rations and receive operations (by clearing (to 0) the ctxen bit and crxen bit), synchronization of the shift operations and the serial clock can be restored by using the first serial clock input after reception or transmission is next enabled as the first clock. remark n = 1 or 2 17.4 baud rate generator the baud rate generator is the circuit that generates the uart/ioe serial clock. two independent circuits are incorporated, one for each serial interface. 17.4.1 baud rate generator configuration the baud rate generator block diagram is shown in figure 17-14. chapter 17 asynchronous serial interface/3-wire serial i/o 436 user s manual u11316ej4v1ud figure 17-14 baud rate generator block diagram internal bus 8 baud rate generator control register brgc, brgc2 reset asynchronous serial interface mode registers 1 & 2 asim1, asim2 1/8 sck clock serial interface mode registers 1 & 2 csim1, csim2 1/8 csck1 5-bit counter 5-bit counter reset start bit detection 1/2 uart reception shift clock clear match match 1/2 selector selector selector shift clock for uart transmission & ioe frequency divider selector f prs f xx /2 p25/asck/sck1, p12/asck2/sck2 brgc write csck1 start bit detection sampling clock reset chapter 17 asynchronous serial interface/3-wire serial i/o 437 user? manual u11316ej4v1ud (1) 5-bit counter counter that counts the clock (f prs ) by which the output from the frequency divider is selected. generates a signal with the frequency selected by the low-order 4 bits of the baud rate generator control registers (brgc/brgc2). (2) frequency divider scales the internal clock (f xx /2) or, in asynchronous serial interface mode, a clock that is twice the external baud rate input (asck/asck2), and selects fprs with the next-stage selector. (3) both-edge detection circuit detects both edges of the asck/asck2 pin input signal and generates a signal with a frequency twice that of the asck/ asck2 input clock. 17.4.2 baud rate generator control register (brgc, brgc2) the brgc and brgc2 are 8-bit registers that set the baud rate clock in asynchronous serial interface mode or the shift clock in 3-wire serial i/o mode. these registers can be read/written with an 8-bit manipulation instruction. the brgc and brgc2 format is shown in figure 17-15. reset input clears the brgc register to 00h. caution when a baud rate generator control register (brgc, brgc2) write instruction is executed, the 5-bit counter and 1/2 frequency divider operations are reset. consequently, if a write to the brgc and brgc2 is performed during communication, the generated baud rate clock may be disrupted, preventing normal communication from continuing. the brgc and brgc2 should therefore not be written to during communication. chapter 17 asynchronous serial interface/3-wire serial i/o 438 user s manual u11316ej4v1ud figure 17-15 baud rate generator control register (brgc) format and baud rate generator control register 2 (brgc2) format 7 tps3 brgc 6 tps2 5 tps1 4 tps0 3 mdl3 2 mdl2 1 mdl1 0 mdl0 tps23 tps22 tps21 tps20 mdl23 mdl22 mdl21 mdl20 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 f prs /16 f prs /17 f prs /18 f prs /19 f prs /20 f prs /21 f prs /22 f prs /23 f prs /24 f prs /25 f prs /26 f prs /27 f prs /28 f prs /29 f prs /30 f prs note 2 after reset address r/w r/w 00h 0ff90h brgc2 r/w k baud rate generator input clock note 1 f prs : prescaler output selection clock 00h 0ff91h mdl3 mdl2 mdl1 mdl0 mdl23 mdl22 mdl21 mdl20 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 10 11 f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, f xx /512, f xx /1,024, f xx /2,048, f xx /4,096, f xx /8,192, f asck /2 note f asck /4 f asck /8 f asck /16 f asck /32 f asck /64 f asck /128 f asck /256 f asck /512 f asck /1,024 f asck /2,048 f asck /4,096 n 12-bit prescaler tap selection (f prs ) other than the above setting prohibited f xx : oscillator frequency or external clock input tps3 tps2 tps1 tps0 tps23 tps22 tps21 tps20 notes 1. only f prs /16 can be selected when asck/asck2 input is used. 2. can only be used in 3-wire serial i/o mode. note can not be selected when the value set in bits mdl3 to mdl0 or mdl23 to mdl20, k = 15. chapter 17 asynchronous serial interface/3-wire serial i/o 439 user s manual u11316ej4v1ud 17.4.3 baud rate generator operation the baud rate generator only operates when uart/ioe transmit/receive operations are enabled. the generated baud rate clock is a signal scaled from the internal clock (f xx /2) or a signal scaled from the clock input from the external baud rate input (asck) pin. caution if a write to the baud rate generator control register (brgc) is performed during communication, the generated baud rate clock may be disrupted, preventing normal communication from continuing. the brgc should therefore not be written to during communication. (1) baud rate clock generation in uart mode (a) using internal clock (f xx /2) this function is selected by setting (to 1) bit 0 (sck) of the asynchronous serial interface mode register (asim). the internal clock (f xx /2) is scaled by the frequency divider, this signal (f prs ) is scaled by the 5-bit counter, and the signal further divided by 2 is used as the baud rate. the baud rate is given by the following expression: (baud rate) = f k xx n () +? + 16 2 3 f xx : oscillator frequency or external clock input k : value set in bits mdl3 to mdl0 of brgc (k = 0 to 14) n : value set in bits tps3 to tps0 of brgc (n = 0 to 11) (b) using external baud rate input this function is selected by clearing (to 0) bit 0 (sck) of the asynchronous serial interface mode register (asim). when this function is used, bits mdl3 to mdl0 of the baud rate generator control register (brgc) must all be cleared (to 0) (k = 0). when this function is used with uart2, it is necessary to set (to 1) bit 2 of the port 3 mode control register (pmc3) and set the p12 pin to control mode. the asck pin input clock is scaled by the frequency divider, and the signal obtained by dividing this signal by 32 (f prs ) (division by 16 and division by 2) is used as the baud rate. the baud rate is given by the following expression: (baud rate) = f asck n 2 6 + f asck : asck pin input clock frequency n : value set in bits tps3 to tps0 of brgc (n = 0 to 11) when this function is used, a number of baud rates can be generated by one external input clock. chapter 17 asynchronous serial interface/3-wire serial i/o 440 user s manual u11316ej4v1ud (2) serial clock generation in 3-wire serial i/o mode selected when the csck1 bit of the clocked serial interface mode register (csim1) is set (to 1) and sck1 is output. (a) normal mode the internal clock (f xx /2) is scaled by the frequency divider, this signal (f prs ) is scaled by the 5-bit counter, and the signal further divided by 2 is used as the serial clock. the serial clock is given by the following expression: (serial clock) = f k xx n () +? + 16 2 3 f xx : oscillator frequency or external clock input k : value set in bits mdl3 to mdl0 of brgc (k = 0 to 14) n : value set in bits tps3 to tps0 of brgc (n = 0 to 11) (b) high-speed mode when this function is used, bits mdl3 to mdl0 of the baud rate generator control register (brgc) are all set (1) (k = 15). the internal clock (f xx /2) is scaled by the frequency divider, and this signal (f prs ) divided by 2 is used as the serial clock. the serial clock is given by the following expression: (serial clock) = f xx n 2 3 + f xx : oscillator frequency or external clock input n : value set in bits tps3 to tps0 of brgc (n = 1 to 11) chapter 17 asynchronous serial interface/3-wire serial i/o 441 user s manual u11316ej4v1ud 17.4.4 baud rate setting in asynchronous serial interface mode there are two methods of setting the baud rate, as shown in table 17-3. this table shows the range of baud rates that can be generated, the baud rate calculation expression and selection method for each case. table 17-3 baud rate setting methods baud rate clock source selection method baud rate calculation baud rate range expression baud rate generator internal system clock sck in asim = 1 f k xx n () +? + 16 2 3 asck input sck in asim = 0 f asck n 2 6 + note including f asck input range: (0 f xx /256) remarks f xx : oscillator frequency or external clock input k : value set in bits mdl3 to mdl0 of brgc (k = 0 to 14; see figure 17-15) n : value set in bits tps3 to tps0 of brgc (n = 0 to 11; see figure 17-15) f asck : asck input clock frequency (0 f xx /4) (1) examples of settings when baud rate generator is used examples of baud rate generator control register (brgc) settings when the baud rate generator is used are shown below. when the baud rate generator is used, the sck bit of the asynchronous serial interface mode register (asim) should be set (to 1). f asck f asck note 131,072 64 f xx f xx 491,520 128 chapter 17 asynchronous serial interface/3-wire serial i/o 442 user s manual u11316ej4v1ud table 17-4 examples of brgc settings when baud rate generator is used oscillator frequency (f xx ) 32.0000 mhz 31.9488 mhz 25.0000 mhz 24.5760 mhz 12.0000 mhz 11.0592 mhz or external clock (f x ) baud rate brgc error brgc error brgc error brgc error brgc error brgc error [bps] value (%) value (%) value (%) value (%) value (%) value (%) 75 bah 0.16 bah 0.00 b4h 1.73 b4h 0.00 a4h 2.34 a2h 0.00 110 b2h 1.36 b2h 1.52 ach 0.92 abh 1.01 9bh 1.36 99h 1.82 150 aah 0.16 aah 0.00 a4h 1.73 a4h 0.00 94h 2.34 92h 0.00 300 9ah 0.16 9ah 0.00 94h 1.73 94h 0.00 84h 2.34 82h 0.00 600 8ah 0.16 8ah 0.00 84h 1.73 84h 0.00 74h 2.34 72h 0.00 1,200 7ah 0.16 7ah 0.00 74h 1.73 74h 0.00 64h 2.34 62h 0.00 2,400 6ah 0.16 6ah 0.00 64h 1.73 64h 0.00 54h 2.34 52h 0.00 4,800 5ah 0.16 5ah 0.00 54h 1.73 54h 0.00 44h 2.34 42h 0.00 9,600 4ah 0.16 4ah 0.00 44h 1.73 44h 0.00 34h 2.34 32h 0.00 19,200 3ah 0.16 3ah 0.00 34h 1.73 34h 0.00 24h 2.34 22h 0.00 31,250 30h 0.00 30h 0.16 29h 0.00 29h 1.70 18h 0.00 16h 0.54 38,400 2ah 0.16 2ah 0.00 24h 1.73 24h 0.00 14h 2.34 12h 0.00 76,800 1ah 0.16 1ah 0.00 14h 1.73 14h 0.00 04h 2.34 02h 0.00 115,200 11h 2.12 11h 1.96 0bh 0.47 0bh 1.23 00h 18.62 00h 25.00 153,600 0ah 0.16 0ah 0.00 04h 1.73 04h 0.00 00h 38.96 00h 43.75 chapter 17 asynchronous serial interface/3-wire serial i/o 443 user s manual u11316ej4v1ud (2) examples of settings when external baud rate input (asck) is used table 17-5 shows an example of setting when external baud rate input (asck) is used. when using the asck input, clear the sck bit of the asynchronous serial interface mode register (asim) to 0, and set the corresponding pin in the control mode by using pmc3 or pmc1. table 17-5 examples of settings when external baud rate input (asck) is used f asck 153.6 khz 4.9152 mhz (asck input frequency) baud rate [bps] brgc value brgc value 75 50h a0h 150 40h 90h 300 30h 80h 600 20h 70h 1,200 10h 60h 2,400 00h 50h 4,800 40h 9,600 30h 19,200 20h 38,400 10h 76,800 00h chapter 17 asynchronous serial interface/3-wire serial i/o 444 user s manual u11316ej4v1ud 17.5 cautions (1) an asynchronous serial interface mode register (asim) rewrite should not be performed during a transmit operation. if an asim rewrite is performed during a transmit operation, subsequent transmit operations may not be possible (normal operation is restored by reset input). software can determine whether transmission is in progress by using a transmission completion interrupt (intst) or the interrupt request flag (stif) set by intst. (2) after reset input the transmit shift register (txs) is emptied but a transmission completion interrupt is not generated. a transmit operation can be started by writing transmit data to the txs. (3) the receive buffer (rxb) must be read even if there is a receive error. if rxb is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. (4) to disable the reception completion interrupt on occurrence of a reception error, insert wait cycles of two clocks that serve as the reference of the baud rate clock after occurrence of the reception error and before the receive buffers (rxb and rxb2) are read. otherwise, the reception completion interrupt occurs even through the interrupt is disabled. the time equivalent to the above two clocks can be calculated by the following expression; wait time = 2 n + 3 f xx remark f xx : oscillation frequency n: value of n when 12-bit prescaler is selected by baud rate generator control register (brgc, brgc2) (n = 0 to 11). (5) the contents of the asynchronous serial interface status register (asis) are cleared (to 0) by reading the receive buffer (rxb) or by reception of the next data. if you want to find the details of an error, therefore, asis must be read before reading rxb. (6) the baud rate generator control register (brgc) should not be written to during communication. if a write instruction is executed, the 5-bit counter and 1/2 frequency divider operations will be reset, and the generated baud rate clock may be disrupted, preventing normal communication from continuing. (7) specify whether data is transferred with msb or lsb first before writing the sio. even if the specification is made after writing the sio, the byte order of the data already stored in the sio cannot be changed. chapter 17 asynchronous serial interface/3-wire serial i/o 445 user s manual u11316ej4v1ud (8) when data is successively transmitted from the transmission side in 3-wire serial i/o mode, the second and subsequent receive data may be undefined under the following conditions <1> and <2>. <1> read from the shift register (sion) is not completed in the period from reception completion ( a in the figure below) to the next fall of the serial clock (sckn) ( b in the figure below) (n = 1 or 2) <2> the reception enable bit is cleared in the period from reception completion ( a in the figure below) to the next rise of the serial clock (sckn) ( c in the figure below), and the reception enable flag cannot be set after the shift register (sion) is read (n = 1 or 2) sckn sin abc intcsin d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 implement the following workaround to prevent this bug. read the shift register after reception completion ( a in the figure above) by the next fall of the serial clock ( b in the figure above). clear the reception enable bit after reception completion ( a in the figure above) by the next rise of the serial clock ( c in the figure above), read the shift register, and set the reception enable flag. remark n = 1 or 2 446 user? manual u11316ej4v1ud chapter 18 3-wire/2-wire serial i/o mode 18.1 functions (1) 3-wire serial i/o mode (msb/lsb first) in this mode, 8-bit data are transferred by using three lines, a serial clock line (sck0) and two serial bus lines (so0 and si0). this mode is useful when connecting a peripheral i/o or display controller having the conventional clocked serial interface. generally, a handshake line is necessary for checking the communication status. (2) 2-wire serial i/o mode (msb first) in this mode, 8-bit data are transferred by using two lines, a serial clock line (scl) and a serial data bus line (sda). generally, a handshake line is necessary for checking the communication status. 18.2 configuration figure 18-1 shows the block diagram of the clocked serial interface (csi) in the 3-wire/2-wire serial i/o mode. chapter 18 3-wire/2-wire serial i/o mode 447 user? manual u11316ej4v1ud figure 18-1 block diagram of clocked serial interface (in 3-wire/2-wire serial mode) internal bus 1/8 8 1/8 csim ctxe crxe mod1 mod0 cls1 cls0 direction control circuit iicc spt stt reset clear set d q so latch reset shift register (sio) 8 reset p27/si0 note note note p33/so0/sda p32/sck0/scl cls0 cls1 serial clock counter cls0 cls1 timer 3 output f xx /16 interrupt signal generator intcsi f xx /2 8 sprm sprs3 sprs2 sprs1 sprs0 reset internal bus 8 selector serial clock control circuit selector selector prescaler cmos push-pull output : in 3-wire serial i/o mode n-ch open-drain output : in 2-wire serial i/o mode chapter 18 3-wire/2-wire serial i/o mode 448 user s manual u11316ej4v1ud (1) shift register (sio) the sio converts 8-bit serial data to 8-bit parallel data, and vice versa. sio is used for both transmission and reception. actual transmit/receive operations are controlled by writing to/reading from sio. sio can be read or written to with an 8-bit manipulation instruction. the contents of sio are undefined after reset input. (2) so latch the so latch holds the so0/sda pin output level. this latch can also be directly controlled by software. (3) serial clock selector selects the serial clock to be used. (4) serial clock counter counts the serial clocks output or input in a transmit/receive operation, and checks that 8-bit data transmission/reception has been performed. (5) interrupt signal generator a interrupt request is generated when 8 serial clocks have been counted by the serial clock counter. (6) serial clock control circuit controls the supply of the serial clock to the shift register (sio), and also controls the clock output to the sck0 pin when the internal clock is used. (7) direction control circuit controls the transmit/receive data shift direction. chapter 18 3-wire/2-wire serial i/o mode 449 user s manual u11316ej4v1ud 18.3 control registers 18.3.1 clocked serial interface mode register (csim) the csim is an 8-bit register that specifies the serial interface operating mode, serial clock, etc. this register can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the csim format is shown in figure 18-2. reset input clears the csim register to 00h. figure 18-2 clocked serial interface mode register (csim) format 7 ctxe csim 6 crxe 5 0 4 0 3 mod1 2 mod0 1 cls1 0 cls0 address after reset r/w r/w sck0, scl pin external clock slave input output internal clock master tm3/2 sprs f xx /16 00h 0ff82h cls1 serial clock specification 0 0 cls0 0 0 10 11 crxe receive operations disabled enabled 1 0 ctxe transmit operations disabled enabled 1 0 3-wire serial i/o mode msb-first so0, si0, sck0 sda, scl mod1 operating mode selection bit operating mode transfer direction pins used 0 mod0 0 3-wire serial i/o mode 2-wire serial i/o mode lsb-first 01 setting prohibited msb-first 10 11 chapter 18 3-wire/2-wire serial i/o mode 450 user s manual u11316ej4v1ud caution when changing from ?txe = 0, crxe = 1?to ?txe = 1, crxe = 0? and when changing from ?txe = 1, crxe = 0?to ?txe = 0, crxe = 1? ensure that this is not done with a single instruction, as this will result in malfunction of the serial clock counter, and the first communication after the change will finish in fewer than 8 bits. instead, two instructions should be used as shown below. example to change ctxe = 1, crxe = 0 to ctxe = 0, crxe = 1 clr1 ctxe set1 crxe 18.3.2 prescaler mode register for serial clock (sprm) sprm is an 8-bit register that specifies the division ratio of the serial clock when sprs is specified by setting the cls1 bit of the clocked serial interface mode register (csim) to 1 and clearing the cls0 bit of csim to 0. this register can be read or written to with an 8-bit manipulation instruction. figure 18-3 shows the format of sprm. reset input sets this register to 04h. rewrite the contents of sprm only when transmission/reception is disabled (ctxe = crxe = 0). figure 18-3 format of prescaler mode register (sprm) for serial clock 0000sprs3sprs2sprs1sprs0 76543210 sprm 0ff81h address 04h after reset r/w r/w sprs3 0 0 0 0 0 0 0 0 1 1 specifies serial clock f xx /16 f xx /24 f xx /32 f xx /48 f xx /64 f xx /96 f xx /128 f xx /192 f xx /256 f xx /384 sprs2 0 0 0 0 1 1 1 1 0 0 sprs1 0 0 1 1 0 0 1 1 0 0 sprs0 0 1 0 1 0 1 0 1 0 1 chapter 18 3-wire/2-wire serial i/o mode 451 user s manual u11316ej4v1ud 18.3.3 i 2 c bus control register (iicc) iicc is an 8-bit register composed of bits which control the so latch status. iicc is read or written with 8-bit manipulation instructions and bit manipulation instructions. when a read is performed, iicc is read as 00 . the format of the iicc register is shown in figure 18-4. the iicc register must not be written to during a transmit, receive, or transmit/receive operation. reset input clears sbic to 00h. figure 18-4 format of i 2 c bus control register (iicc) 000000sttspt 76543210 iicc 0ff80h address 00h after reset r/w r/w spt 0 1 operation not affected sets so latch (1) stt 0 1 operation not affected clears so latch (0) 18.4 3-wire serial i/o mode the 3-wire serial i/o mode is used to communicate with devices that incorporate a conventional clocked serial interface. basically, communication is performed using three lines: the serial clock (sck0), serial data output (so0), and serial data input (si0). generally, a handshake line is necessary for checking the communication status. figure 18-5 example of 3-wire serial i/o system configuration 3-wire serial i/o ? ? ? ? ? 3-wire serial i/o sck so si port (interrupt) port sck si so port interrupt (port) master cpu note slave cpu note handshaking lines chapter 18 3-wire/2-wire serial i/o mode 452 user s manual u11316ej4v1ud 18.4.1 basic operation timing in the 3-wire serial i/o mode, data transmission/ reception is performed in 8-bit units. data is transmitted/received bit by bit in msb-first or lsb-first order in synchronization with the serial clock. msb first/lsb first switching is specified by the mod 0 bit of the clocked serial interface mode register (csim). transmit data is output in synchronization with the fall of sck0, and receive data is sampled on the rise of sck0. an interrupt request (intcsi) is generated on the 8th rise of sck0. when the internal clock is used as sck0, sck0 output is stopped on the 8th rise of sck0 and sck0 remains high until the next data transmit or receive operation is started. 3-wire serial i/o mode timing is shown in figure 18-6. figure 18-6 3-wire serial i/o mode timing (1/2) (a) msb-first intcsi di7 di6 di5 di4 di3 di2 di1 di0 sck0 note si0 (input) so0 (output) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 transfer end interrupt generation note master cpu: output slave cpu: input transfer starts after execution of a write instruction to sio chapter 18 3-wire/2-wire serial i/o mode 453 user s manual u11316ej4v1ud figure 18-6 3-wire serial i/o mode timing (2/2) (b) lsb-first intcsi di0 di1 di2 di3 di4 di5 di6 di7 sck0 note si0 (input) so0 (output) 12345678 do0 do1 do2 do3 do4 do5 do6 do7 transfer end interrupt generation note master cpu: output slave cpu: input transfer starts after execution of a write instruction to sio in the 3-wire serial i/o mode, the so0 pin functions as a cmos push-pull output. chapter 18 3-wire/2-wire serial i/o mode 454 user s manual u11316ej4v1ud 18.4.2 operation when transmission only is enabled a transmit operation is performed when the ctxe bit of the clocked serial interface mode register (csim) is set (to 1). the transmit operation starts when a write to the shift register (sio) is performed while the ctxe1 bit is set (to 1). when the ctxe bit is cleared (to 0), the so0 pin is in the output high impedance state. (1) when the internal clock is selected as the serial clock when transmission starts, the serial clock is output from the sck0 pin and data is output in sequence from sio to the so0 pin in synchronization with the fall of the serial clock, and si0 pin signals are shifted into sio in synchronization with the rise of the serial clock. there is a delay of up to one sck0 clock cycle between the start of transmission and the first fall of sck0. if transmission is disabled during the transmit operation (by clearing (to 0) the ctxe bit), sck0 clock output is stopped and the transmit operation is discontinued on the next rise of sck0. in this case an interrupt request (intcsi) is not generated, and the so0 pin becomes output high impedance. (2) when an external clock is selected as the serial clock when transmission starts, data is output in sequence from sio to the so0 pin in synchronization with the fall of the serial clock input to the sck0 pin after the start of transmission, and si0 pin signals are shifted into sio in synchronization with the rise of the sck0 pin input. if transmission has not started, shift operations are not performed and the so0 pin output level does not change even if the serial clock is input to the sck0 pin. if transmission is disabled during the transmit operation (by clearing (to 0) the ctxe bit), the transmit operation is discontinued and subsequent sck0 input is ignored. in this case an interrupt request (intcsi) is not generated, and the so0 pin becomes output high impedance. 18.4.3 operation when reception only is enabled a receive operation is performed when the crxe bit of the clocked serial interface mode register (csim) is set (to 1). the receive operation starts when the crxe changes from 0 to 1 , or when a read from shift register (sio) is performed. (1) when the internal clock is selected as the serial clock when reception starts, the serial clock is output from the sck0 pin and the si0 pin data is fetched in sequence into shift register (sio) in synchronization with the rise of the serial clock. there is a delay of up to one sck0 clock cycle between the start of reception and the first fall of sck0. if reception is disabled during the receive operation (by clearing (to 0) the crxe bit), sck0 clock output is stopped and the receive operation is discontinued on the next rise of sck0. in this case an interrupt request (intcsi) is not generated, and the contents of the sio register will be undefined. (2) when an external clock is selected as the serial clock when reception starts, the si0 pin data is fetched into shift register (sio) in synchronization with the rise of the serial clock input to the sck0 pin after the start of reception. if reception has not started, shift operations are not performed even if the serial clock is input to the sck0 pin. if reception is disabled during the receive operation (by clearing (to 0) the crxe bit), the receive operation is discontinued and subsequent sck0 input is ignored. in this case an interrupt request (intcsi) is not generated. chapter 18 3-wire/2-wire serial i/o mode 455 user s manual u11316ej4v1ud 18.4.4 operation when transmission/reception is enabled when the ctxe bit and crxe bit of the clocked serial interface mode register (csim) are both set (to 1), a transmit operation and receive operation can be performed simultaneously (transmit/receive operation). the transmit/receive operation is started when the crxe bit is changed from 0 to 1 , or by performing a write to shift register (sio). when a transmit operation is started for the first time, the crxe bit always changes from 0 to 1 , and there is thus a possibility that the transmit/receive operation will start immediately, and undefined data will be output. the first transmi t data should therefore be written to sio beforehand when both transmission and reception are disabled (when the ctxe bit and crxe bit are both cleared (to 0)), before enabling transmission/reception. when transmission/reception is disabled (ctxe = crxe = 0), the so0 pin is in the output high impedance state. (1) when the internal clock is selected as the serial clock when transmission/reception starts, the serial clock is output from the sck0 pin, data is output in sequence from shift register (sio) to the so0 pin in synchronization with the fall of the serial clock, and si0 pin data is shifted in order into sio in synchronization with the rise of the serial clock. there is a delay of up to one sck0 clock cycle between the start of transmission and the first fall of sck0. if either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is discontinued. if transmission only is disabled, the so0 pin becomes output high impedance. if reception only is disabled, the contents of the sio register will be undefined. if transmission and reception are disabled simultaneously, sck0 clock output is stopped and the transmit and receive operations are discontinued on the next rise of sck0. when transmission and reception are disabled simultaneously, the contents of sio are undefined, an interrupt request (intcsi) is not generated, and the so0 pin becomes output high impedance. (2) when an external clock is selected as the serial clock when transmission/reception starts, data is output in sequence from shift register (sio) to the so0 pin in synchronization with the fall of the serial clock input to the sck0 pin after the start of transmission/reception, and si0 pin data is shifted in order into sio in synchronization with the rise of the serial clock. if transmission/reception has not started, shift operations are not performed and the so0 pin output level does not change even if the serial clock is input to the sck0 pin. if either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is discontinued. if transmission only is disabled, the so0 pin becomes output high impedance. if reception only is disabled, the contents of the sio register will be undefined. if transmission and reception are disabled simultaneously, the transmit and receive operations are discontinued and subsequent sck0 input is ignored. when transmission and reception are disabled simultaneously, the contents of sio are undefined, an interrupt request (intcsi) is not generated, and the so0 pin becomes output high impedance. 18.4.5 corrective action in case of slippage of serial clock and shift operations when an external clock is selected as the serial clock, there may be slippage between the number of serial clocks and shift operations due to noise, etc. in this case, since the serial clock counter is initialized by disabling both transmit ope rations and receive operations (by clearing (to 0) the ctxe bit and crxe bit), synchronization of the shift operations and the serial clock can be restored by using the first serial clock input after reception or transmission is next enabled as the first clock. chapter 18 3-wire/2-wire serial i/o mode 456 user s manual u11316ej4v1ud 18.5 2-wire serial i/o mode the 2-wire serial i/o mode an support any communication format depending on the program. basically, communication is performed by using two lines, a serial clock line (scl) and a serial data input/output line (sda). generally, a handshake line is necessary for checking the communication status. in the 2-wire serial i/o mode, both the scl and sda pins serves as n-ch open-drain output pins in the output mode. therefore, connect external pull-up resistors to these pins. figure 18-7 example of configuration of 2-wire serial i/o system master cpu slave cpu scl sda port (interrupt) port scl sda port port (interrupt) note v dd v dd note handshake line chapter 18 3-wire/2-wire serial i/o mode 457 user s manual u11316ej4v1ud 18.5.1 basic operation timing in the 2-wire serial i/o mode, data are transferred/received in 8-bit units. data are transferred/received in synchronization with the serial clock in 1-bit units with the msb first. transmit data is output at the falling edge of scl. receive data is sampled at the rising edge of scl. an interrupt request (intcsi) is generated at the eighth rising edge of scl. when scl is used as the internal clock, output of scl is stopped at the eighth rising edge of scl and scl is kept high until transfer or reception of the next data is started. figure 18-8 timing in 2-wire serial i/o mode sda scl note intcsi 12345678 d7 d6 d5 d4 d3 d2 d1 d0 transfer end interrupt occurs starts at falling edge of sck0 note master cpu: output slave cpu: input the pin specified as the serial data bus of the sda pin serves as an n-ch open-drain i/o pin and must be externally pulled up by resistor. because sda outputs the status of the so latch, the output status of the sda pin can be manipulated by setting the spt and stt bits. however, do not set these bits during serial transfer. when scl is used as the internal clock (when used as the master cpu), the scl pin serves as an n-ch open-drain output pin and must be externally pulled up by resistor. chapter 18 3-wire/2-wire serial i/o mode 458 user s manual u11316ej4v1ud 18.5.2 operation when transmission only is enabled a transmit operation is performed when the ctxe bit of the clocked serial interface mode register (csim) is set (to 1). the transmit operation starts when a write to the shift register (sio) is performed while the ctxe1 bit is set (to 1). when the ctxe bit is cleared (to 0), the sda pin is in the output high impedance state. (1) when the internal clock is selected as the serial clock when transmission starts, the serial clock is output from the scl pin and data is output in sequence from sio to the sda pin in synchronization with the fall of the serial clock. there is a delay of up to one scl clock cycle between the start of transmission and the first fall of scl. if transmission is disabled during the transmit operation (by clearing (to 0) the ctxe bit), scl clock output is stopped and the transmit operation is discontinued on the next rise of scl. in this case an interrupt request (intcsi) is not generated, and the sda pin becomes output high impedance. (2) when an external clock is selected as the serial clock when transmission starts, data is output in sequence from sio to the sda pin in synchronization with the fall of the serial clock input to the scl pin after the start of transmission. if transmission has not started, shift operations are not performed and the sda pin output level does not change even if the serial clock is input to the scl pin. if transmission is disabled during the transmit operation (by clearing (to 0) the ctxe bit), the transmit operation is discontinued and subsequent scl input is ignored. in this case an interrupt request (intcsi) is not generated, and the sda pin becomes output high impedance. (3) detecting transmit error because the status of the serial data (sda) being transmitted is also input to the sio of the device that is sending the data in the 2-wire serial i/o mode, the data of the sio before and after transmission can be compared and it can be judged, if the two data are different, that a transmit error has occurred. 18.5.3 operation when reception only is enabled a receive operation is performed when the crxe bit of the clocked serial interface mode register (csim) is set (to 1). the receive operation starts when the crxe changes from 0 to 1 , or when a read from shift register (sio) is performed. (1) when the internal clock is selected as the serial clock when reception starts, the serial clock is output from the scl pin and the sda pin data is fetched in sequence into shift register (sio) in synchronization with the rise of the serial clock. there is a delay of up to one scl clock cycle between the start of reception and the first fall of scl. if reception is disabled during the receive operation (by clearing (to 0) the crxe bit), scl clock output is stopped and the receive operation is discontinued on the next rise of scl. in this case an interrupt request (intcsi) is not generated, and the contents of the sio register will be undefined. (2) when an external clock is selected as the serial clock when reception starts, the sda pin data is fetched into shift register (sio) in synchronization with the rise of the serial clock input to the scl pin after the start of reception. if reception has not started, shift operations are not performed even if the serial clock is input to the scl pin. if reception is disabled during the receive operation (by clearing (to 0) the crxe bit), the receive operation is discontinued and subsequent scl input is ignored. in this case an interrupt request (intcsi) is not generated. chapter 18 3-wire/2-wire serial i/o mode 459 user s manual u11316ej4v1ud 18.5.4 operation when transmission/reception is enabled when the ctxe bit and crxe bit of the clocked serial interface mode register (csim) are both set (to 1), a transmit operation and receive operation can be performed simultaneously (transmit/receive operation). the transmit/receive operation is started when the crxe bit is changed from 0 to 1 , or by performing a write to shift register (sio). when a transmit operation is started for the first time, the crxe bit always changes from 0 to 1 , and there is thus a possibility that the transmit/receive operation will start immediately, and undefined data will be output. the first transmi t data should therefore be written to sio beforehand when both transmission and reception are disabled (when the ctxe bit and crxe bit are both cleared (to 0)), before enabling transmission/reception. when transmission/reception is disabled (ctxe = crxe = 0), the sda pin is in the output high impedance state. (1) when the internal clock is selected as the serial clock when transmission/reception starts, the serial clock is output from the scl pin, data is output in sequence from shift register (sio) to the sda pin in synchronization with the fall of the serial clock, and sda pin data is shifted in order into sio in synchronization with the rise of the serial clock. there is a delay of up to one scl clock cycle between the start of transmission and the first fall of scl. if either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is discontinued. if transmission only is disabled, the sda pin becomes output high impedance. if reception only is disabled, the contents of the sio register will be undefined. if transmission and reception are disabled simultaneously, scl clock output is stopped and the transmit and receive operations are discontinued on the next rise of scl. when transmission and reception are disabled simultaneously, the contents of sio are undefined, an interrupt request (intcsi) is not generated, and the sda pin becomes output high impedance. (2) when an external clock is selected as the serial clock when transmission/reception starts, data is output in sequence from shift register (sio) to the sda pin in synchronization with the fall of the serial clock input to the scl pin after the start of transmission/reception, and sda pin data is shifted in order into sio in synchronization with the rise of the serial clock. if transmission/reception has not started, shift operations are not performed and the sda pin output level does not change even if the serial clock is input to the scl pin. if either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is discontinued. if transmission only is disabled, the sda pin becomes output high impedance. if reception only is disabled, the contents of the sio register will be undefined. if transmission and reception are disabled simultaneously, the transmit and receive operations are discontinued and subsequent scl input is ignored. when transmission and reception are disabled simultaneously, the contents of sio are undefined, an interrupt request (intcsi) is not generated, and the sda pin becomes output high impedance. (3) detecting transmit error because the status of the serial data (sda) being transmitted is also input to the sio of the device that is sending the data in the 2-wire serial i/o mode, the data of the sio before and after transmission can be compared and it can be judged, if the two data are different, that a transmit error has occurred. 18.5.5 corrective action in case of slippage of serial clock and shift operations when an external clock is selected as the serial clock, there may be slippage between the number of serial clocks and shift operations due to noise, etc. in this case, since the serial clock counter is initialized by disabling both transmit ope rations and receive operations (by clearing (to 0) the ctxe bit and crxe bit), synchronization of the shift operations and the serial clock can be restored by using the first serial clock input after reception or transmission is next enabled as the first clock. chapter 18 3-wire/2-wire serial i/o mode 460 user? manual u11316ej4v1ud 18.6 cautions (1) when changing from ?txe = 0, crxe = 1?to ?txe = 1, crxe = 0? and when changing from ?txe = 1, crxe = 0?to ?txe = 0, crxe = 1? ensure that this is not done with a single instruction, as this will result in malfunction of the serial clock counter, and the first communication after the change will finish in fewer than 8 bits. instead, two instructions should be used as shown below. example to change ?txe = 1, crxe = 0?to ?txe = 0, crxe = 1 clr1 ctxe set1 crxe (2) in the pd784038, 784038y subseries, data is output when data is written to the shift register. sck0 so0 intcsi ab c a: setting the transmission enable bit (ctxe 1) b: data (55h) written to shift register (sio 55h) c: generation of transfer completion interrupt request (3) in the pd784038, 784038y subseries, the serial clock counter is incremented by one when the shift register is written after transmission is enabled and if the sck0 pin is low level. therefore, if transmission is started while the external clock is selected as the serial clock and the sck0 pin is low level, a transmission completion interrupt request is generated at the 7th rising of the serial clock. sck0 so0 intcsi ab c a: setting the transmission enable bit (ctxe 1) b: data (aah) written to shift register (sio aah) c: generation of transfer completion interrupt request chapter 18 3-wire/2-wire serial i/o mode 461 user s manual u11316ej4v1ud (4) when master transmission and slave reception are executed alternately in 3-wire serial i/o mode, an invalid serial clock may be output from the sck0 pin. (not applicable to sck1 and sck2 pins) set sck0 to high-level output port mode in the period in which the invalid clock (1 system clock max.) indicated in attachment 2 may be generated when alternately executing master transmission and slave reception. sck0 invalid clock cpu processing <1> <2> <3> <4> <5> <6> transmission <1> end of slave reception <2> sio read <3> reception disabled (crxe = 0) <4> transmit clock selection <5> master transmission enabled (ctxe = 1) <6> sio write preventive program example (when tm3/2 is selected as the internal clock) set1 p3.2 ; p32 = 1 clr1 pmc3.2 ; sck0 pin: i/o port mode clr1 crxe ; reception disabled set1 csim.0 ; slave master set1 ctxe ; transmission enabled : ; wait for at least 1 serial clock set1 pmc3.2 ; sck0 pin: sck0 i/o mode mov sio,a ; write to sio register chapter 18 3-wire/2-wire serial i/o mode 462 user? manual u11316ej4v1ud (5) when data is successively transmitted from the transmission side in 3-wire serial i/o mode, the second and subsequent receive data may be undefined under the following conditions <1> and <2>. <1> read from the shift register (sio) is not completed in the period from reception completion ( a in the figure below) to the next fall of the serial clock (sck0) ( b in the figure below) <2> the reception enable bit is cleared in the period from reception completion ( a in the figure below) to the next rise of the serial clock (sck0) ( c in the figure below), and the reception enable flag cannot be set after the shift register (sio) is read sck0 si0 abc intcsi d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 implement the following workaround to prevent this bug. read the shift register after reception completion ( a in the figure above) by the next fall of the serial clock ( b in the figure above). clear the reception enable bit after reception completion ( a in the figure above) by the next rise of the serial clock ( c in the figure above), read the shift register, and set the reception enable flag. 463 user? manual u11316ej4v1ud chapter 19 i 2 c bus mode ( pd784038y subseries only) 19.1 outline of functions ? 2 c (inter ic) bus mode (msb first) the i 2 c bus mode is an interface for communicating with devices that conform with the i 2 c bus format. it allows 8-bit data transfer to several devices using 2 lines: a serial clock line (scl) and a serial data bus (sda). in the i 2 c bus mode, the master can output start conditions, data, and stop conditions to a slave on the serial data bus. a slave automatically detects the data received by means of hardware. this function can simplify the i 2 c bus control part in application programs. the conventional serial i/o method being limited to a data transfer function, a lot of ports and wiring are required in order to discriminate chip select signals and command/data and recognize busy states when the serial bus is configured with several devices connected. in addition, performing these controls with software places a considerable load on software. in the i 2 c bus mode, the serial bus can be configured with two signal lines, a serial clock line (scl) and a serial data bus (sda). therefore, use of this mode is effective to reduce the number of microcontroller ports, wiring, and complicated routing in the circuit board. the i 2 c bus mode is used for performing single master and slave operations through the i 2 c bus. for further information, refer to 19.4 i 2 c bus mode functions figure 19-1 example of serial bus configuration using i 2 c bus master cpu sda scl serial data bus serial clock slave cpu address 1 slave cpu address 2 slave ic address 3 slave ic address n +v dd sda scl sda scl sda scl sda scl +v dd chapter 19 i 2 c bus mode ( pd784038y subseries only) 464 user s manual u11316ej4v1ud figure 19-2 block diagram of clock-synchronous serial interface (in i 2 c bus mode) 19.2 configuration the block diagram of the clock-synchronous serial interface (csi) in the i 2 c bus mode is shown in figure 19-2. internal bus 1/8 8 1/8 reset csim ctxe wup cls1 cls0 slave address register (sva) reset 8 8 match signal reset iicc spt stt spd std acke ackd wrel wtim set clear so latch d q reset shift register (sio) data hold time correction circuit dht0 dht1 acknowledge detection circuit intspc intcsi interrupt signal generation circuit serial clock wait control circuit f xx /2 8 8 internal bus reset sprm scd dht1 dht0 sprs3 sprs2 sprs1 sprs0 serial clock control circuit serial clock counter acknowledge detection circuit start condition detection circuit stop condition detection circuit mod0 mod1 mod0 mod1 mod0 mod1 cls0 cls1 n-ch open drain output p32/sck0/scl n-ch open drain output p33/so0/sda wake up control circuit noise elimination circuit noise elimination circuit noise elimination circuit prescaler chapter 19 i 2 c bus mode ( pd784038y subseries only) 465 user s manual u11316ej4v1ud (1) shift register (sio) the sio register converts 8-bit serial data to 8-bit parallel data or vice versa. it is used both for transmission and reception. actual transmission and reception is controlled by writing/reading to/from the sio register. reading and writing is performed with 8-bit manipulation instructions. reset input causes the contents of this register to become undefined. (2) slave address register (sva) the slave address register is used to set the address of this microcomputer when it is used as a slave. this register can also be used to check the direction of transmission. (3) so latch the so latch serves to retain the sda pin output level. it can be controlled by software. (4) wake up control circuit the wake up control circuit is used when the microcomputer is employed as a slave to control whether to always generate an interrupt or generate an interrupt only when the address set to the slave address register (sva) matches the reception address. (5) serial clock selector the serial clock selector selects the serial clock to be used. (6) serial clock counter the serial clock counter counts the serial clocks output during transmission and reception to check whether transmission or reception has been performed. (7) interrupt signal generator the interrupt signal generator controls the generation of interrupt request signal. interrupt requests are generated with the timing shown in table 19-1 based on the setting of bit 7 (wtim) in the i 2 c bus control register (iicc) and bit 5 (wup) in the clock synchronous serial interface mode register (csim). (8) serial clock control circuit this circuit controls the serial clock supplied to the shift register (sio). in addition, it controls the clock output to the scl pin if the internal clock is used. (9) serial clock wait control circuit the serial clock wait control circuit controls wait timing. (10) acknowledge output circuit, stop condition detection circuit, start condition detection circuit, acknowledge detection circuit these circuits output and detect various control signals. (11) data hold time correction circuit this circuit generates the data hold time at the falling edge of the serial clock. this circuit is controlled by setting the data hold time specification bit (dht0, dht1) in the prescaler mode register (sprm) for serial clock with the external oscillation frequency. chapter 19 i 2 c bus mode ( pd784038y subseries only) 466 user s manual u11316ej4v1ud 19.3 control register 19.3.1 clocked serial interface mode register (csim) csim is an 8-bit register used to specify the serial interface operation mode, serial clock, wakeup function, and so on. it is read/written with 8-bit manipulation instructions. the format of the csim is shown in figure 19-3. reset input clears the contents of this register to 00h. figure 19-3 clocked serial interface mode register (csim) format ctxe 0 wup 0 1 1 cls1 cls0 6 43210 csim 0ff82h address 00h after reset r/w r/w cls1 0 1 serial clock specification external clock internal clock setting prohibited cls0 0 0 slave master sprs input output other than above sck0, scl pins wup 0 1 wakeup function control an interrupt request is generated every time address and data transfer is completed. an interrupt request (intcsi) is generated upon reception of this microcontroller's address, and then an interrupt request (intcsi) is generated every time data transfer is completed. ctxe 0 1 reception/transmission disabled enabled 75 19.3.2 i 2 c bus control register (iicc) iicc is an 8-bit register consisting of a bit that controls the serial bus status. reading and writing is performed with 8-bit manipulation instructions. during read operation, the write-only bit is 0 . figure 19-4 shows the format of iicc. do not write data to iicc during transmission, reception, and transmission/reception. reset input clears the contents of this register to 00h. chapter 19 i 2 c bus mode ( pd784038y subseries only) 467 user s manual u11316ej4v1ud figure 19-4 i 2 c bus control register (iicc) format (1/2) wtim wrel ackd acke std spd stt spt 76543210 iicc 0ff80h address 00h after reset r/w r/w wait timing setting bit (r/w) this bit controls the interrupt generation timing and wait timing control during data reception. rewrite this bit only when transmission/reception is prohibited (ctxe = 0). wtim 0 8-clock wait: interrupt request (intcsi) is generated at eighth falling edge of scl. when used as master : after 8 clocks are output, changes scl output to low level and waits. when used as slave : after 8 clocks are input, changes scl pin to low level and generates a wait request. 1 9-clock wait: interrupt request (intsci) is generated at ninth falling edge of scl. when used as master : after 9 clocks are output, changes scl output to low level and waits. when used as slave : after 9 clocks are input, changes scl pin to low level and generates a wait request. wait cancellation trigger bit (w) wrel wait status is canceled (scl is set to high level) when wrel = 1. acknowledge detection flag (r) ackd clear conditions (ackd = 0) set conditions (ackd = 1) 1 upon detection of acknowledge signal (ack), at wait upon detection of acknowledge signal (ack) (when sda is cancellation (wrel = 1 or s10 write or spt = 1) low level at ninth rising edge of scl) 2 ctxe = 0 3 at reset input acknowledge output enable (r/w) this bit enables output of the acknowledge signal upon reception of data. acke 0 disables automatic output of acknowledge signal. used during transmission, or when 8-clock wait is selected. however, when wup = 1 during address reception, operation is as follows. upon reception of microcontroller address : automatically outputs acknowledge signal in synchro- nization with ninth falling edge. upon reception of other than microcontroller address : does not automatically output acknowledge signal. 1 when 8-clock wait is selected : by making acke = 1 before performing wait control, an acknowledge signal is output in synchronization with the eighth falling edge of scl. when 9-clock wait is selected : by making acke = 1 beforehand, an acknowledge signal is automatically output in synchronization with the eighth falling edge of scl. however, when wup = 1 during address reception, operation is as follows. upon reception of microcontroller address : automatically outputs acknowledge signal. upon reception of other than microcontroller address : does not automatically output acknowledge signal. following the eighth falling edge when 8-clock wait is selected, if the acke bit is changed from 0 to 1, ack is output with the timing set in acke. chapter 19 i 2 c bus mode ( pd784038y subseries only) 468 user? manual u11316ej4v1ud figure 19-4 i 2 c bus control register (iicc) format (2/2) wtim wrel ackd acke std spd stt spt 76543210 iicc 0ff80h address 00h after reset r/w r/w start condition detection flag (r) std clear conditions (std = 0) set conditions (std = 1) 1 1 upon wait cancellation following detection of start when wup = 0 : upon detection of start condition condition (wrel = 1 or si0 write note or spt-1) when wup = 1 : upon detection of microcontroller 2 ctxe = 0 address 3 at reset input note except during address write when microcontroller is used as master. stop condition detection flag (r) spd clear conditions (spd = 0) set conditions (spd = 1) 1 1 upon detection of start condition upon detection of stop condition 2 ctxe = 0 3 at reset input start condition trigger bit (w) stt by making stt = 1 when scl and sda are high level note 1 , the s0 latch is cleared (to 0). after the s0 latch is cleared, scl becomes low level, and the stt bit is automatically cleared (to 0). notes 1. the level of scl can be checked by using the p32/scl pin as an input pin (pm32 = 1) and reading scl note 2 . the level of sda can be checked by using the p33/sda pin as an input pin (pm33 = 1) and reading sda note 2 . 2. scl and sda are defined as reserved words when using an nec electronics assembler, and as sfr variables using the #pragma sfr command in c compiler. cautions 1. even when stt is set (to 1) when scl and sda are low level, the start condition is not output (after stt is set to 1, scl the start condition is not output even when scl becomes high level. 2. after stt is set (to 1), be sure to write address to sio after executing one or more instructions with nop or the like. stop condition trigger bit (w) spt by making spt = 1, the so latch is cleared (to 0), and the scl becomes high level. after scl becomes high level, the so latch is set (to 1). after the so latch is set, the spt bit is automatically cleared (to 0). chapter 19 i 2 c bus mode ( pd784038y subseries only) 469 user s manual u11316ej4v1ud 19.3.3 prescaler mode system for serial clock (sprm) sprm is an 8-bit register used to specify the serial clock and duty when the data hold time in relation to the falling edge of scl and the serial clock are specified for the internal clock (cls1 bit = 1, cls0 bit 0). this register is read/written with 8-bit manipulation instructions. figure 19-5 shows the format of sprm. reset input sets the contents of this register to 04h. rewrite sprm only when transmission/reception is disabled (ctxe = 0). figure 19-5 prescaler mode register for serial clock (sprm) format scd dht1 dht0 0 sprs3 sprs2 sprs1 sprs0 76543210 sprm 0ff81h address 04h after reset r/w r/w sprs3 0 0 0 0 0 0 0 0 1 1 serial clock specification f xx /16 f xx /24 f xx /32 f xx /48 f xx /64 f xx /96 f xx /128 f xx /192 f xx /256 f xx /384 sprs2 0 0 0 0 1 1 1 1 0 0 sprs1 0 0 1 1 0 0 1 1 0 0 sprs0 0 1 0 1 0 1 0 1 0 1 dht1 0 0 1 data hold time specification 16 mhz < f xx 32 mhz 8 mhz < f xx 16 mhz 4 mhz < f xx 8 mhz dht0 0 1 10/f xx to 12/f xx 5/f xx to 7/f xx 3/f xx to 5/f xx scd 0 1 serial clock duty specification for standard mode for high-speed mode chapter 19 i 2 c bus mode ( pd784038y subseries only) 470 user s manual u11316ej4v1ud 19.3.4 slave address register (sva) sva is an 8-bit register used to specify the microcomputer s address when it is used as a slave device. bit 0 of sva (tre bit) can be used to check whether transmission or reception is performed. bits 1 to 7 are read/written with an 8-bit manipulation instruction. bit 0 can only be read, using an 8-bit manipulation instruction and a bit manipulation instruction. figure 19-5 shows the format of sva. reset input set the contents of this register to 01h. figure 19-6 slave address register (sva) format sva6 sva5 sva4 sva3 sva2 sva1 sva0 tre 76543210 sva 0ff83h address 01h after reset note r/w tre 0 1 status specification transmission mode reception mode set slave address note bit 0: only read (r) is possible. bits 1 to 7: read/write (r/w) are possible. chapter 19 i 2 c bus mode ( user s manual u11316ej4v1ud 19.4 i 2 c bus mode function 19.4.1 pin configuration the serial clock pin (scl) and serial data bus pin (sda) are configured as follows: (1) scl pin that inputs/outputs serial clock master : n-ch open-drain output slave : schmitt input (2) sda serial data input/output dual pin n-ch open-drain output and schmitt input for both master and slave. because both the serial clock and serial data bus are n-ch open drain output, they must be connected to external pull- up resistors. figure 19-7 pin configuration clock output (clock input) data output data input (clock output) clock input data output data input scl sda scl sda master device slave device v dd v dd chapter 19 i 2 c bus mode ( user s manual u11316ej4v1ud 19.4.2 functions the following function is available in the i 2 c bus mode of pd784038y. (1) automatic identification of serial data the start condition , data and stop condition on the serial data bus are automatically detected. (2) chip select by address the master can select specific slave device from those connected to the i 2 c bus by transmitting a slave address and communicate with that slave. (3) wake-up function when a slave operates, it generates an interrupt only when the address it has received from the master coincides with the value of the slave address register (sva). therefore the slave on the i 2 c bus other than the one selected by the master can operate independently of the serial communication. (4) acknowledge signal (ack) control function the acknowledge signal that is used to check whether serial communication has been correctly executed can be controlled during the master and slave operations. (5) wait signal (wait) control function a slave device can control the wait signal that indicates the busy status of the slave. chapter 19 i 2 c bus mode ( user s manual u11316ej4v1ud 19.5 definition and control method of the i 2 c bus the following describes the serial data communication format of the i 2 c bus and the meanings of the signals used. figure 19-8 shows the transfer timing of the start condition , data , and stop condition output to the i 2 c serial data bus. figure 19-8 serial data transfer timing on i 2 c bus scl sda 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 start condition address r/w ack data ack data ack stop condition the start condition, slave address, and stop condition are output by the master. the acknowledge signal (ack) is output by either the master or slave (usually, this signal is output by the side that receives 8-bit data). the serial clock (scl) is continuously output by the master. however, the slave can extend the scl low level period, thus a wait can be inserted. 19.5.1 start condition the start condition is output to the serial data bus when sda pin goes low while the scl pin is high. therefore, the start condition of the scl and sda pins is a signal output by the master when the master starts serial transfer to a slave. figure 19-9 start condition h sda scl the start condition is output by making stt = 1 when scl is being high. when the start condition is executed, std is set (std = 1). after stt is set (to 1), be sure to write address to sio after executing one or more instructions with nop or the like. chapter 19 i 2 c bus mode ( user s manual u11316ej4v1ud 19.5.2 addresses the 7-bit data following the start condition is defined to be an address. an address is 7 bit of data output by the master to select a specific slave from those connected to the bus line. therefore, all the slaves on the bus line must have a different address. a slave detects the start condition by hardware and checks whether the 7-bit data output by the master coincides with the value of the slave address register (sva) of the slave. if the 7-bit data coincides with the value of the slave address register of the slave, is selected. after that, communication takes place between the master and this slave, until the master transmits a start or stop condition. figure 19-10 address scl sda intcsi 123456789 a6 a5 a4 a3 a2 a1 a0 r/w address note note in slave, when wup = 1, if an address other than own address is received, intcsi does not occur. the slave address and the transfer direction explained in section 19.5.3 transfer direction specification are written to iso simultaneously, and then an address is output. the received address is also written into iso with specification of transfer direction. slave address, however, is assigned to the higher 7 bits of sio. after stt is set (to 1), be sure to write address to sio after executing one or more instructions with nop or the like chapter 19 i 2 c bus mode ( user s manual u11316ej4v1ud 19.5.3 transfer direction specification the master transmits the 1-bit data to specify the transfer direction following 7-bit address. the transfer direction specification bit 0 indicates data transmission from the master to the slave. on the other hand, the transfer specification bit 1 indicates data reception from the slave to the master. figure 19-11 transfer direction specification scl sda intcsi 123456789 a6 a5 a4 a3 a2 a1 a0 r/w transfer direction specification note note intcsi is not generated if other than own address is received during wup = 1 in slave operation. transfer direction specification bit is output by writing into sio with address simultaneously. in addition, the received direction is written not only into sio with address but also into tre bit (bit 0) in the slave addres s register (sva) simultaneously. the transfer direction is assigned to the lowest order bit in the sio. after the stt is set (to 1), at least one instruction should be executed using nop, etc. before writing the transfer direction to the sio. chapter 19 i 2 c bus mode ( user s manual u11316ej4v1ud 19.5.4 acknowledge signal (ack) the acknowledge signal is used to confirm that serial data has been received at transmission and reception sides. the reception side returns the acknowledge signal each time it has received 8 bits of data. however, do not return ack on receiving the last data when a start condition or stop condition is to be issued while the master receives data (refer to figure 19-16). the transmission side checks whether the reception side has returned the acknowledge signal after it has transmitted 8-bit data. when the acknowledge signal has been returned, it is assumed that the 8-bit data has been correctly received, and the next processing is performed. if a slave does not return the acknowledge signal, it is not received the data correctly. consequently, the master outputs a stop condition to abort transmission. figure 19-12 acknowledge signal scl sda 123456789 a6 a5 a4 a3 a2 a1 a0 r/w ack remark when 8 clock wait : the acknowledge signal is output synchronized with the falling edge of the eighth clock of scl by setting acke = 1 before the wait release. when 9 clock wait : the acknowledge signal is output synchronized with the falling edge of the eighth clock of scl by setting acke = 1 beforehand. the acknowledge signal is output synchronized with the falling edge of the 8th clock of scl by setting acke (to 1). in wup = 1, however, acknowledge is automatically output synchronized with the falling edge of the 8th clock of scl regardless of acke value when receiving own address and the acknowledged signal is not output when receiving other than own address. when 8-clock wait : the acknowledge signal is output synchronized with the falling edge of the 8th clock of scl by setting acke = 1 before the wait release. when 9-clock wait : the acknowledge signal is output synchronized with the falling edge of the 8th clock of scl by setting acke = 1 beforehand. the following operate when address reception in wup = 1. upon reception of relevant microcontroller address : automatic output of acknowledge signal is per- formed. upon reception of other than relevant microcontroller address : automatic output of acknowledge signal is not performed. chapter 19 i 2 c bus mode ( user s manual u11316ej4v1ud 19.5.5 stop condition the stop condition is set when the sda pin goes high while the scl pin is high. the stop condition is output by the master to the slave when serial transfer has been completed. figure 19-13 stop condition h sda scl the stop condition is generated by setting spt (to 1). and when detecting the stop condition, spd is set (to 1) and intspc is generated. chapter 19 i 2 c bus mode ( user s manual u11316ej4v1ud 19.5.6 wait signal (wait) the wait signal is output by a slave to the master to indicate that the slave is waiting to send/receive data (wait status). the slave informs the master that it is the wait status by making scl pin low. when the slave is released from the wait status, the master can start the next transfer. figure 19-14 wait signal (1/2) (1) when eight clocks wait for master and slave (master: transmission, slave: reception, acke = 0) master slave transmission line sio scl 6789 123 the master makes hi-z and the slave makes it wait (low level). waits after the 9th clock has been output sio data waits after the 8th clock has been output sio ffh sio scl acke scl sda d2 d1 678 9 123 d0 ack d7 d6 d5 chapter 19 i 2 c bus mode ( user s manual u11316ej4v1ud figure 19-14 wait signal (2/2) (2) when nine clocks wait for master and slave (master: transmission, slave: reception, acke = 1) master slave transmission lline sio scl 6789 23 both master and slave wait after the 9th clock has been output. sio data sio ffh sio scl scl sda d2 d1 6789 123 d0 ack d6 d5 acke h d7 output according to the value set to acke beforehand 1 the wait is automatically generated when values are set to both wup and wtim. the wait, however, is released when wrel = 1 is made, and address is written to sio, or ctxe is cleared (to 0). chapter 19 i 2 c bus mode ( user s manual u11316ej4v1ud 19.5.7 interrupt request (intcsi) generation timing and wait control the interrupt request is generated when the combination of the wup bit of the clock synchronous serial interface (csim) and the wtim bit of the i 2 c bus control register (iicc) are correspond with the timings shown in figure 19-1 and also wait is controlled by the same manner. table 19-1 intcsi generation timing and wait control wup wtim slave operation master operation address data data address data data reception transmission reception transmission 00889989 01899999 109 note 1, 2 8 note 2 9 note 2 989 119 note 1, 2 9 note 2 9 note 2 999 notes 1. only when the intcsi signal and wait in slave operation in wup = 1 and the address which has been set in the slave address register (sva) matched, an interrupt request or wait are generated at the falling edge of the 9th clock. at this time, even if acke is set, ack is output. 2. when wup = 1, neither intcsi nor wait in is generated if the sva and received address have not matched. remark the numbers in the table refer to the number of serial clocks. both the interrupt request and wait control synchronize with the falling edge of the serial clock. (1) when address transmission and reception at slave operation : the interrupt timing and wait timing are determined by the wup regardless of wtim bit. at master operation : the interrupt timing and wait timing are generated at the falling edge of the 9th clock regardless of the wup bit and wtim bit. (2) when data reception at master/slave operation : the interrupt timing and wait timing are determined by the wtim bit regardless of wum bit. (3) when data transmission at master/slave operation : the interrupt timing and wait timing are generated at the falling edge of the 9th clock regardless of the wup bit and wtim bit. (4) wait release method three wait release methods are described as below. wrel = 1 in the i 2 c bus control register (iicc). write operation of serial shift register (sio) ctxe = 0 in clock synchronous serial interface mode register when 8 clock wait (wtim = 0) is selected, ack output level should be determined before wait release. chapter 19 i 2 c bus mode ( user s manual u11316ej4v1ud 19.5.8 interrupt request generation timing intspc is generated at the detection of the stop condition. processing to wait the generation of the next start condition is required in the intspc interrupt routine. this is applied when used as a slave or wup = 0. 19.5.9 detection method of address match in the i 2 c bus mode, the master transmits the slave address, as a consequence, the specific slave device can be selected. the address match detection can be performed automatically with the hardware. if the self-addressed setting assigned to the slave address register in the wake up function specification bit (wup) = 1, intcsi interrupt request is generated only when the slave address transmitted from the master matches the address set to sva. to identify the slave reception data as the address, the value of the start bit condition bit (std) should be verified. caution when wup = 0, the intcsi interrupt request is generated, even though the self-addressed setting set to the slave address register (sva) dose not match the data (address) received after the start condition. 19.5.10 error detection in the i 2 c bus mode, the state of the serial bus (sda) during transmission is transferred to the serial shift register of the device during transmission. thus, the transmission error is detected by comparing the data before the transmission with the data after the transmission. in this case, the transmission error occurred if the two data are different each other. 19.6 timing chart in the i 2 c bus mode, the master outputs the address to the serial bus, then, a target slave device is chosen among several slave devices. the master transmits the tre bit, which indicates the data transmission direction next to the slave address, and then, the transmission to the slave starts. figures 19-15 and 19-16 indicate the timing chart of the data transmission. first, the shift operation of the shift register (sio) is performed synchronizing with the falling edge of serial clock, next, the transmission data are sent to so0 latch, finally, they are output from sda pin as msb first. on the other hand, the data input to the sda pin triggered by scl rising edge are held into the sio. chapter 19 i 2 c bus mode ( user s manual u11316ej4v1ud figure 19-15 example of communication from master to slave (with 9-clock wait selected for both master and slave. slave: wup = 0) (1/3) (1) start condition = address sio ackd std spd wup wtim acke stt spt wrel intcsi intspc tre scl sda sio ackd std spd wup wtim acke stt spt wrel intcsi intspc tre processing in master device transfer line processing in slave device sio data sio ffh h h h reception 123456789 1234 a6 a5 a4 a3 a2 a1 a0 w ack d7 d6 d5 d4 sio address note start condition transmission h h note after the stt is set (to 1), at least one instruction such as nop etc., should be executed before writing the address to the sio. chapter 19 i 2 c bus mode ( user s manual u11316ej4v1ud figure 19-15 example of communication from master to slave (with 9-clock wait both selected for master and slave. slave: wup = 0) (2/3) (2) data sio ackd std spd wup wtim acke stt spt wrel intcsi intspc tre scl sda sio ackd std spd wup wtim acke stt spt wrel intcsi intspc tre processing in master device transfer line processing in slave device sio data sio ffh h h h reception transmission sio data sio ffh 89 123456789 123 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 h h chapter 19 i 2 c bus mode ( user s manual u11316ej4v1ud figure 19-15 example of communication from master to slave (with 9-clock wait both selected for master and slave. slave: wup = 0) (3/3) (3) stop condition sio ackd std spd wup wtim acke stt spt wrel intcsi intspc tre scl sda sio ackd std spd wup wtim acke stt spt wrel intcsi intspc tre processing in master device transfer line processing in slave device sio data sio ffh h h h reception 1 d7 start condition transmission sio address sio ffh 23456789 12 d6 d5 d4 d3 d2 d1 d0 a6 a5 stop condition ack h h chapter 19 i 2 c bus mode ( user s manual u11316ej4v1ud figure 19-16 example of communication from slave to master (when selecting the 9th clock wait both master and slave) (1/3) (1) start condition = address sio ackd std spd wup wtim acke stt spt wrel intcsi intspc tre scl sda sio ackd std spd wup wtim acke stt spt wrel intcsi intspc tre processing in master device transfer line processing in slave device sio address note sio data 1 a6 start condition sio ffh h h h h 23456789 123456 a5 a4 a3 a2 a1 a0 r d7 d6 d5 d4 d3 d2 note after the stt is set (to 1), at least one instruction such as nop, etc., should be executed before writing the address to the sio. chapter 19 i 2 c bus mode ( user s manual u11316ej4v1ud figure 19-16 example of communication from slave to master (when selecting the 9th clock wait both master and slave) (2/3) (2) data sio ackd std spd wup wtim acke stt spt wrel intcsi intspc tre scl sda sio ackd std spd wup wtim acke stt spt wrel intcsi intspc tre processing in master device transfer line processing in slave device sio ffh sio data transmission 1 d0 h h h h sio data sio ffh reception 23456789 89 123 d7 d6 d5 d4 d3 d2 d1 d0 ack ack d7 d6 d5 chapter 19 i 2 c bus mode ( user s manual u11316ej4v1ud figure 19-16 example of communication from slave to master (when selecting the 9th clock wait both master and slave) (3/3) (3) stop condition sio ackd std spd wup wtim acke stt spt wrel intcsi intspc tre scl sda sio ackd std spd wup wtim acke stt spt wrel intcsi intspc tre processing in master device transfer line processing in slave device sio ffh sio data 1 d7 sio address h h h h 23456789 12 d6 d5 d4 d3 d2 d1 d0 a6 a5 start condition stop condition n ack chapter 19 i 2 c bus mode ( user s manual u11316ej4v1ud 19.7 signal and flags table 19-2 lists the relationship between kinds of signals and flags in i 2 c bus mode. table 19-2 relationship between signals and flags signal outputting definition conditions for effect to flag meaning of signal device outputting start condition master at falling edge of sda sets stt. sets std, clear transmitting the address when scl is in high level spd. to next, and indicates start of serial communication. stop condition master at falling edge of sda sets spt. sets both spd indicates end of the serial when scl is in high level and spcif, communication. clears both ackd and std. acknowledge master/slave after the reception has acke = 1 sets ackd. indicates 1 byte reception signal (ack) (receiver) been completed, the low has ended. level signal of sda output when 9th clock of scl is staying in high level. wait (wait) master/slave low level signal output to depends on the indicates that serial scl value of wtim bit communication is in disable state. serial clock master synchronous clock for sets csiif. note 2 synchronous signal of various signals output serial communication address master 7-bit data synchronizing indicates address value (a6 to a0) with scl after start to specify slave on the condition output serial bus transfer direction master 1-bit data synchronizing perform either data (r/w) with scl after address is transmission or reception output. data (d7 to d0) master/slave 8-bit data synchronizing indicates actual data for with scl which is not communicating immediately after entering start condition notes 1. when it is wait state, serial transmission is started after the wait state has been released. 2. for further details of timing for generation of a interrupt request, refer to table 19-1 intcsi generation timing and wait control. executes to write data to sio when ctxe = 1 (start instruction of serial transmission) note 1 489 user? manual u11316ej4v1ud chapter 20 clock output function the pd784038 has a clock function that outputs a signal scaled from the system clock. the clock output function can output the system clock directly, or a 1/2, 1/4, 1/8 or 1/16 system clock signal. in addition, it can be used as a 1-bit output port. the output pin has a dual function as the astb pin. caution this function cannot be used with the pd784031, and when the external memory extension mode is used. 20.1 configuration the clock output function configuration is shown in figure 20-1. figure 20-1 clock output function configuration f clk f clk /2 f clk /4 f clk /8 f clk /16 selector 2 output control selector 1 address latch signal reset astb/clkout clock output mode register (clom) lv 0 0 cle 0 fs2 fs1 fs0 chapter 20 clock output function 490 user s manual u11316ej4v1ud (1) clock output mode register (clom) register that controls the operation of the clock output function. (2) selector 1 selector that selects the frequency of the clock to be output. (3) output control controls the output signal in accordance with the contents of the clock output mode register (clom). (4) selector 2 selects either the astb signal or the clkout signal as the signal to be output to the astb/clkout pin. (5) astb/clkout pin pin that outputs the signal selected by selector 2. while the reset input is low, the astb/clo pin is in the hi-z state, and when the reset input becomes high it outputs a low-level signal, and then outputs a signal according to the set function. chapter 20 clock output function 491 user s manual u11316ej4v1ud 20.2 clock output mode register (clom) the clom controls the clock output function. clom can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the clom format is shown in figure 20-2. reset input clears the clom register to 00h. figure 20-2 clock output mode register (clom) format 7 lv clom 6 0 5 0 4 cle 3 0 2 fs2 1 fs1 0 fs0 frequency selection f clk note f clk /2 f clk /4 f clk /8 f clk /16 fs2 0 0 fs1 0 0 fs0 1 0 010 011 100 outputs lv bit contents outputs clock selected by bits fs2 to fs0 clock output control cle 1 0 outputs low level outputs high level output level control lv 1 0 address after reset r/w r/w 00h 0ffc6h note outputs the system clock duty 50 % cautions 1. with the pd784031, and when the external memory extension mode is used, the clock output mode register (clom) should be set to 00h (value after reset release). 2. the other bits (fs0 to fs2 and lv) must not be changed while the cle bit is set (to 1). 3. the other bits (fs0 to fs2 and lv) must not be changed at the same time when the cle bit is changed. chapter 20 clock output function 492 user s manual u11316ej4v1ud 20.3 operation 20.3.1 clock output a signal with the clock output frequency selected by bits fs0 to fs2 is selected by selector 1 and output. the output signal has the same level as the lv bit when the cle bit is cleared (to 0), and is output from the clock signal immediately after the cle bit is set (to 1). when the cle bit is cleared (to 0), the contents of the lv bit are output in synchronization with the clock signal, and further output operations are stopped. figure 20-3 clock output operation timing (a) lv = 0 f clk /n (n = 1, 2, 4, 8, 16) clkout cle (b) lv = 1 f clk /n (n = 1, 2, 4, 8, 16) cle clkout setting of bits fs0 to fs2 and the lv bit should only be performed when cle = 0 (bits fs0 to fs2 and the lv bit should not be changed within the same instruction that changes the cle bit contents). chapter 20 clock output function 493 user s manual u11316ej4v1ud 20.3.2 one-bit output port when the cle bit is cleared (to 0), the contents of the lv bit are output from the clkout pin. the clkout pin changes as soon as the contents of the lv bit change. figure 20-4 one-bit output port operation clkout set1 lv instruction executed clr1 lv instruction executed lv 20.3.3 operation in standby mode (1) halt mode the state prior to setting of the halt mode is maintained. that is, if, during clock output, clock output has been performed continuously, and clock output has been disabled, the lv bit contents set before the halt mode setting are output unchanged. (2) stop mode and idle mode clock output must be disabled before setting the stop mode or idle mode (this must be done by software). the clkout pin level output is the level before the stop mode or idle mode was set (the contents of the lv bit). 20.4 cautions (1) this function cannot be used with the pd784031, and when the external memory extension mode is used. (2) with the pd784031, and when the external memory extension mode is used, the clock output mode register (clom) should be set to 00h (value after reset release). (3) the other bits (fs0 to fs2 and lv) must not be changed while the cle bit is set (to 1). (4) the other bits (fs0 to fs2 and lv) must not be changed at the same time when the cle bit is changed. 494 user? manual u11316ej4v1ud chapter 21 edge detection function p20 to p26 have an edge detection function that allows a rising edge/falling edge to be set programmably, and the detected edge is sent to internal hardware. the relation between pins p20 to p26 and the use of the detected edge is shown in table 21-1. table 21-1 pins p20 to p26 and use of detected edge pin use detected edge specification register p20 nmi, standby circuit control intm0 p21 intp0, timer/counter 1 capture signal timer/counter 1 count clock signal real-time output port trigger signal p22 intp1, timer/counter 2 cr22 capture signal p23 intp2, ci (timer/counter 2 count clock signal), timer/counter 2 cr21 capture signal p24 intp3, timer/counter 0 capture signal intm1 timer/counter 0 count clock signal p25 intp4, standby circuit control p26 intp5, a/d converter conversion start signal, standby circuit control the edge detection function operates at all times except in stop mode and idle mode (although the edge detection function for pins p20, p25 and p26 also operates in stop mode and idle mode). for the p21/intp0 pin, the noise elimination time when edge detection is performed can be selected by software. 21.1 edge detection function control registers 21.1.1 external interrupt mode registers (intm0, intm1) the intmn (n = 0, 1) specify the valid edge to be detected on pins p20 to p26. the intm0 specifies the valid edge for pins p20 to p23, and the intm1 specifies the valid edge for pins p24 to p26. the intmn can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the format of intm0 and intm1 are shown in figures 21-1 and 21-2 respectively. reset input clears these registers to 00h. chapter 21 edge detection function 495 user? manual u11316ej4v1ud figure 21-1 external interrupt mode register 0 (intm0) format 7 es21 intm0 6 es20 5 es11 4 es10 3 es01 2 es00 1 0 0 esnmi falling edge rising edge p20 (nmi) pin input detected edge specification esnmi 1 0 falling edge rising edge p21 (intp0, cr11/cr11w capture trigger, tm1/tm1w count clock, real-time output port output trigger) pin input detected edge specification es01 0 0 setting prohibited 1 both falling & rising edges 1 es00 1 0 0 1 falling edge rising edge p22 (intp1, cr22/cr22w capture trigger) pin input detected edge specification es11 0 0 setting prohibited 1 both falling & rising edges 1 es10 1 0 0 1 falling edge rising edge p23 (intp2, cr21/cr21w capture trigger, ci) pin input detected edge specification es21 0 0 setting prohibited 1 both falling & rising edges 1 es20 1 0 0 1 address after reset r/w r/w 00h 0ffa0h chapter 21 edge detection function 496 user s manual u11316ej4v1ud figure 21-2 external interrupt mode register 1 (intm1) format 7 0 intm1 6 0 5 es51 4 es50 3 es41 2 es40 1 es31 0 es30 falling edge rising edge p24 (intp3, cr02 capture trigger, tm0 count clock) pin input detected edge specification es31 0 0 setting prohibited 1 both falling & rising edges 1 es30 1 0 0 1 falling edge rising edge p25 (intp4) pin input detected edge specification es41 0 0 setting prohibited 1 both falling & rising edges 1 es40 1 0 0 1 falling edge rising edge p26 (intp5, a/d conversion start signal) pin input detected edge specification es51 0 0 setting prohibited 1 both falling & rising edges 1 es50 1 0 0 1 address after reset r/w r/w 00h 0ffa1h caution valid edge detection cannot be performed when the valid edge is changed by a write to the external interrupt mode register (intmn: n = 0, 1). also, if an edge is input during a change of the valid edge, that edge may or may not be judged to be a valid edge. chapter 21 edge detection function 497 user s manual u11316ej4v1ud 21.1.2 sampling clock selection register (scs0) the scs0 specifies the sampling clock (f smp ) for digital noise elimination performed on pin p21. the scs0 can be read or written to with an 8-bit manipulation instruction. the format of scs0 is shown in figure 21- 3. reset input clears the scs0 register to 00h. figure 21-3 sampling clock selection register (scs0) format 7 0 scs0 6 0 5 0 4 0 3 0 2 0 1 scs01 0 scs00 f clk 3/f clk (188 ns) 4/f clk (250 ns) sampling clock (f smp ) pulse width eliminated as noise minimum pulse width recognized as signal scs01 scs00 0 0 f xx /64 192/f xx (6.0 s) 0 1 f xx /128 1 0 f xx /256 1 1 address after reset r/w r/w 00h 0ffa4h f xx = 32 mhz f clk = 16 mhz ? ? ? ? ? ? 384/f xx (12.0 s) 768/f xx (24.0 s) 256/f xx (8.0 s) 1,024/f xx (32.0 s) 512/f xx (16.0 s) chapter 21 edge detection function 498 user? manual u11316ej4v1ud 21.2 edge detection for pins p20, p25 and p26 on pins p20, p25 and p26, noise elimination is performed by means of analog delay before edge detection. therefore, an edge cannot be detected unless the pulse width is a given time (10 s) or longer. the width of the pulse eliminated as noise varies depending on the characteristics and ambient temperature of the device used. it is recommended to input a pulse with a width of 10 s or more to prevent the pulse from being eliminated as noise. figure 21-4 edge detection for pins p20, p25 and p26 p20/p25/p26 input p20/p25/p26 input signal after noise elimination falling edge rising edge short pulse eliminated as noise falling edge detected since pulse is sufficiently wide short pulse eliminated as a noise rising edge detected since pulse is sufficiently wide 10 s (min.) 10 s (max.) 10 s (max.) caution since analog delay noise elimination is performed on pins p20, p25 and p26, an edge is detected up to 10 s after it is actually input. also, unlike pins p21 to p24, the delay before an edge is detected is not a specific value, because of differences in the characteristics of various devices. chapter 21 edge detection function 499 user s manual u11316ej4v1ud 21.3 edge detection for pin p21 in p21 edge detection, digital noise elimination is performed using the clock (f smp ) specified by the sampling clock selection register (scs0). in digital noise elimination, input is sampled using the f smp clock, and if the input level is not the same at least four times in succession (if it is the same only three or fewer times in succession), it is eliminated as noi se. therefore, the level must be maintained for at least 4 f smp clock cycles in order to be recognized as a valid edge. remark when the pulse width of a signal with a comparatively long pulse width and a lot of noise, such as an infrared remote count reception signal, is measured, or when a signal is input in which oscillation occurs when an edge occurs, as with switch input chattering, for instance, it is better to set the sampling clock to low speed with the sampling clock selection register (scs0). if the sampling clock is high-speed, there will be a reaction to the short-pulse noise components as well, and the program will frequently have to judge whether the input is noise or a signal. however, by slowing down the sampling clock, reaction to short pulse width noise is eliminated and thus the program does not have to make judgments so frequently, and can thus be simplified. figure 21-5 p21 pin edge detection p21 input f smp p21 input signal after noise elimination rising edge falling edge digital noise elimination with f smp clock cautions 1. since digital noise elimination is performed with the f smp clock, there is a delay of 3 to 4 f smp clocks between input of an edge to the pin and the point at which the edge is actually detected. 2. if the input pulse width is 3 to 4 f smp clocks, it is uncertain whether a valid edge will be detected. therefore, to ensure reliable operation, the level should be held for at least 4 clocks. 3. if noise input to the pin is synchronized with the f smp clock in the pd784038, it may not be recognized as noise. if there is a possibility of such noise being input, noise should be eliminated by adding a filter to the input pin. chapter 21 edge detection function 500 user s manual u11316ej4v1ud 21.4 edge detection for pins p22 to p24 edge detection for pins p22 to p24 is performed after digital noise elimination by means of clock sampling. unlike the p21 pin, f clk is used as the sampling clock. in digital noise elimination, input is sampled using the f clk clock, and if the input level is not the same at least four times in succession (if it is the same only three or fewer times in succession), it is eliminated as noise. therefore, the level mus t be maintained for at least 4 f clk clock cycles (0.25 s: f clk = 16 mhz, f clk = 1/2 f xx , f xx = 32 mhz) in order to be recognized as a valid edge. figure 21-6 edge detection for pins p22 to p24 p22 to p24 input f clk p22 to p24 input signal after noise elimination rising edge falling edge digital noise elimination with f clk clock cautions 1. since digital noise elimination is performed with the f clk clock, there is a delay of 3 to 4 f clk clocks between input of an edge to the pin and the point at which the edge is actually detected. 2. if the input pulse width is 3 to 4 f clk clocks, it is uncertain whether a valid edge will be detected. therefore, to ensure reliable operation, the level should be held for at least 4 clocks. 3. if noise input to a pin is synchronized with the f clk clock in the pd784038, it may not be recognized as noise. if there is a possibility of such noise being input, noise should be eliminated by adding a filter to the input pins. chapter 21 edge detection function 501 user s manual u11316ej4v1ud 21.5 cautions (1) valid edge detection cannot be performed when the valid edge is changed by a write to the external interrupt mode register (intmn: n = 0, 1). also, if an edge is input during a change of the valid edge, that edge may or may not be judged to be a valid edge. (2) since analog delay noise elimination is performed on pins p20, p25 and p26, an edge is detected up to 10 s after it is actually input. also, unlike pins p21 to p24, the delay before an edge is detected is not a specific value, because of differences in the characteristics of various devices. (3) since digital noise elimination is performed on the p21 pin with the f smp clock, there is a delay of 3 to 4 f smp clocks between input of an edge to the pin and the point at which the edge is actually detected. (4) if the input pulse width on the p21 pin is 3 to 4 f smp clocks, it is uncertain whether a valid edge will be detected. therefore, to ensure reliable operation, the level should be held for at least 4 clocks. (5) if noise input of the p21 pin is synchronized with the f smp clock in the pd784038, it may not be recognized as noise. if there is a possibility of such noise being input, noise should be eliminated by adding a filter to the input pins. (6) since digital noise elimination is performed on pins p22 to p24 with the f clk clock, there is a delay of 3 to 4 f clk clocks between input of an edge to the pin and the point at which the edge is actually detected. (7) if the input pulse width on pins p22 to p24 is 3 to 4 f clk clocks, it is uncertain whether a valid edge will be detected. therefore, to ensure reliable operation, the level should be held for at least 4 clocks. (8) if noise input to pins p22 to p24 is synchronized with the f clk clock in the pd784038, it may not be recognized as noise. if there is a possibility of such noise being input, noise should be eliminated by adding a filter to the input pins. 502 user? manual u11316ej4v1ud chapter 22 interrupt functions the pd784038 is provided with three interrupt request service modes (see table 22-1 ). these three service modes can be set as required in the program. however interrupt service by macro service can only be selected for interrupt request sources provided with the macro service processing mode shown in table 22-2. context switching cannot be selected for non-maskable interrupts or operand error interrupts. multiple-interrupt control using 4 priority levels can easily be performed for maskable vectored interrupts. table 22-1 interrupt request service modes interrupt request servicing performed pc & psw contents service service mode vectored interrupts software saving to & restoration executed by branching to service program at from stack address note specified by vector table context switching saving to & restoration executed by automatic switching to register from fixed area in bank specified by vector table and branching register bank to service program at address note specified by fixed area in register bank macro service hardware retained execution of pre-set service such as data (firmware) transfers between memory and i/o note the start addresses of all interrupt service programs must be in the base area. if the body of a service program cannot be located in the base area, a branch instruction to the service program should be written in the base area. 22.1 interrupt request sources the pd784038 has the 25 interrupt request sources shown in table 22-2, with a vector table allocated to each. table 22-2 interrupt request sources (1/2) interrupt macro type of default interrupt request generating control context macro service vector interrupt priority generating source unit register switching service control table request name word address address software none brk instruction execution not not 3eh possible possible brkcs instruction execution possible not operand none invalid operand in mov stbc, not not 3ch error #byte instruction or mov wdm, possible possible #byte instruction, and location instruction non- none nmi (pin input edge detection) edge not not 2h maskable detection possible possible intwdt (watchdog timer watchdog not not 4h overflow) timer possible possible chapter 22 interrupt functions 503 user? manual u11316ej4v1ud table 22-2 interrupt request sources (2/2) interrupt macro type of default interrupt request generating control context macro service vector interrupt priority generating source unit register switching service control table request name word address address maskable 0 intp0 (pin input edge detection) edge pic0 possible possible 0fe06h 6h 1 intp1 (pin input edge detection) detection pic1 0fe08h 8h 2 intp2 (pin input edge detection) pic2 0fe0ah 0ah 3 intp3 (pin input edge detection) pic3 0fe0ch 0ch 4 intc00 (tm0-cr00 match signal timer/ cic00 0fe0eh 0eh generation) counter 0 5 intc01 (tm0-cr01 match signal cic01 0fe10h 10h generation) 6 intc10 (tm1-cr10 or tm1w- timer/ cic10 0fe12h 12h cr10w match signal generation) counter 1 7 intc11 (tm1-cr11 or tm1w- cic11 0fe14h 14h cr11w match signal generation) 8 intc20 (tm2-cr20 or tm2w- timer/ cic20 0fe16h 16h cr20w match signal generation) counter 2 9 intc21 (tm2-cr21 or tm2w- cic21 0fe18h 18h cr22w match signal generation) 10 intc30 (tm3-cr30 or tm3w- timer 3 cic30 0fe1ah 1ah cr30w match signal generation) 11 intp4 (pin input edge detection) edge pic4 0fe1ch 1ch 12 intp5 (pin input edge detection) detection pic5 0fe1eh 1eh 13 intad (a/d conversion end) a/d adic 0fe20h 20h converter 14 intser (asynchronous serial asynchro- seric not 0fe22h 22h interface receive error) nous possible 15 intsr (asynchronous serial serial sric possible 0fe24h 24h interface reception end) interface/ intcsi1 (clocked serial interface clocked csiic1 transfer end) serial 16 intst (asynchronous serial interface 1 stic 0fe26h 26h interface transmission end) 17 intcsi (clocked serial interface clocked csiic 0fe28h 28h transfer end) serial interface 18 intser2 (asynchronous serial asynchro- seric2 not 0fe2ah 2ah interface 2 receive error) nous possible 19 intsr2 (asynchronous serial serial sric2 possible 0fe2ch 2ch interface 2 reception end) interface 2/ intcsi2 (clocked serial interface 2 clocked csiic2 transfer end) serial 20 intst2 (asynchronous serial interface 2 stic2 0fe2eh 2eh interface 2 transmission end) 21 note intspc (i 2 c bus stop condition clocked spcic 0fe30h 30h interrupt) serial interface note pd784038y subseries only chapter 22 interrupt functions 504 user? manual u11316ej4v1ud remarks 1. the default priority is a fixed number. this indicates the order of priority when interrupt requests specified as having the same priority are generated simultaneously, 2. the intsr and intcsi1 interrupts are generated by the same hardware (they cannot both be used simultaneously). therefore, although the same hardware is used for the interrupts, two names are provided, for use in each of the two modes. the same applies to intsr2 and intcsi2. 22.1.1 software interrupts interrupts by software consist of the brk instruction which generates a vectored interrupt and the brkcs instruction which performs context switching. software interrupts are acknowledged even in the interrupt disabled state, and are not subject to priority control. 22.1.2 operand error interrupts these interrupts are generated if there is an illegal operand in an mov stbc, #byte instruction or mov wdmc, #byte instruction, and location instruction. operand error interrupts are acknowledged even in the interrupt disabled state, and are not subject to priority control. 22.1.3 non-maskable interrupts a non-maskable interrupt is generated by nmi pin input or the watchdog timer. non-maskable interrupts are acknowledged unconditionally note , even in the interrupt disabled state. they are not subject to interrupt priority control, and are of higher priority that any other interrupt. note except during execution of the service program for the same non-maskable interrupt, and during execution of the service program for a higher-priority non-maskable interrupt 22.1.4 maskable interrupts a maskable interrupt is one subject to masking control according to the setting of an interrupt mask flag. in addition, acknowledgment enabling/disabling can be specified for all maskable interrupts by means of the ie flag in the program status word (psw). in addition to normal vectored interruption, maskable interrupts can be acknowledged by context switching and macro service (though some interrupts cannot use macro service: see table 22-2 ). the priority order for maskable interrupt requests when interrupt requests of the same priority are generated simultaneously is predetermined (default priority) as shown in table 22-2. also, multiprocessing control can be performed with interrupt priorities divided into 4 levels. however, macro service requests are acknowledged without regard to priority control or the ie flag. chapter 22 interrupt functions 505 user? manual u11316ej4v1ud 22.2 interrupt service modes there are three pd784038 interrupt service modes, as follows: vectored interrupt service macro service context switching 22.2.1 vectored interrupt service when an interrupt is acknowledged, the program counter (pc) and program status word (psw) are automatically saved to the stack, a branch is made to the address indicated by the data stored in the vector table, and the interrupt service routi ne is executed. 22.2.2 macro service when an interrupt is acknowledged, cpu execution is temporarily suspended and a data transfer is performed by hardware. since macro service is performed without the intermediation of the cpu, it is not necessary to save or restore cpu statuses such as the program counter (pc) and program status word (psw) contents. this is therefore very effective in improving the cpu service time (see 22.8 macro service function ). 22.2.3 context switching when an interrupt is acknowledged, the prescribed register bank is selected by hardware, a branch is made to a pre- set vector address in the register bank, and at the same time the current program counter (pc) and program status word (psw) are saved in the register bank (see 22.4.2 brkcs instruction software interrupt (software context switching) acknowledgment operation and 22.7.2 context switching ). remark ?ontext?refers to the cpu registers that can be accessed by a program while that program is being executed. these registers include general registers, the program counter (pc), program status word (psw), and stack pointer (sp). chapter 22 interrupt functions 506 user? manual u11316ej4v1ud 22.3 interrupt service control registers pd784038 interrupt service is controlled for each interrupt request by various control registers that perform interrupt service specification. the interrupt control registers are listed in table 22-3. table 22-3 control registers register name symbol function interrupt control registers pic0 registers that perform each interrupt request generation recording, mask pic1 control, vectored interrupt service or macro service specification, context pic2 switching function enabling/disabling, and priority specification. pic3 cic00 cic01 cic10 cic11 cic20 cic21 cic30 pic4 pic5 adic seric sric csiic1 stic csiic seric2 sric2 csiic2 stic2 spcic note interrupt mask registers mk0 maskable interrupt request mask control mk1l linked to mask control flags in interrupt control registers word accesses or byte accesses possible in-service priority register ispr records priority of interrupt request currently being acknowledged interrupt mode control register imc controls nesting of maskable interrupts for which lowest priority level (level 3) is specified watchdog timer mode register wdm specifies priority of interrupts due to nmi pin input and interrupts due to watchdog timer overflow program status word psw specifies enabling/disabling of maskable interrupt acknowledgment note pd784038y subseries only an interrupt control register is allocated to each interrupt source. the flags of each register perform control of the content s corresponding to the relevant bit position in the register. the interrupt control register flag names corresponding to each interrupt request signal are shown in table 22-4. chapter 22 interrupt functions 507 user? manual u11316ej4v1ud table 22-4 interrupt control register flags corresponding to interrupt sources default interrupt interrupt control registers priority request interrupt interrupt macro service priority speci- context switching signal request flag mask flag enable flag fication flag enable flag 0 intp0 pic0 pif0 pmk0 pism0 ppr00 pcse0 ppr01 1 intp1 pic1 pif1 pmk1 pism1 ppr10 pcse1 ppr11 2 intp2 pic2 pif2 pmk2 pism2 ppr20 pcse2 ppr21 3 intp3 pic3 pif3 pmk3 pism3 ppr30 pcse3 ppr31 4 intc00 cic00 cif00 cmk00 cism00 cpr000 ccse00 cpr001 5 intc01 cic01 cif01 cmk01 cism01 cpr010 ccse01 cpr011 6 intc10 cic10 cif10 cmk10 cism10 cpr100 ccse10 cpr101 7 intc11 cic11 cif11 cmk11 cism11 cpr110 ccse11 cpr111 8 intc20 cic20 cif20 cmk20 cism20 cpr200 ccse20 cpr201 9 intc21 cic21 cif21 cmk21 cism21 cpr210 ccse21 cpr211 10 intc30 cic30 cif30 cmk30 cism30 cpr300 ccse30 cpr301 11 intp4 pic4 pif4 pmk4 pism4 ppr40 pcse4 ppr41 12 intp5 pic5 pif5 pmk5 pism5 ppr50 pcse5 ppr51 13 intad adic adif admk adism adpr0 adcse adpr1 14 intser seric serif sermk serpr0 sercse serpr1 15 intsr sric srif srmk srism srpr0 srcse srpr1 intcsi1 csiic1 csiif1 csimk1 csiism1 csipr10 csicse1 csipr11 16 intst stic stif stmk stism stpr0 stcse stpr1 17 intcsi csiic csiif csimk csiism csipr0 csicse csipr1 18 intser2 seric2 serif2 sermk2 serpr20 sercse2 serpr21 19 intsr2 sric2 srif2 srmk2 srism2 srpr20 srcse2 srpr21 intcsi2 csiic2 csiif2 csimk2 csiism2 csipr20 csicse2 csipr21 20 intst2 stic2 stif2 stmk2 stism2 stpr20 stcse2 serpr21 21 note intspc spcic spcif spcmk spcism spcpr0 spccse spcpr1 note pd784038y subseries only chapter 22 interrupt functions 508 user? manual u11316ej4v1ud 22.3.1 interrupt control registers an interrupt control register is allocated to each interrupt source, and performs priority control, mask control, etc. for the corresponding interrupt request. the interrupt control register format is shown in figure 22-1. (1) priority specification flags ( pr1/ pr0) the priority specification flags specify the priority on an individual interrupt source basis for the 21 (22 types for the pd784038y subseries) maskable interrupts. up to 4 priority levels can be specified, and a number of interrupt sources can be specified at the same level. among maskable interrupt sources, level 0 is the highest priority. if multiple interrupt requests are generated simultaneously among interrupt source of the same priority level, they are acknowledged in default priority order. these flags can be manipulated bit-wise by software. reset input sets all bits to ?? (2) context switching enable flag ( cse) the context switching enable flag specifies that a maskable interrupt request is to be serviced by context switching. in context switching, the register bank specified beforehand is selected by hardware, a branch is made to a vector address stored beforehand in the register bank, and at the same time the current contents of the program counter (pc) and program status word (psw) are saved in the register bank. context switching is suitable for real-time processing, since execution of interrupt servicing can be started faster than with normal vectored interrupt servicing. this flag can be manipulated bit-wise by software. reset input sets all bits to ?? (3) macro service enable flag ( ism) the macro service enable flag specifies whether an interrupt request corresponding to that flag is to be handled by vectored interruption or context switching, or by macro service. when macro service processing is selected, at the end of the macro service (when the macro service counter reaches 0) the macro service enable flag is automatically cleared (to 0) by hardware (vectored interrupt service/context switching service). this flag can be manipulated bit-wise by software. reset input sets all bits to ?? (4) interrupt mask flag ( mk) an interrupt mask flag specifies enabling/disabling of vectored interrupt servicing and macro service processing for the interrupt request corresponding to that flag. the interrupt mask contents are not changed by the start of interrupt service, etc., and are the same as the interrupt mask register contents (see 22.3.2 interrupt mask registers (mk0/mk1l) ). macro service processing requests are also subject to mask control, and macro service requests can also be masked with this flag. this flag can be manipulated by software. reset input sets all bits to ?? (5) interrupt request flag ( if) an interrupt request flag is set (to 1) by generation of the interrupt request that corresponds to that flag. when the interrupt is acknowledged, the flag is automatically cleared (to 0) by hardware. this flag can be manipulated by software. reset input sets all bits to ?? chapter 22 interrupt functions 509 user? manual u11316ej4v1ud figure 22-1 interrupt control registers ( icn) (1/3) 7 pif0 pic0 6 pmk0 5 pism0 4 pcse0 3 0 2 0 1 ppr01 0 ppr00 interrupt request priority specification priority 0 (highest priority) priority 1 priority 2 priority 3 prn1 (bit 1) 0 0 prn0 (bit 0) 1 0 10 11 context switching servicing specification serviced by vectored interruption serviced by context switching csen (bit 4) 0 1 interrupt service mode specification vectored interruption servicing/ context switching servicing macro servicing ismn (bit 5) 0 1 interrupt service enabling/disabling interrupt service enabled interrupt service disabled mkn (bit 6) 0 1 interrupt request generation presence/absence no interrupt request (interrupt signal not being generated) interrupt request state (interrupt signal being generated) ifn (bit 7) 0 1 address after reset r/w r/w 43h 0ffe0h pif1 pic1 pmk1 pism1 pcse1 0 0 ppr11 ppr10 r/w 43h 0ffe1h pif2 pic2 pmk2 pism2 pcse2 0 0 ppr21 ppr20 r/w 43h 0ffe2h pif3 pic3 pmk3 pism3 pcse3 0 0 ppr31 ppr30 r/w 43h 0ffe3h cif00 cic00 cmk00 cism00 ccse00 0 0 cpr001 cpr000 cif01 cmk01 cism01 ccse01 0 0 cpr011 cpr010 cif10 cmk10 cism10 ccse10 0 0 cpr101 cpr100 cif11 cmk11 cism11 ccse11 0 0 cpr111 cpr110 r/w 43h 0ffe4h cic01 r/w 43h 0ffe5h cic10 r/w 43h 0ffe6h cic11 r/w 43h 0ffe7h chapter 22 interrupt functions 510 user s manual u11316ej4v1ud figure 22-1 interrupt control registers ( icn) (2/3) 7 cif20 cic20 6 cmk20 5 cism20 4 ccse20 3 0 2 0 1 cpr201 0 cpr200 interrupt request priority specification priority 0 (highest priority) priority 1 priority 2 priority 3 prn1 (bit 1) 0 0 prn0 (bit 0) 1 0 10 11 context switching servicing specification serviced by vectored interruption serviced by context switching csen (bit 4) 0 1 interrupt service mode specification vectored interruption servicing/ context switching servicing macro servicing ismn (bit 5) 0 1 interrupt service enabling/disabling interrupt service enabled interrupt service disabled mkn (bit 6) 0 1 interrupt request generation presence/absence no interrupt request (interrupt signal not being generated) interrupt request state (interrupt signal being generated) ifn (bit 7) 0 1 address after reset r/w r/w 43h 0ffe8h cif21 cic21 cmk21 cism21 ccse21 0 0 cpr211 cpr210 r/w 43h 0ffe9h cif30 cic30 cmk30 cism30 ccse30 0 0 cpr301 cpr300 r/w 43h 0ffeah pif4 pic4 pmk4 pism4 pcse4 0 0 ppr41 ppr40 r/w 43h 0ffebh pif5 pic5 pmk5 pism5 pcse5 0 0 ppr51 ppr50 r/w 43h 0ffech adif adic admk adism adcse 0 0 adpr1 adpr0 r/w 43h 0ffedh serif seric sermk 0 sercse 0 0 serpr1 serpr0 r/w 43h 0ffeeh srif sric srmk srism srcse 0 0 srpr1 srpr0 r/w 43h 0ffefh chapter 22 interrupt functions 511 user s manual u11316ej4v1ud figure 22-1 interrupt control registers ( icn) (3/3) 7 csiif1 csiic1 6 csimk1 5 csiism1 4 csicse1 3 0 2 0 1 csipr11 0 csipr10 interrupt request priority specification priority 0 (highest priority) priority 1 priority 2 priority 3 prn1 (bit 1) 0 0 prn0 (bit 0) 1 0 10 11 context switching servicing specification serviced by vectored interruption serviced by context switching csen (bit 4) 0 1 interrupt service mode specification vectored interruption servicing/ context switching servicing macro servicing ismn (bit 5) 0 1 interrupt service enabling/disabling interrupt service enabled interrupt service disabled mkn (bit 6) 0 1 interrupt request generation presence/absence no interrupt request (interrupt signal not being generated) interrupt request state (interrupt signal being generated) ifn (bit 7) 0 1 address after reset r/w r/w 43h 0ffefh stif stic stmk stism stcse 0 0 stpr1 stpr0 r/w 43h 0fff0h csiif csiic csimk csiism csicse 0 0 csipr1 csipr0 r/w 43h 0fff1h serif2 seric2 sermk2 0 sercse2 00 serpr21 serpr20 r/w 43h 0fff2h srif2 sric2 srmk2 srism2 srcse2 0 0 srpr21 srpr20 csiif2 csimk2 csiism2 csicse2 0 0 csipr21 csipr20 stif2 stmk2 stism2 stcse2 0 0 stpr21 stpr20 r/w 43h 0fff3h csiic2 r/w 43h 0fff3h stic2 r/w 43h 0fff4h spcif spcmk spcism spccse 0 0 spcpr1 spcpr0 spcic note r/w 43h 0fff5h note pd784038y subseries only chapter 22 interrupt functions 512 user s manual u11316ej4v1ud 22.3.2 interrupt mask registers (mk0/mk1l) the mk0 and mk1l are composed of interrupt mask flags. mk0 is a 16-bit register which can be manipulated as 8- bit units, mk0l and mk0h, as well as being manipulated as a 16-bit unit. mk1l is an 8-bit register that can be manipulated as an 8-bit unit. in addition, each bit of the mk0 and mk1l can be manipulated individually with a bit manipulation instruction. each interrupt mask flag controls enabling/disabling of the corresponding interrupt request. when an interrupt mask flag is set (to 1), acknowledgment of the corresponding interrupt request is disabled. when an interrupt mask flag is cleared (to 0), the corresponding interrupt request can be acknowledged as a vectored interrupt or macro service request. each interrupt mask flag in the mk0 and mk1l is the same flag as the interrupt mask flag in the interrupt control register. the mk0 and mk1l are provided for en bloc control of interrupt masking. after reset input, the mk0 is set to ffffh, the mk1l is set to ffh, and all maskable interrupts are disabled. figure 22-2 interrupt mask register (mk0, mk1l) format (1) byte accesses cmk11 mk0l cmk10 cmk01 cmk00 pmk3 pmk2 pmk1 pmk0 address after reset r/w r/w ffh 0ffach csimk1 srmk csimk2 srmk2 mk0h sermk admk pmk5 pmk4 cmk30 cmk21 cmk20 r/w ffh 0ffadh 1 mk1l 1 1 note stmk2 sermk2 csimk stmk r/w ffh 0ffaeh interrupt request enabling/disabling specification interrupt service enabled interrupt service disabled mk 0 1 7654 3 21 0 note spcmk when the pd784038y subseries is used (2) word accesses 7 cmk11 mk0 6 cmk10 5 cmk01 4 cmk00 3 pmk3 2 pmk2 1 pmk1 0 pmk0 interrupt request enabling/disabling specification interrupt service enabled interrupt service disabled mk 0 1 15 14 13 12 11 10 9 8 address after reset r/w r/w ffffh 0ffach csimk1 srmk sermk admk pmk5 pmk4 cmk30 cmk21 cmk20 chapter 22 interrupt functions 513 user s manual u11316ej4v1ud 22.3.3 in-service priority register (ispr) the ispr shows the priority level of the maskable interrupt currently being serviced and the non-maskable interrupt being serviced. when a maskable interrupt request is acknowledged, the bit corresponding to the priority of that interrupt request is set (to 1), and remains set until the service program ends. when a non-maskable interrupt is acknowledged, the bit corresponding to the priority of that non-maskable interrupt is set (to 1), and remains set until the service program ends. when an reti instruction or retcs instruction is executed, the bit, among those set (to 1) in the ispr, that corresponds to the highest-priority interrupt request is automatically cleared (to 0) by hardware. the contents of the ispr are not changed by execution of an retb or retcsb instruction. reset input clears the ispr register to 00h. figure 22-3 in-service priority register (ispr) format 7 nmis ispr 6 wdts 5 0 4 0 3 ispr3 2 ispr2 1 ispr1 0 ispr0 priority level priority n interrupt not being acknowledged priority n interrupt being acknowledged (n = 0 to 3) isprn 1 0 nmi service state nmi interrupt not being acknowledged nmi interrupt being acknowledged nmis 1 0 watchdog timer interrupt service state watchdog timer interrupt not being acknowledged watchdog timer interrupt being acknowledged wdts 1 0 address after reset r/w r 00h 0ffa8h caution in-service priority register (ispr) is a read-only register. there is a risk of malfunction if a write is performed on this register. chapter 22 interrupt functions 514 user s manual u11316ej4v1ud 22.3.4 interrupt mode control register (imc) the imc contains the prsl flag. the prsl flag specifies enabling/disabling of nesting of maskable interrupts for which the lowest priority level (level 3) is specified. when the imc is manipulated, the interrupt disabled state (di state) should be set first to prevent malfunction. the imc can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. reset input sets the imc register to 80h. figure 22-4 interrupt mode control register (imc) format 7 prsl imc 6 0 5 0 4 0 3 0 2 0 1 0 0 0 control of nesting operations for maskable interrupts (lowest level) nesting between interrupts set as level 3 (lowest level) enabled nesting between interrupts set as level 3 (lowest level) disabled prsl 1 0 address after reset r/w r/w 80h 0ffaah chapter 22 interrupt functions 515 user? manual u11316ej4v1ud 22.3.5 watchdog timer mode register (wdm) the prc bit of the wdm specifies the priority of nmi pin input non-maskable interrupts and watchdog timer overflow non-maskable interrupts. the wdm can be written to only by a dedicated instruction. this dedicated instruction, mov wdm, #byte, has a special code configuration (4 bytes), and a write is not performed unless the 3rd and 4th bytes of the operation code are mutual 1? complements. if the 3rd and 4th bytes of the operation code are not 1? complements, a write is not performed and an operand error interrupt is generated. in this case, the return address saved in the stack area is the address of the instruction that was the source of the error, and thus the address that was the source of the error can be identified from the return address saved in the stack area. if recovery from an operand error is simply performed by means of an retb instruction, an endless loop will result. as an operand error interrupt is only generated in the event of an inadvertent program loop (with the nec electronics assembler, ra78k4, only the correct dedicated instruction is generated when mov wdm, #byte is written), system initialization should be performed by the program. other write instructions (?ov wdm, a? ?nd wdm, #byte? ?et1 wdm.7? etc.) are ignored and do not perform any operation. that is, a write is not performed to the wdm, and an interrupt such as an operand error interrupt is not generated. the wdm can be read at any time by a data transfer instruction. reset input clears the wdm register to 00h. figure 22-5 watchdog timer mode register (wdm) format 7 run wdm 6 0 5 0 4 prc 3 0 2 wdi2 1 wdi1 0 0 watchdog timer interrupt request priority specification watchdog timer interrupt request < nmi pin input interrupt request watchdog timer interrupt request > nmi pin input interrupt request prc 1 0 address after reset r/w r/w 00h 0ffc2h see figure 12-2 in chapter 12 watchdog timer function for details. caution the watchdog timer mode register (wdm) can only be written to with a dedicated instruction (mov wdm, #byte). chapter 22 interrupt functions 516 user s manual u11316ej4v1ud 22.3.6 program status word (psw) the psw is a register that holds the current status regarding instruction execution results and interrupt requests. the ie flag that sets enabling/disabling of maskable interrupts is mapped in the low-order 8 bits of the psw (pswl). pswl can be read or written to with an 8-bit manipulation instruction, and can also be manipulated with a bit manipulation instruction or dedicated instruction (ei/di). when a vectored interrupt is acknowledged or a brk instruction is executed, pswl is saved to the stack and the ie flag is cleared (to 0). pswl is also saved to the stack by the push psw instruction, and is restored from the stack by the reti, retb and pop psw instructions. when context switching or a brkcs instruction is executed, pswl is saved to a fixed area in the register bank, and the ie flag is cleared (to 0). pswl is restored from the fixed area in the register bank by an retcsi or retcsb instruction. reset input clears pswl to 00h. figure 22-6 program status word (pswl) format 7 s pswl 6 z 5 rss 4 ac 3 ie 2 p/v 1 0 0 cy after reset 00h ie interrupt acknowledgment enabling/disabling disabled enabled 1 0 used in normal instruction execution 22.4 software interrupt acknowledgment operations a software interrupt is acknowledged in response to execution of a brk or brkcs instruction. software interrupts cannot be disabled. 22.4.1 brk instruction software interrupt acknowledgment operation when a brk instruction is executed, the program status word (psw), program counter (pc) are saved in that order to the stack, the ie flag is cleared (to 0), the vector table (003eh/003fh) contents are loaded into the low-order 16 bits of the pc, and 0000b into the high-order 4 bits, and a branch is performed (the start of the service program must be in the base area). the retb instruction must be used to return from a brk instruction software interrupt. caution the reti instruction must not be used to return from a brk instruction software interrupt. chapter 22 interrupt functions 517 user s manual u11316ej4v1ud 22.4.2 brkcs instruction software interrupt (software context switching) acknowledgment operation the context switching function can be initiated by executing a brkcs instruction. the register bank to be used after context switching is specified by the brkcs instruction operand. when a brkcs instruction is executed, the program branches to the start address of the interrupt service program (which must be in the base area) stored beforehand in the specified register bank, and the contents of the program status word (psw) and program counter (pc) are saved in the register bank. figure 22-7 context switching operation by execution of a brkcs instruction register bank (0 to 7) a b r5 r7 x c r4 r6 d h vp up e l v u t w register bank n (n = 0 to 7) 7 transfer 3 register bank switching (rsb0-rsb2 n) 4 rss 0 ( ie 0 ) 1 save 2 save (bits 8 to 11 of temporary register) 6 exchange 5 save pc 15-0 pc 19-16 0000b temporary register psw the retcsb instruction is used to return from a software interrupt due to a brkcs instruction. the retcsb instruction must specify the start address of the interrupt service program for the next time context switching is performed by a brkcs instruction. this interrupt service program start address must be in the base area. caution the retcs instruction must not be used to return from a brkcs instruction software interrupt. chapter 22 interrupt functions 518 user s manual u11316ej4v1ud figure 22-8 return from brkcs instruction software interrupt (retcsb instruction operation) pc 19-16 pc 15-0 1 restoration 3 transfer 4 restoration (to original register bank) 2 restoration psw vvp uup te wl retcsb instruction operand register bank n (n = 0 to 7) a r5 r7 d h b x r4 r6 c 22.5 operand error interrupt acknowledgment operation an operand error interrupt is generated when the data obtained by inverting all the bits of the 3rd byte of the operand of an mov stbc, #byte instruction or location instruction or an mov wdm,#byte instruction does not match the 4th byte of the operand. operand error interrupts cannot be disabled. when an operand error interrupt is generated, the program status word (psw) and the start address of the instruction that caused the error are saved to the stack, the ie flag is cleared (to 0), the vector table value is loaded into the program counter (pc), and a branch is performed (within the base area only). as the address saved to the stack is the start address of the instruction in which the error occurred, simply writing an retb instruction at the end of the operand error interrupt service program will result in generation of another operand error interrupt. you should therefore either process the address in the stack or initialize the program by referring to 22.12 restoring interrupt function to initial state . chapter 22 interrupt functions 519 user s manual u11316ej4v1ud 22.6 non-maskable interrupt acknowledgment operation non-maskable interrupts are acknowledged even in the interrupt disabled state. non-maskable interrupts can be acknowledged at all times except during execution of the service program for an identical non-maskable interrupt or a non- maskable interrupt of higher priority. the relative priorities of non-maskable interrupts are set by the prc bit of the watchdog timer mode register (wdm) (see 22.3.5 watchdog timer mode register (wdm) ). except in the cases described in 22.9 when interrupt requests and macro service are temporarily held pending , a non-maskable interrupt request is acknowledged immediately. when a non-maskable interrupt request is acknowledged, the program status word (psw) and program counter (pc) are saved in that order to the stack, the ie flag is cleared (to 0), the in-service priority register (ispr) bit corresponding to the acknowledged non-maskable interrupt is set (to 1), the vector table contents are loaded into the pc, and a branch is performed. the ispr bit that is set (to 1) is the nmis bit in the case of a non-maskable interrupt due to edge input to the nmi pin, and the wdts bit in the case of watchdog timer overflow. when the non-maskable interrupt service program is executed, non-maskable interrupt requests of the same priority as the non-maskable interrupt currently being executed and non-maskable interrupts of lower priority than the non-maskable interrupt currently being executed are held pending. a pending non-maskable interrupt is acknowledge after completion of the non-maskable interrupt service program currently being executed (after execution of the reti instruction). however, even if the same non-maskable interrupt request is generated more than once during execution of the non-maskable interrupt service program, only one non-maskable interrupt is acknowledged after completion of the non-maskable interrupt service program. chapter 22 interrupt functions 520 user s manual u11316ej4v1ud figure 22-9 non-maskable interrupt request acknowledgment operations (1/2) (a) when a new nmi request is generated during nmi service program execution main routine nmi request nmi request (nmis = 1) nmi request held pending since nmis = 1 pending nmi request is serviced (b) when a watchdog timer interrupt request is generated during nmi service program execution (when the watchdog timer interrupt priority is higher (when prc in the wdm = 1)) main routine nmi request watchdog timer interrupt request chapter 22 interrupt functions 521 user s manual u11316ej4v1ud figure 22-9 non-maskable interrupt request acknowledgment operations (2/2) (c) when a watchdog timer interrupt request is generated during nmi service program execution (when the nmi interrupt priority is higher (when prc in the wdm = 0)) main routine nmi request watchdog timer interrupt request watchdog timer interrupt is kept pending because prc = 0 pending watchdog timer interrupt is processed (d) when an nmi request is generated twice during nmi service program execution main routine nmi request nmi request held pending since nmi service program is being executed nmi request held pending since nmi service program is being executed nmi request was generated more than once, but is only acknowledged once chapter 22 interrupt functions 522 user s manual u11316ej4v1ud cautions 1. macro service requests are acknowledged and serviced even during execution of a non-maskable interrupt service program. if you do not want macro service processing to be performed during a non-maskable interrupt service program, you should manipulate the interrupt mask register in the non-maskable interrupt service program to prevent macro service generation. 2. the reti instruction must be used to return from a non-maskable interrupt. subsequent interrupt acknowledgment will not be performed normally if a different instruction is used. to resume program execution from the initial state after the non-maskable interrupt has been acknowledged, see 22.12 restoring interrupt function to initial state. 3. non-maskable interrupts are always acknowledged, except during non-maskable interrupt service program execution (except when a high non-maskable interrupt request is generated during execution of a low-priority non-maskable interrupt service program) and for a certain period after execution of the special instructions shown in 22.9. therefore, a non-maskable interrupt will be acknowledged even when the stack pointer (sp) value is undefined, in particular after reset release, etc. in this case, depending on the value of the sp, it may happen that the program counter (pc) and program status word (psw) are written to the address of a write-inhibited special function register (sfr) (see table 3.5 in 3.9 special function registers (sfr)), and the cpu becomes deadlocked, or an unexpected signal is output from a pin, or the pc and psw are written to an address in which ram is not mounted, with the result that the return from the non-maskable interrupt service program is not performed normally and a software upsets occurs. therefore, the program following reset release must be as shown below. cseg at 0 dw strt cseg base strt: location 0fh ; or location 0h movg sp, #imm24 chapter 22 interrupt functions 523 user s manual u11316ej4v1ud 22.7 maskable interrupt acknowledgment operation a maskable interrupt can be acknowledged when the interrupt request flag is set (to 1) and the mask flag for that interrupt is cleared (to 0). when servicing is performed by macro service, the interrupt is acknowledged and serviced by macro service immediately. in the case of vectored interrupt and context switching, an interrupt is acknowledged in the interrupt enabled state (when the ie flag is set (to 1)) if the priority of that interrupt is one for which acknowledgment is permitted. if maskable interrupt requests are generated simultaneously, the interrupt for which the highest priority is specified by the priority specification flag is acknowledged. if the interrupts have the same priority specified, they are acknowledged in accordance with their default priorities. a pending interrupt is acknowledged when a state in which it can be acknowledged is established. the interrupt acknowledgment algorithm is shown in figure 22-10. chapter 22 interrupt functions 524 user s manual u11316ej4v1ud figure 22-10 interrupt acknowledgment processing algorithm no if = 1 mk = 0 ism = 1 cse = 1 ie = 1 higher priority than interrupt currently being serviced? higher priority than other existing interrupt requests? highest default priority among interrupt requests of same priority? vectored interrupt generation interrupt request? yes no interrupt mask released? yes no yes yes yes yes no no interrupt enabled state? macro service? no no no interrupt request held pending yes context switching? context switching generation yes highest default priority among macro service requests? macro service processing execution interrupt request held pending no yes chapter 22 interrupt functions 525 user s manual u11316ej4v1ud 22.7.1 vectored interruption when a vectored interruption maskable interrupt request is acknowledged, the program status word (psw) and program counter (pc) are saved in that order to the stack, the ie flag is cleared (to 0) (the interrupt disabled state is set), and the in-service priority register (ispr) bit corresponding to the priority of the acknowledged interrupt is set (to 1). also, data in the vector table predetermined for each interrupt request is loaded into the pc, and a branch is performed. the return from a vectored interrupt is performed by means of the reti instruction. caution when a maskable interrupt is acknowledged by vectored interruption, the reti instruction must be used to return from the interrupt. subsequent interrupt acknowledgment will not be performed normally if a different instruction is used. 22.7.2 context switching initiation of the context switching function is enabled by setting (to 1) the context switching enable flag of the interrupt control register. when an interrupt request for which the context switching function is enabled is acknowledged, the register bank specified by 3 bits of the lower address (even address) of the corresponding vector table address is selected. the vector address stored beforehand in the selected register bank is transferred to the program counter (pc), and at the same time the contents of the pc and program status word (psw) up to that time are saved in the register bank and a branch is made to the interrupt service program. figure 22-11 context switching operation by generation of an interrupt request register bank (0 to 7) a b r5 r7 x c r4 r6 d h vp up e l v u t w register bank n (n = 0 to 7) 7 transfer 6 exchange 4 2 save (temporary register bit 8-11) 5 save 1 save pc 15-0 pc 19-16 0000b temporary register psw n 3 register bank switching (rsb0-rsb2 n) vector table rss 0 ( ie 0 ) chapter 22 interrupt functions 526 user s manual u11316ej4v1ud the retcs instruction is used to return from an interrupt that uses the context switching function. the retcs instruction must specify the start address of the interrupt service program to be executed when that interrupt is acknowledged next. this interrupt service program start address must be in the base area. caution the retcs instruction must be used to return from an interrupt serviced by context switching. subsequent interrupt acknowledgment will not be performed normally if a different instruction is used. figure 22-12 return from interrupt that uses context switching by means of retcs instruction pc 19-16 pc 15-0 2 restoration 4 restoration (to original register bank) psw retcs instruction operand 3 transfer register bank n (n = 0 to 7) vvp uup tde wh l ax r5 r4 r7 r6 bc 1 restoration chapter 22 interrupt functions 527 user s manual u11316ej4v1ud 22.7.3 maskable interrupt priority levels the pd784038 performs multiple interrupt servicing in which an interrupt is acknowledged during servicing of another interrupt. multiple interrupts can be controlled by priority levels. there are two kinds of priority control, control by default priority and programmable priority control in accordance with the setting of the priority specification flag. in priority control by means of default priority, interrupt service is perform ed in accordance with the priority preassigned to each interrupt request (default priority) (see table 22-2 ). in programmable priority control, interrupt requests are divided into four levels according to the setting of the priority specification flag. interrupt requests for which multiple interruption is permitted are shown in table 22-5. since the ie flag is cleared (to 0) automatically when an interrupt is acknowledged, when multiple interruption is used, the ie flag should be set (to 1) to enable interrupts by executing an ei instruction in the interrupt service program, etc. table 22-5 multiple interrupt servicing priority of interrupt currently ispr value ie flag in psw prsl in acknowledgeable maskable interrupts being acknowledged imc register no interrupt being 00000000 0 all macro service only acknowledged 1 all maskable interrupts 3 00001000 0 all macro service only 10 all maskable interrupts 11 all macro service maskable interrupts specified as priority 0/1/2 2 0000 100 0 all macro service only 1 all macro service maskable interrupts specified as priority 0/1 1 0000 10 0 all macro service only 1 all macro service maskable interrupts specified as priority 0 0 0000 1 all macro service only non-maskable interrupts 1000 all macro service only 0100 1100 chapter 22 interrupt functions 528 user s manual u11316ej4v1ud figure 22-13 examples of servicing when another interrupt request is generated during interrupt service (1/3) main routine ei ei ei interrupt request a (level 3) interrupt request b (level 2) interrupt request d (level 2) interrupt request e (level 2) interrupt request f (level 3) interrupt request g (level 1) a servicing b servicing c servicing d servicing e servicing f servicing g servicing h servicing since interrupt request b has a higher priority than interrupt request a, and interrupts are enabled, interrupt request b is acknowledged. the priority of interrupt request d is higher than that of interrupt request c, but since interrupts are disabled, interrupt request d is held pending. although interrupts are enabled, interrupt request f is held pending since it has a lower priority than interrupt request e. although interrupts are enabled, interrupt request h is held pending since it has the same priority as interrupt request g. interrupt request h (level 1) ei interrupt request c (level 3) chapter 22 interrupt functions 529 user s manual u11316ej4v1ud figure 22-13 examples of servicing when another interrupt request is generated during interrupt service (2/3) main routine ei ei interrupt request i (level 1) interrupt request k (level 2) interrupt request n (level 2) macro service request j (level 2) i servicing j macro service k servicing l servicing m servicing n servicing o servicing p servicing the macro service request is serviced irrespective of interrupt enabling/disabling and priority. the interrupt request is held pending since it has a lower priority than interrupt request k. interrupt request m generated after interrupt request l has a higher priority, and is therefore acknowledged first. since servicing of interrupt request n performed in the interrupt disabled state, interrupt requests o and p are held pending. after interrupt request n servicing, the pending interrupt requests are acknowledged. although interrupt request o was generated first, interrupt request p has a higher priority and is therefore acknowledged first. interrupt request l (level 3) interrupt request m (level 1) interrupt request o (level 3) interrupt request p (level 1) chapter 22 interrupt functions 530 user s manual u11316ej4v1ud figure 22-13 examples of servicing when another interrupt request is generated during interrupt service (3/3) main routine ei ei ei ei ei ei interrupt request q level 3) interrupt request s (level 1) interrupt request u (level 0) w macro service q servicing r servicing s servicing t servicing u servicing v servicing x servicing y servicing z servicing interrupt request x (level 1) interrupt request r (level 2) interrupt request t (level 0) note 1 note 2 multiple acknowledgment of levels 3 to 0. if the prsl bit of the imc register is set (to 1), only macro service requests and non- maskable interrupts generate nesting beyond this. if the prsl bit of the imc register is cleared (to 0), level 3 interrupts can also be nested during level 3 interrupt servicing (see figure 22-15). <1>: interrupt request v (level 0) <2>: macro service request w (level 3) even though the interrupt enabled state is set during servicing of level 0 interrupt request u, the interrupt request is not acknowledged but held pending even though its priority is 0. however, the macro service request is acknowledged and serviced irrespective of its level and even though there is a pending interrupt with a higher priority level. <3>: interrupt request y (level 2) <4>: interrupt request z (level 2) pending interrupt requests y and z are acknowledged after servicing of interrupt request x. as interrupt requests y and z have the same priority level, interrupt request z which has the higher default priority is acknowledged first, irrespective of the order in which the interrupt requests were generated. <1> <2> <4> <3> notes 1. low default priority 2. high default priority remarks 1. a to z in the figure are arbitrary names used to differentiate between the interrupt requests and macro service requests. 2. high/low default priorities in the figure indicate the relative priority levels of the two interrupt requests. chapter 22 interrupt functions 531 user? manual u11316ej4v1ud figure 22-14 examples of servicing of simultaneously generated interrupts main routine ei interrupt request a (level 2) macro service request b (level 3) macro service request c (level 1) interrupt request d (level 1) interrupt request e (level 1) macro service request f (level 1) default priority order a > b > c > d > e > f macro service request b servicing macro service request c servicing macro service request f servicing interrupt request d servicing interrupt request e servicing interrupt request a servicing ? when requests are generated simultaneously, they are acknowledged in order starting with macro service. ? macro service requests are acknowledged in default priority order (b/c/f) (not dependent upon the programmable priority order). ? as interrupt requests are acknowledged in high-to-low priority level order, d and e are acknowledged first. ? as d and e have the same priority level, the interrupt request with the higher default priority, d, is acknowledged first. remark a to f in the figure are arbitrary names used to differentiate between the interrupt requests and macro service requests. chapter 22 interrupt functions 532 user s manual u11316ej4v1ud figure 22-15 differences in level 3 interrupt acknowledgment according to imc register setting main routine ei ei interrupt request a (level 3) interrupt request b (level 3) a servicing b servicing interrupt request c (level 3) interrupt request d (level 3) c servicing d servicing interrupt request e note 1 (level 3) interrupt request f note 2 (level 3) f servicing e servicing imc 80h ei main routine imc 00h ei main routine ei ei the prsl bit of the imc is set to 1, and nesting between level 3 interrupts is disabled. even though interrupts are enabled, interrupt request b is held pending since it has the same priority as interrupt request a. the prsl bit of the imc is set to 0, so that a level 3 interrupt is acknowledged even during level 3 interrupt servicing (nesting is possible). since level 3 interrupt request c is being serviced in the interrupt enabled state and prsl = 0, interrupt request d, which is also level 3, is acknowledged. as interrupt request 3 and f are both of the same level, the one with the higher default priority, f, is acknowledged first. when the interrupt enabled state is set during servicing of interrupt request f, pending interrupt request e is acknowledged since prsl = 0. imc 00h notes 1. low default priority 2. high default priority remarks 1. a to f in the figure are arbitrary names used to differentiate between the interrupt requests and macro service requests. 2. high/low default priorities in the figure indicate the relative priority levels of the two interrupt requests. chapter 22 interrupt functions 533 user? manual u11316ej4v1ud 22.8 macro service function 22.8.1 outline of macro service function macro service is one method of servicing interrupts. with a normal interrupt, the program counter (pc) and program status word (psw) are saved, and the start address of the interrupt service program is loaded into the pc, but with macro service, different processing (mainly data transfers) is performed instead of this processing. this enables interrupt requests to be responded to quickly, and moreover, since transfer processing is faster than processing by a program, the processing time can also be reduced. also, since a vectored interrupt is generated after processing has been performed the specified number of times, another advantage is that vectored interrupt programs can be simplified. figure 22-16 differences between vectored interrupt and macro service processing macro service context switching note 1 vectored interrupt note 1 vectored interrupt interrupt request generation main routine main routine main routine main routine macro service processing main routine note 2 note 4 note 4 note 3 interrupt servicing main routine sel rbn interrupt servicing restore pc, psw save general registers initialize general registers interrupt servicing restore general registers main routine restore pc & psw main routine notes 1. when register bank switching is used, and an initial value has been set in the register beforehand 2. register bank switching by context switching, saving of pc and psw 3. register bank, pc and psw restoration by context switching 4. pc and psw saved to the stack, vector address loaded into pc 22.8.2 types of macro service macro service can be used with the 19 kinds note of interrupt shown in table 22-6. there are four kinds of operation, which can be used to suit the application. note twenty types with the pd784038y subseries chapter 22 interrupt functions 534 user s manual u11316ej4v1ud table 22-6 interrupts for which macro service can be used default interrupt request generation source generating unit macro service control priority word address 0 intp0 (pin input edge detection) edge detection 0fe06h 1 intp1 (pin input edge detection) 0fe08h 2 intp2 (pin input edge detection) 0fe0ah 3 intp3 (pin input edge detection) 0fe0ch 4 intc00 (tm0-cr00 match signal generation) timer/counter 0 0fe0eh 5 intc01 (tm0-cr01 match signal generation) 0fe10h 6 intc10 (tm1-cr10 or tm1w-cr10w match signal generation) timer/counter 1 0fe12h 7 intc11 (tm1-cr11 or tm1w-cr11w match signal generation) 0fe14h 8 intc20 (tm2-cr20 or tm2w-cr20w match signal generation) timer/counter 2 0fe16h 9 intc21 (tm2-cr21 or tm2w-cr21w match signal generation) 0fe18h 10 intc30 (tm3-cr30 or tm3w-cr30w match signal generation) timer 3 0fe1ah 11 intp4 (pin input edge detection) edge detection 0fe1ch 12 intp5 (pin input edge detection) 0fe1eh 13 intad (a/d conversion end) a/d converter 0fe20h 14 intsr (asynchronous serial interface reception end) asynchronous 0fe24h intcsi1 (clocked serial interface transfer end) serial interface/ 15 intst (asynchronous serial interface transmission end) clocked serial 0fe26h interface 1 16 intcsi (clocked serial interface transfer end) clocked serial 0fe28h interface 17 intsr2 (asynchronous serial interface 2 reception end) asynchronous 0fe2ch intcsi2 (clocked serial interface 2 transfer end) serial interface 2/ 18 intst2 (asynchronous serial interface 2 transmission end) clocked serial 0fe2eh interface 2 19 note intspc (i 2 c bus stop condition interrupt) clocked serial 0fe30h interface note pd784038y subseries only remarks 1. the default priority is a fixed number. this indicates the order of priority when macro service requests are generated simultaneously, 2. the intsr and intcsi1 interrupts are generated by the same hardware (they cannot both be used simultaneously). therefore, although the same hardware is used for the interrupts, two names are provided, for use in each of the two modes. the same applies to intsr2 and intcsi2. chapter 22 interrupt functions 535 user s manual u11316ej4v1ud there are four kinds of macro service, as shown below. (1) type a one byte or one word of data is transferred between a special function register (sfr) and memory each time an interrupt request is generated, and a vectored interrupt request is generated when the specified number of transfers have been performed. memory that can be used in the transfers is limited to internal ram addresses 0fe00h to 0feffh when the location 0h instruction is executed, and addresses 0ffe00h to 0ffeffh when the location 0fh instruction is executed. the specification method is simple and is suitable for low-volume, high-speed data transfers. (2) type b as with type a, one byte or one word of data is transferred between a special function register (sfr) and memory each time an interrupt request is generated, and a vectored interrupt request is generated when the specified number of transfers have been performed. the sfr and memory to be used in the transfers is specified by the macro service channel (the entire 1-mbyte memory space can be used). this is a general version of type a, suitable for large volumes of transfer data. (3) type c data is transferred from memory to two special function registers (sfr) each time an interrupt request is generated, and a vectored interrupt request is generated when the specified number of transfers have been performed. with type c macro service, not only are data transfers performed to two locations in response to a single interrupt request, but it is also possible to add output data ring control and a function that automatically adds data to a compare register. the entire 1-mbyte memory space can be used. type c is mainly used with the intc10 and intc11 interrupts, and is used for stepping motor control, etc., by macro service, with p0l or p0h and cr10, cr10w, cr11 and cr11w used as the sfrs to which data is transferred. (4) counter mode this mode is to decrement the macro service counter (msc) when an interrupt occurs and is used to count the division operation of an interrupt and interrupt generation circuit. when msc is 0, a vector interrupt can be generated. to restart the macro service, msc must be set again. msc is fixed to 16 bits and cannot be used as an 8-bit counter. chapter 22 interrupt functions 536 user s manual u11316ej4v1ud 22.8.3 basic macro service operation interrupt requests for which the macro service processing generated by the algorithm shown in figure 22-10 can be specified are basically serviced in the sequence shown in figure 22-17. interrupt requests for which macro service processing can be specified are not affected by the status of the ie flag, but are disabled by setting (to 1) an interrupt mask flag in the interrupt mask register (mk0). macro service processing can be executed in the interrupt disabled state and during execution of an interrupt service program. figure 22-17 macro service processing sequence no msc = 0? vcie = 1? msc msc 1 interrupt service mode bit 0 interrupt request flag 0 yes no yes macro service processing execution ; data transfer, real-time output port control ; decrement macro service counter (msc) interru p t in p ut generation execute next instruction generation of interrupt request for which macro service processing can be specified the macro service type and transfer direction are determined by the value set in the macro service control word mode register. transfer processing is then performed using the macro service channel specified by the channel pointer according to the macro service type. the macro service channel is memory which contains the macro service counter which records the number of transfers, the transfer destination and transfer source pointers, and data buffers, and can be located at any address in the range fe00h to feffh when the location 0h instruction is executed, or ffe00h to ffeffh when the location 0fh instruction is executed. chapter 22 interrupt functions 537 user s manual u11316ej4v1ud 22.8.4 operation at end of macro service in macro service, processing is performed the number of times specified during execution of another program. macro service ends when the processing has been performed the specified number of times (when the macro service counter (msc) reaches 0). either of two operations may be performed at this point, as specified by the vcie bit (bit 7) of the macro service mode register for each macro service. (1) when vcie bit is 0 in this mode, an interrupt is generated as soon as the macro service ends. figure 22-18 shows an example of macro service and interrupt acknowledgment operations when the vcie bit is 0. this mode is used when a series of operations end with the last macro service processing performed, for instance. it is mainly used in the following cases: asynchronous serial interface receive data buffering (intsr/intsr2) a/d conversion result fetch (intad) compare register update as the result of a match between a timer register and the compare register (intc00/ intc01/intc10/intc11/intc20/intc21/intc30) timer/counter capture register read due to edge input to the intpn pin (intp0/intp1/intp2/intp3) chapter 22 interrupt functions 538 user s manual u11316ej4v1ud figure 22-18 operation at end of macro service when vcie = 0 main routine ei main routine ei macro service request last macro service request macro service processing macro service processing servicing of interrupt request due to end of macro service other interrupt request last macro service request servicing of other interrupt macro service processing servicing of interrupt request due to end of macro service at the end of macro service (msc = 0), an interrupt request is generated and acknowledged. if the last macro service is performed when the interrupt due to the end of macro service cannot be acknowledged while other interrupt servicing is being executed, etc., that interrupt is held pending until it can be acknowledged. chapter 22 interrupt functions 539 user s manual u11316ej4v1ud (2) when vcie bit is 1 in this mode, an interrupt is not generated after macro service ends. figure 22-19 shows an example of macro service and interrupt acknowledgment operations when the vcie bit is 1. this mode is used when the final operation is to be started by the last macro service processing performed, for instance. it is mainly used in the following cases: clocked serial interface receive data transfers (intcsi/intcsi1/intcsi2) asynchronous serial interface data transfers (intst/ intst2) to stop a stepping motor in the case (intc10/intc11) of stepping motor control by means of macro service type c using the real-time output port and timer/counter. figure 22-19 operation at end of macro service when vcie = 1 main routine ei macro service request last macro service request interrupt request due to he end of the hardware operation started by the last macro service processing macro service processing processing of last macro service interrupt servicing chapter 22 interrupt functions 540 user s manual u11316ej4v1ud 22.8.5 macro service control registers (1) macro service control word the pd784038 s macro service function is controlled by the macro service control mode register and macro service channel pointer. the macro service processing mode is set by means of the macro service mode register, and the macro service channel address is indicated by the macro service channel pointer. the macro service mode register and macro service channel pointer are mapped onto the part of the internal ram shown in figure 22-20 for each macro service as the macro service control word. when macro service processing is performed, the macro service mode register and channel pointer values correspond- ing to the interrupt requests for which macro service processing can be specified must be set beforehand. figure 22-20 macro service control word format reserved word channel pointer mode register 0fe31 0fe30 0fe2f 0fe2e 0fe2d 0fe2c spchp spmmd stchp2 stmmd2 srchp2/csichp2 srmmd2/csimmd2 0fe29 0fe28 0fe27 0fe26 0fe25 0fe24 csichp csimmd stchp stmmd srchp/csichp1 srmmd/csimmd1 0fe21 0fe20 0fe1f 0fe1e 0fe1d 0fe1c 0fe1b 0fe1a 0fe19 0fe18 0fe17 0fe16 0fe15 0fe14 0fe13 0fe12 0fe11 0fe10 0fe0f 0fe0e 0fe0d 0fe0c 0fe0b 0fe0a 0fe09 0fe08 0fe07 0fe06 adchp admmd pchp5 pmmd5 pchp4 pmmd4 cchp30 cmmd30 cchp21 cmmd21 cchp20 cmmd20 cchp11 cmmd11 cchp10 cmmd10 cchp01 cmmd01 cchp00 cmmd00 pchp3 pmmd3 pchp2 pmmd2 pchp1 pmmd1 pchp0 pmmd0 intst2 channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register ? ? ? intsr2/intcsi2 ? ? ? intcsi ? ? ? intst ? ? ? intad ? ? ? intp5 ? ? ? intp4 ? ? ? intc30 ? ? ? intc21 ? ? ? intc20 ? ? ? intc11 ? ? ? intc10 ? ? ? intc01 intc00 ? ? ? intp3 ? ? ? intp2 ? ? ? intp1 ? ? ? intp0 ? ? ? ? ? ? intsr/intcsi1 ? ? ? source address channel pointer mode register intspc note ? ? ? note pd784038y subseries only chapter 22 interrupt functions 541 user s manual u11316ej4v1ud (2) macro service mode register the macro service mode register is an 8-bit register that specifies the macro service operation. this register is written in internal ram as part of the macro service control word (see figure 22-20 ). the format of the macro service mode register is shown in figure 22-21. figure 22-21 macro service mode register format (1/2) 7 vcie 6 mod2 5 mod1 4 mod0 3 cht3 2 cht2 1 cht1 0 cht0 cht0 0 1 0 cht1 0 0 0 cht2 0 0 0 cht3 1 0 0 mod2 mod1 mod0 000 001 010 011 100 101 110 111 vcie 0 1 type a counter mode counter decrement data transfer direction memory sfr data size: 1 byte data transfer direction sfr memory data transfer direction memory sfr data size: 1 byte data transfer direction sfr memory data transfer direction memory sfr data size: 2 bytes data transfer direction sfr memory data transfer direction memory sfr data size: 2 bytes data transfer direction sfr memory not generated (next interrupt processing is vectored interrupt) generated interrupt request when msc = 0 type b chapter 22 interrupt functions 542 user s manual u11316ej4v1ud figure 22-21 macro service mode register format (2/2) 7 vcie 6 mod2 5 mod1 4 mod0 3 cht3 2 cht2 1 cht1 0 cht0 cht0 1 1 0 cht1 1 0 0 cht2 1 1 1 cht3 1 1 1 0 1 1 1 mod2 mod1 mod0 000 001 010 011 100 101 110 111 type c decrements mpd increments mpd retains mpt decrements mpt retains mpt increments mpt data size for timer specified by mpt: 1 byte no automatic addition no ring control ring control automatic addition no ring control ring control no ring control ring control no ring control ring control data size for timer specified by mpt: 2 bytes no automatic addition automatic addition vcie 0 1 generated not generated (next interrupt processing is vectored interrupt) interrupt request when msc = 0 (3) macro service channel pointer the macro service channel pointer specifies the macro service channel address. the macro service channel can be located in the 256-byte space from fe00h to feffh when the location 0h instruction is executed, or ffe00h to ffeffh when the location 0fh instruction is executed, and the high-order 16 bits of the address are fixed. therefore, the low-order 8 bits of the data stored to the highest address of the macro service channel are set in the macro service channel pointer. chapter 22 interrupt functions 543 user s manual u11316ej4v1ud 22.8.6 macro service type a (1) operation data transfers are performed between buffer memory in the macro service channel and an sfr specified in the macro service channel. with type a, the data transfer direction can be selected as memory-to-sfr or sfr-to-memory. data transfers are performed the number of times set beforehand in the macro service counter. one macro service processing transfers 8-bit or 16-bit data. type a macro service is useful when the amount of data to be transferred is small, as transfers can be performed at high speed. chapter 22 interrupt functions 544 user s manual u11316ej4v1ud figure 22-22 macro service data transfer processing flow (type a) read contents of macro service mode register determine channel type read channel pointer contents (m) other to other macro service processing read msc contents (n) calculate buffer address note read sfr pointer contents determine transfer direction sfr memory memory sfr read buffer contents, then transfer read data to specified sfr specified sfr contents, then transfer read data to buffer msc msc 1 msc = 0? no yes clear (to 0) interrupt service mode bit (ism) vcie = 1? (vectored interrupt request generation) type a yes no 1-byte transfer: m n 1 2-byte transfer: m n 2 1 note macro service request acknowledgment clear (to 0) interrupt request flag (if) end end chapter 22 interrupt functions 545 user s manual u11316ej4v1ud (2) macro service channel configuration the channel pointer and 8-bit macro service counter (msc) indicate the buffer address in internal ram (fe00h to feffh when the location 0h instruction is executed, or ffe00h to ffeffh when the location 0fh instruction is executed) which is the transfer source or transfer destination (see figure 22-23 ). in the channel pointer, the low- order 8 bits of the address are written to the macro service counter in the macro service channel. the sfr involved with the access is specified by the sfr pointer (sfrp). the low-order 8 bits of the sfr address are written to the sfrp. chapter 22 interrupt functions 546 user s manual u11316ej4v1ud figure 22-23 type a macro service channel (a) 1-byte transfers 70 macro service counter (msc) sfr pointer (sfrp) macro service buffer 1 macro service buffer 2 macro service buffer n channel pointer mode register macro service control word macro service channel high addresses low addresses macro service buffer address = (channel pointer) (macro service counter) 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mcs = 1 mcs = 2 mcs = n (b) 2-byte transfers 70 macro service counter (msc) sfr pointer (sfrp) macro service buffer 1 macro service buffer 2 macro service buffer n channel pointer mode register macro service control word macro service channel high addresses low addresses macro service buffer address = (channel pointer) (macro service counter) 2 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mcs = 1 mcs = 2 mcs = n (high-order byte) (low-order byte) (high-order byte) (low-order byte) (high-order byte) (low-order byte) chapter 22 interrupt functions 547 user? manual u11316ej4v1ud (3) example of use of type a an example is shown below in which data received via the asynchronous serial interface is transferred to a buffer area in on-chip ram. figure 22-24 asynchronous serial reception (internal ram) 0fe7fh channel pointer 7fh mode register 11h note low-order 8 bits of rxb address type a, sfr memory, 8-bit transfer, interrupt request generation when msc = 0 1 internal bus msc 0eh sfrp 8ch note 0fe70h r x d/p30 intsr macro service request receive buffer (rxb) shift register remark addresses in the figure are the values when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values in the figure. chapter 22 interrupt functions 548 user s manual u11316ej4v1ud 22.8.7 macro service type b (1) operation data transfers are performed between a data area in memory and an sfr specified by the macro service channel. with type b, the data transfer direction can be selected as memory-to-sfr or sfr-to-memory. data transfers are performed the number of times set beforehand in the macro service counter. one macro service processing transfers 8-bit or 16-bit data. this type of macro service is macro service type a for general purposes and is ideal for processing a large amount of data because up to 64 kbytes of data buffer area when 8-bit data is transferred or 1 mbyte of data buffer area when 16-bit data is transferred can be set in any address space. chapter 22 interrupt functions 549 user s manual u11316ej4v1ud figure 22-25 macro service data transfer processing flow (type b) read contents of macro service mode register determine channel type other to other macro service processing 1-byte transfer: +1 2-byte transfer: +2 determine transfer direction sfr memory memory sfr msc msc 1 msc = 0? no yes clear (to 0) interrupt service mode bit (ism) vcie = 1? (vectored interrupt request generation) type b yes no increment mp note read data from sfr, and write to memory addressed by mp read data from memory, and write to sfr specified by sfr pointer select transfer source memory with macro service pointer (ms) note select transfer source sfr with sfr pointer end end macro service request acknowledgment read channel pointer contents (m) clear (to 0) interrupt request flag (if) chapter 22 interrupt functions 550 user? manual u11316ej4v1ud (2) macro service channel configuration the macro service pointer (mp) indicates the data buffer area in the 1-mbyte memory space that is the transfer destination or transfer source. the low-order 8 bits of the sfr that is the transfer destination or transfer source is written to the sfr pointer (sfrp). the macro service counter (msc) is a 16-bit counter that specifies the number of data transfers. the macro service channel that stores the mp, sfrp and msc is located in internal ram space addresses 0fe00h to 0feffh when the location 0h instruction is executed, or 0ffe00h to 0ffeffh when the location 0fh instruction is executed. the macro service channel is indicated by the channel pointer as shown in figure 22-26. in the channel pointer, the low-order 8 bits of the address are written to the macro service counter in the macro service channel. figure 22-26 type b macro service channel macro service counter (msc) sfr pointer (sfrp) (bits 8 to 15) (bits 0 to 7) (bits 16 to 23) note (bits 8 to 15) (bits 0 to 7) channel pointer mode register macro service pointer (mp) macro service control word low addresses macro service channel high addresses sfr buffer area macro service buffer address = macro service pointer note bits 20 to 23 must be set to 0. chapter 22 interrupt functions 551 user s manual u11316ej4v1ud (3) example of use of type b an example is shown below in which parallel data is input from port 3 in synchronization with an external signal. the intp4 external interrupt pin is used for synchronization with the external signal. figure 22-27 parallel data input synchronized with external interrupts 64k memory space macro service control word, macro service channel (internal ram) 0fe6eh buffer area note low-order 8 bits of port 3 address 1 +1 internal bus port 3 p37 p36 p35 p34 p33 p32 p31 p30 intp4 edge detection macro service request intp4 msc 00h 20h 03h note mp 00h a0h 00h sfrp type b, sfr memory, 8-bit transfer, interrupt request generation when msc = 0 channel pointer 6eh mode register 18h 0a01fh 0a000h remark macro service channel addresses in the figure are the values when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values in the figure. chapter 22 interrupt functions 552 user s manual u11316ej4v1ud figure 22-28 parallel data input timing intp4 port 3 data fetch (macro service) 22.8.8 macro service type c (1) operation in type c macro service, data in the memory specified by the macro service channel is transferred to two sfrs, for timer use and data use, specified by the macro service channel in response to a single interrupt request (the sfrs can be freely selected). an 8-bit or 16-bit timer sfr can be selected. in addition to the basic data transfers described above, type c macro service, the following functions can be added to type c macro service to reduce the size of the buffer area and alleviate the burden on software. these specifications are made by using the mode register of the macro service control word. (a) updating of timer macro service pointer it is possible to choose whether the timer macro service pointer (mpt) is to be kept as it is or incremented/ decremented. the mpt is incremented or decremented in the same direction as the macro service pointer (mpd) for data. (b) updating of data macro service pointer it is possible to choose whether the data macro service pointer (mpd) is to be incremented or decremented. (c) automatic addition the current compare register value is added to the data addressed by the timer macro service pointer (mpt), and the result is transferred to the compare register. if automatic addition is not specified, the data addressed by the mpt is simply transferred to the compare register. (d) ring control an output data pattern of the length specified beforehand is automatically output repeatedly. these specifications are made by the mode register in the macro service control word. chapter 22 interrupt functions 553 user s manual u11316ej4v1ud figure 22-29 macro service data transfer processing flow (type c) (1/2) read contents of macro service mode register determine channel type read channel pointer contents (m) other to other macro service processing note transfer data to compare register automatic addition specified? no increment mpt? no increment mpd? type c yes read memory addressed by mpt retain mpt? no increment mpd (+1) no yes yes yes increment mpt note 1 1-byte transfer: +1 2-byte transfer: +2 add data to compare register decrement mpd ( 1) decrement mpt transfer data to buffer register read memory addressed by mpd macro service request acknowledgment chapter 22 interrupt functions 554 user s manual u11316ej4v1ud figure 22-29 macro service data transfer processing flow (type c) (2/2) no no yes no no yes yes yes no yes 1 end ring control? ring counter = 0? increment mpd? msc = 0? vcie = 1? subtract modulo register contents from data macro service pointer (mpd), and return pointer to start address add modulo register contents to data macro service pointer (mpd), and return pointer to start address msc msc 1 clear (to 0) interrupt service mode bit (ism) clear (to 0) interrupt request flag (if) load modulo register contents into ring counter end decrement ring counter (vectored interrupt request generation) chapter 22 interrupt functions 555 user s manual u11316ej4v1ud (2) macro service channel configuration there are two kinds of type c macro service channel, as shown in figure 22-30. the timer macro service pointer (mpt) mainly indicates the data buffer area in the 1-mbyte memory space to be transferred or added to the timer/counter compare register. the data macro service pointer (mpd) indicates the data buffer area in the 1-mbyte memory space to be transferred to the real-time output port. the modulo register (mr) specifies the number of repeat patterns when ring control is used. the ring counter (rc) holds the step in the pattern when ring control is used. when initialization is performed, the same value as in the mr is normally set in this counter. the macro service counter (msc) is a 16-bit counter that specifies the number of data transfers. the low-order 8 bits of the sfr that is the transfer destination is written to the timer sfr pointer (tsfrp) and data sfr pointer (dsfrp). the macro service channel that stores these pointers and counters is located in internal ram space addresses 0fe00h to 0feffh when the location 0h instruction is executed, or 0ffe00h to 0ffeffh when the location 0fh instruction is executed. the macro service channel is indicated by the channel pointer as shown in figure 22-30. in the channel pointer, the low-order 8 bits of the address are written to the macro service counter in the macro service channel. figure 22-30 type c macro service channel (1/2) (a) no ring control macro service counter (msc) timer sfr pointer (tsfrp) (bits 8 to 15) (bits 0 to 7) (bits 8 to 15) (bits 8 to 15) (bits 0 to 7) (bits 0 to 7) (bits 16 to 23) note (bits 16 to 23) note channel pointer mode register timer macro service pointer (mpt) data macro service pointer (mpd) data sfr pointer (dsfrp) macro service control word low addresses macro service channel high addresses tsfr dsfr timer buffer area data buffer area macro service buffer address = macro service pointer note bits 20 to 23 must be set to 0. chapter 22 interrupt functions 556 user s manual u11316ej4v1ud figure 22-30 type c macro service channel (2/2) (b) with ring control macro service counter (msc) timer sfr pointer (tsfrp) (bits 8 to 15) (bits 8 to 15) (bits 8 to 15) (bits 0 to 7) (bits 0 to 7) (bits 0 to 7) (bits 16 to 23) note (bits 16 to 23) note ring counter (rc) channel pointer mode register timer macro service pointer (mpt) data sfr pointer (dsfrp) data macro service pointer (mpd) modulo register (mr) macro service control word low addresses macro service channel high addresses tsfr dsfr timer buffer area data buffer area macro service buffer address = macro service pointer note bits 20 to 23 must be set to 0. (3) examples of use of type c (a) basic operation an example is shown below in which the output pattern to the real-time output port and the output interval are directly controlled. update data is transferred from the two data storage areas set in the 1-mbyte space beforehand to the real-time output function buffer register (p0l) and the compare register (cr10). chapter 22 interrupt functions 557 user s manual u11316ej4v1ud figure 22-31 stepping motor open loop control by real-time output port 1m memory space macro service control word, macro service channel (internal ram) timer/ counter1 tm1 output latch p0 0fe5eh 123408h 123400h output data area low-order 8 bits of cr10 address type c, mpt/mpd incremented, 1-byte timer data, no automatic addition, no ring control, interrupt request generation at msc = 0 low-order 8 bits of p0l address intc10 match real-time output trigger/ macro service start 1 +1 123411h 123409h output timing data area t9 ... t2 t1 d9 d2 d1 ... msc 00h 04h 14h mpt 12h 34h dsfrp 09h 0eh 12h mpd channel pointer 34h 00h 5eh tsfrp mode register 0fh stepping motor internal bus compare register cr10 buffer register p0l p00 p01 p02 p03 +1 remark internal ram addresses in the figure are the values when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values in the figure. chapter 22 interrupt functions 558 user s manual u11316ej4v1ud figure 22-32 data transfer control timing tm1 count value 0h compare register (cr10) t1 buffer register p0l intc10 timer interrupt p00 p02 p03 p01 t1 t7 t8 t9 d1 d2 d3 d4 d5 d6 d7 d9 t2 t3 t4 t5 t6 t8 t7 t3 t2 t4 t5 t6 d8 chapter 22 interrupt functions 559 user s manual u11316ej4v1ud (b) examples of use of automatic addition control and ring control (i) automatic addition control the output timing data ( ? t) specified by the macro service pointer (mpt) is added to the contents of the compare register, and the result is written back to the compare register. use of this automatic addition control eliminates the need to calculate the compare register setting value in the program each time. (ii) ring control with ring control, the predetermined output patterns is prepared for one cycle only, and the one-cycle data patterns are output repeatedly in order in ring form. when ring control is used, only the output patterns for one cycle need be prepared, allowing the size of the data rom area to be reduced. the macro service counter (msc) is decremented each time a data transfer is performed. with ring control, too, an interrupt request is generated when msc = 0. when controlling a stepping motor, for example, the output patterns will vary depending on the configuration of the stepping motor concerned, and the phase excitation method (single-phase excitation, two-phase excitation, etc.), but repeat patterns are used in all cases. examples of single-phase excitation and 1-2-phase excitation of a 4-phase stepping motor are shown in figures 22-33 and 22-34. chapter 22 interrupt functions 560 user s manual u11316ej4v1ud figure 22-33 single-phase excitation of 4-phase stepping motor phase a phase b phase c phase d 1 cycle (4 patterns) 1 2 3 4 1 2 3 figure 22-34 1-2-phase excitation of 4-phase stepping motor phase a phase b phase c phase d 1 cycle (8 patterns) 1 2 3 4 5 6 7 8 1 2 3 4 8 5 chapter 22 interrupt functions 561 user s manual u11316ej4v1ud figure 22-35 automatic addition control + ring control block diagram 1 (when output timing varies with 1-2-phase excitation) . . . d1 1m memory space macro service control word, macro service channel (internal ram) compare register cr10w timer/counter1 tm1w addition buffer register p0l output latch p0 p00 p02 p01 p03 0fe5ah 1237feh 123007h output timing: 123400h 123000h output data (8 items) d7 d0 msc 02h 00h 14h mpt 12h 34h dsfrp 00h 0eh 12h mpd 30h mr 00h rc 08h 08h channel pointer 5ah tsfrp mode register 7fh low-order 8 bits of cr10 address type c, mpt/mpd incremented, 2-byte timer data, automatic addition, ring control, interrupt request generation at msc = 0 low-order 8 bits of p0l address to stepping motor intc10 match t512 -1 +2 +1 1 t2 t1 . . . remark internal ram addresses in the figure are the values when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values in the figure. chapter 22 interrupt functions 562 user s manual u11316ej4v1ud figure 22-36 automatic addition control + ring control timing diagram 1 (when output timing varies with 1-2-phase excitation) tm1w count value 0h ffffh compare register (cr10w) t0 buffer register p0l intc10 ? t1 p00 p02 p03 p01 t2 t1 + ? t2 t3 t2 + ? t3 t7 t6 + ? t7 t9 t8 + ? t9 t4 t3 + ? t4 t6 t5 + ? t6 t5 t4 + ? t5 t1 t0 + ? t1 ? t3 ? t4 ? t5 ? t6 ? t9 t0 ? t7 ? t8 d1 d2 d3 d4 d5 d6 d7 d0 d0 d7 count start ? t2 t8 t7 + ? t8 chapter 22 interrupt functions 563 user s manual u11316ej4v1ud figure 22-37 automatic addition control + ring control block diagram 2 (1-2-phase excitation constant-velocity operation) 1m memory space macro service control word, macro service channel (internal ram) compare register cr10 timer/counter 1 tm1 addition buffer register p0l output latch p0 p00 p02 p01 p03 0fe7ah 123007h output timing: 1233ffh 123000h output data (8 items) d7 d6 d0 . . . msc ffh ffh 14h mpt 12h 33h dsfrp ffh 0eh 12h mpd 30h mr 07h rc 08h 08h channel pointer 7ah tsfrp mode register 3ch low-order 8 bits of cr10 address type c, mpt retained, mpd decremented, 1-byte timer data, automatic addition, ring control, interrupt request generation at msc = 0 low-order 8 bits of p0l address to stepping motor intc10 match t remark internal ram addresses in the figure are the values when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values in the figure. chapter 22 interrupt functions 564 user s manual u11316ej4v1ud figure 22-38 automatic addition control + ring control timing diagram 2 (1-2-phase excitation constant-velocity operation) tm1 count value 0h ffffh compare register (cr10) t0 buffer register p0l d6 d5 d4 d3 d2 d1 d0 d7 d6 d7 d0 intc10 ? t p00 p02 p03 p01 count start t1 t0 + ? t t2 t1 + ? t t3 t2 + ? t t4 t3 + ? t t5 t4 + ? t t6 t5 + ? t t7 t6 + ? t t8 t7 + ? t t9 t8 + ? t t10 t9 + ? t chapter 22 interrupt functions 565 user s manual u11316ej4v1ud 22.8.9 counter mode (1) operation msc is decremented the number of times set in advance to the macro service counter (msc). because the number of times an interrupt occurs can be counted, this function can be used as an event counter where the interrupt generation cycle is long. figure 22-39 macro service data transfer processing flow (counter mode) macro service request acknowledged reads contents of macro service mode register identifies channel type msc msc 1 others to other macro service processing msc is 16 bits wide counter mode msc = 0? no yes vcie = 1? no yes clears interrupt processing type bit (ism) to 0 clears interrupt request flag (if) to 0 end end (vectored interrupt request is generated) chapter 22 interrupt functions 566 user s manual u11316ej4v1ud (2) configuration of macro service channel the macro service channel consists of only a 16-bit macro service counter. the low-order 8 bits of the address of the msc are written to the channel pointer. figure 22-40 counter mode ? ? ? ? ? macro service channel macro service counter (msc) high-order 8 bytes low-order 8 bytes high addresses low addresses channel pointer mode register 70 (3) example of using counter mode here is an example of counting the number of edges input to external interrupt pin intp5. figure 22-41 counting number of edges (internal ram) intp5 macro service request msc 0eh high-order 8 bytes low-order 8 bytes channel pointer 7eh mode register 00h counter mode interrupt request is generated when msc = 0. internal bus ofe7eh 1 intp5/p26 remark the internal ram address in the figure above is the value when the location 0h instruction is executed. when the location 0fh instruction is executed, add 0f0000h to this value. chapter 22 interrupt functions 567 user s manual u11316ej4v1ud 22.9 when interrupt requests and macro service are temporarily held pending when the following instructions are executed, interrupt acknowledgment and macro service processing is deferred for 8 system clock cycles. however, software interrupts are not deferred. ei di brk brkcs retcs retcsb !addr16 reti retb location 0h or location 0fh pop psw popu post mov pswl, a mov pswl, #byte movg sp, #imm24 write instruction and bit manipulation instruction to an interrupt control register note , or the mk0, mk1l, imc or ispr register (except bt and bf instructions) psw bit manipulation instruction (excluding the bt pswl. bit, $addr20, bf pswl. bit, $addr20, bt pswh. bit, $addr20, bf pswh. bit, $addr20, set1 cy, not1 cy, and clr1 cy instructions) note interrupt control registers: pic0, pic1, pic2, pic3, pic4, pic5, cic00, cic01, cic10, cic11, cic20, cic21, cic30, adic, seric, sric, csiic1, stic, csiic, seric2, sric2, csiic2, stic2, spcic ( pd784038y subseries only) chapter 22 interrupt functions 568 user s manual u11316ej4v1ud cautions 1. when an interrupt related register is polled using a bf instruction, etc., the branch destination of that br instruction, etc., should not be that instruction. if a program is written in which a branch is made to that instruction itself, all interrupts and macro service requests will be held pending until a condition whereby a branch is not made by that instruction arises. bad example loop : bf pic0.7, $loop all interrupts and macro service requests are held pending until pic0.7 is 1. interrupts and macro service requests are not serviced until after execution of the instruction following the bf instruction. good example (1) loop : nop bf pic0.7, $loop interrupts and macro service requests are serviced after execu tion of the nop instruction, so that interrupts are never held pending for a long period. good example (2) loop : bt pic0.7, $next using a btclr instruction instead of a bt instruction has the advantage that the flag is cleared (to 0) automatically. br $loop interrupts and macro service requests are serviced after execu- next : tion of the br instruction, so that interrupts are never held pending for a long period. 2. for a similar reason, if problems are caused by a long pending period for interrupts and macro service when instructions to which the above applies are used in succession, a time at which interrupts and macro service requests can be acknowledged should be provided by inserting an nop instruction, etc., in the series of instructions. chapter 22 interrupt functions 569 user s manual u11316ej4v1ud 22.10 instructions whose execution is temporarily suspended by an interrupt or macro service execution of the following instructions is temporarily suspended by an acknowledgeable interrupt request or macro service request, and the interrupt or macro service request is acknowledged. the suspended instruction is resumed after completion of the interrupt service program or macro service processing. temporarily suspended instructions: movm, xchm, movbk, xchbk cmpme, cmpmne, cmpmc, cmpmnc cmpbke, cmpbkne, cmpbkc, cmpbknc sacw 22.11 interrupt and macro service operation timing interrupt requests are generated by hardware. the generated interrupt request sets (to 1) an interrupt request flag. when the interrupt request flag is set (to 1), a time of 8 clocks (0.5 s: f clk = 16 mhz) is taken to determine the priority, etc. following this, if acknowledgment of that interrupt or macro service is enabled, interrupt request acknowledgment processing is performed when the instruction being executed ends. if the instruction being executed is one which temporarily defers interrupts and macro service, the interrupt request is acknowledged after the following instruction (see 22.9 when interrupt requests and macro service are temporarily held pending for deferred instructions). figure 22-42 interrupt request generation and acknowledgment (unit: clock = 1/f clk ) interrupt request flag 8 clocks instruction interrupt request acknowledgment processing/macro service processing chapter 22 interrupt functions 570 user s manual u11316ej4v1ud 22.11.1 interrupt acknowledge processing time the time shown in table 22-7 is required to acknowledge an interrupt request. after the time shown in this table has elapsed, execution of the interrupt processing program is started. table 22-7 interrupt acknowledge processing time (unit: clock = 1/f clk ) vector table irom emem branch irom, pram emem pram emem destination stack iram pram emem iram pram emem iram pram emem iram pram emem vectored 26 29 37 + 4n 27 30 38 + 4n 30 33 41 + 4n 31 34 42 + 4n interrupts context 22 23 22 23 switching remarks 1. irom : internal rom (with high-speed fetch specified) pram : peripheral ram of internal ram (only when location 0h instruction is executed in the case of branch destination) iram : internal high-speed ram emem : internal rom when external memory and high-speed fetch are not specified 2. n is the number of wait states per byte necessary for writing data to the stack (the number of wait states is the sum of the number of address wait states and the number of access wait states). 3. it the vector table is emem, and if wait states are inserted in reading the vector table, add 2 m to the value of the vectored interrupt in the above table, and add m to the value of context switching, where m is the number of wait states per byte necessary for reading the vector table. 4. it the branch destination is emem and if wait states are inserted in reading the instruction at the branch destination, add that number of wait states. 5. if the stack is occupied by pram and if the value of the stack pointer (sp) is odd, add 4 to the value in the above table. 6. the number of wait states is the sum of the number of address wait states and the number of access wait states. chapter 22 interrupt functions 571 user s manual u11316ej4v1ud 22.11.2 processing time of macro service macro service processing time differs depending on the type of the macro service, as shown in table 22-8. table 22-8 macro service processing time (units: clock = 1/f clk ) processing type of macro service data area iram others type a sfr memory 1 byte 24 2 bytes 25 memory sfr 1 byte 24 2 bytes 26 type b sfr memory 33 35 memory sfr 34 36 type c 49 53 counter mode msc 017 msc = 0 25 remarks 1. iram: internal high-speed ram 2. in the following cases in the other data areas, add the number of clocks specified below. if the data size is 2 bytes with irom or iram, and the data is located at an odd address: 4 clocks if the data size is 1 byte with emem: number of wait states for data access if the data size is 2 bytes with emem: 4 + 2n (where n is the number of wait states per byte) 3. if msc = 0 with type a, b, or c, add 1 clock. 4. with type c, add the following value depending on the function to be used and the status at that time. ring control: 4 clocks. adds 7 more clocks if the ring counter is 0 during ring control. chapter 22 interrupt functions 572 user s manual u11316ej4v1ud 22.12 restoring interrupt function to initial state if an inadvertent program loop or system error is detected by means of an operand error interrupt, the watchdog timer, nmi pin input, etc., the entire system must be restored to its initial state. in the pd784038, interrupt acknowledgment related priority control is performed by hardware. this interrupt acknowledgment related hardware must also be restored to its initial state, otherwise subsequent interrupt acknowledgment control may not be performed normally. a method of initializing interrupt acknowledgment related hardware in the program is shown below. the only way of performing initialization by hardware is by reset input. example movw mk0, #0ffffh ; mask all maskable interrupts mov mk1l, #0ffh iresl : cmp ispr, #0 ; no interrupt service programs running? bz $next movg sp, #retval ; forcibly change sp location reti ; forcibly terminate running interrupt service program, return address = iresl retval : dw loww (iresl) ; stack data to return to iresl with reti instruction db 0 db highw (iresl) ; loww & highw are assembler operators for calculating low-order 16 bits & high-order 16 bits respectively of symbol next next : it is necessary to ensure that a non-maskable interrupt request is not generated via the nmi pin during execution of this program. after this, on-chip peripheral hardware initialization and interrupt control register initialization are performed. when interrupt control register initialization is performed, the interrupt request flags must be cleared (to 0). chapter 22 interrupt functions 573 user s manual u11316ej4v1ud 22.13 cautions (1) the in-service priority register (ispr) is read-only. writing to this register may result in malfunction. (2) the watchdog timer mode register (wdm) can only be written to with a dedicated instruction (mov wdm/#byte). (3) the reti instruction must not be used to return from a software interrupt caused by a brk instruction. use the retb instruction. (4) the retcs instruction must not be used to return from a software interrupt caused by a brkcs instruction. use the retcsb instruction. (5) when a maskable interrupt is acknowledged by vectored interruption, the reti instruction must be used to return from the interrupt. subsequent interrupt related operations will not be performed normally if a different instruction is used. (6) the retcs instruction must be used to return from a context switching interrupt. subsequent interrupt related operations will not be performed normally if a different instruction is used. (7) macro service requests are acknowledged and serviced even during execution of a non-maskable interrupt service program. if you do not want macro service processing to be performed during a non-maskable interrupt service program, you should manipulate the interrupt mask register in the non-maskable interrupt service program to prevent macro service generation. (8) the reti instruction must be used to return from a non-maskable interrupt. subsequent interrupt acknowledgment will not be performed normally if a different instruction is used. to resume program execution from the initial state after the non-maskable interrupt has been acknowledged, see 22.12 restoring interrupt function to initial state . (9) non-maskable interrupts are always acknowledged, except during non-maskable interrupt service program execution (except when a high non-maskable interrupt request is generated during execution of a low-priority non-maskable interrupt service program) and for a certain period after execution of the special instructions shown in 22.9 . therefore, a non-maskable interrupt will be acknowledged even when the stack pointer (sp) value is undefined, in particular after reset release, etc. in this case, depending on the value of the sp, it may happen that the program counter (pc) and program status word (psw) are written to the address of a write-inhibited special function register (sfr) (see table 3-5 in 3.9 special function registers (sfr) ), and the cpu becomes deadlocked, or the pc and psw are written to an unexpected signal is output from a pin, or an address is which ram is not mounted, with the result that the return from the non-maskable interrupt service program is not performed normally and a software upsets occurs. therefore, the program following reset release must be as follows. cseg at 0 dw strt cseg base strt: location 0fh ; or location 0h movg sp, #imm24 chapter 22 interrupt functions 574 user? manual u11316ej4v1ud (10) when an interrupt related register is polled using a bf instruction, etc., the branch destination of that br instruction, etc., should not be that instruction. if a program is written in which a branch is made to that instruction itself, all interrupts and macro service requests will be held pending until a condition whereby a branch is not made by that instruction arises. bad example loop: bf pic0.7, $loop all interrupts and macro service requests are held pending until pic0.7 is 1. interrupts and macro service requests are not serviced until after execution of the instruction following the bf instruction. good example (1) loop: nop bf pic0.7, $loop interrupts and macro service requests are serviced after execution of the nop instruction, so that interrupts are never held pending for a long period. good example (2) loop: bt pic0.7, $next using a btclr instruction instead of a bt instruction has the advantage that the flag is cleared (to 0) automatically. br $loop interrupts and macro service requests are serviced after execution of the br instruction, so that interrupts are never held pending for a long period. next: (11) for a similar reason to that given in (10), if problems are caused by a long pending period for interrupts and macro service when instructions to which the above applies are used in succession, a time at which interrupts and macro service requests can be acknowledged should be provided by inserting an nop instruction, etc., in the series of instructions. 575 user? manual u11316ej4v1ud chapter 23 local bus interface function the local bus interface function is provided for the connection of external memory (rom and ram) and i/os. external memory (rom and ram) and i/os are accessed using the rd, wr, and astb pin signals, with pins ad0 to ad7 used as the multiplexed address/data bus and pins a8 to a19 as the address bus. the basic bus interface timing is shown in figures 23-7 and 23-8. also provided are a wait function for interfacing with low-speed memory, a refresh signal output function for refreshing pseudo-static ram, and a bus hold function for connecting devices that have a bus master function, such as a dma controller. 23.1 memory extension function with the pd784038, external memory and i/o extension can be performed by setting the memory extension mode register (mm). the pd784031 can access an external memory of 64 kbytes from the initial status. the memory space that can be accessed can be extended by setting of mm. 23.1.1 memory extension mode register (mm) the mm is an 8-bit register that performs external extension memory control, address wait number specification, and internal fetch cycle control. the mm register can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the mm format is shown in figure 23-1. reset input sets the mm register to 20h. chapter 23 local bus interface function 576 user? manual u11316ej4v1ud figure 23-1 memory extension mode register (mm) format 7 ifch mm 6 0 mm3 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 astb /clk out 5 aw 4 0 3 mm3 2 mm2 1 mm1 0 mm0 address after reset r/w r/w 20h 0ffc4h mm2 mm1 mm0 mode port 4 port 5 single-chip mode note 256-byte extension mode 1-kbyte extension mode 4-kbyte extension mode 16-kbyte extension mode 64-kbyte extension mode 256-kbyte extension mode 1-mbyte extension mode setting prohibited port port port port port port rd wr port port port port port port a8, a9 port a8 to a11 a8 to a13 a8 to a15 a8 to a15 a8 to a15 a16 to a19 p60 to p63 p64/ rd p65/ wr ad0 to ad7 ad0 to ad7 ad0 to ad7 ad0 to ad7 ad0 to ad7 ad0 to ad7 ad0 to ad7 port a16, a17 port rd wr rd wr astb rd wr rd wr rd wr rd wr other than the above aw address wait specification disabled enabled 1 0 ifch internal rom fetches fetch performed at same speed as external memory all wait control settings valid high-speed fetches performed wait control specification invalid 1 0 clkout note with the pd784031, these settings are the same as 64-kbyte extension mode. chapter 23 local bus interface function 577 user? manual u11316ej4v1ud 23.1.2 memory map with external memory extension the memory map when memory extension is used is shown in figures 23-2 to 23-5. external devices at the same addresses as the internal rom area, internal ram area and sfr area (excluding the external sfr area (0ffd0h to 0ffdfh)) cannot be accessed. if an access is made to these addresses, the memory or sfr in the pd784038 has access priority and no astb signal, rd signal or wr signal is output (these pins remain at the inactive level). the address bus output level remains at the level output prior to this, and the address/data bus output becomes high-impedance. except in 1-mbyte extension mode, the address output externally is output with the upper part of the address specified by the program masked. example 1: in 256-byte extension mode, when address 54321h is accessed by the program, the output address is 21h. example 2: in 256-byte extension mode, when address 67821h is accessed by the program, the output address is 21h. figure 23-2 pd784035 memory map (1/2) (a) when location 0h instruction is executed sfr sfr sfr sfr sfr note 2 sfr internal ram internal ram internal ram internal rom single-chip mode 1-mbyte extension mode 256-byte to 256-kbyte extension modes internal rom internal rom external memory external memory external memory note 1 external memory note 2 fffffh 0ffffh 0ffe0h 0ffcfh 0f700h 0bfffh 00000h notes 1. any extension size area in unshaded part 2. external sfr area chapter 23 local bus interface function 578 user s manual u11316ej4v1ud figure 23-2 sfr sfr sfr sfr sfr note 2 sfr internal ram internal ram internal ram internal rom single-chip mode 1-mbyte extension mode 256-byte to 256-kbyte extension modes internal rom internal rom external memory note 1 external memory fffffh fffe0h fffcfh ff700h 0bfffh 00000h external memory note 2 notes 1. any extension size area in unshaded part 2. external sfr area chapter 23 local bus interface function 579 user s manual u11316ej4v1ud figure 23-3 sfr sfr sfr sfr sfr note 2 sfr internal ram internal ram internal ram internal rom single-chip mode 1-mbyte extension mode 256-byte to 256-kbyte extension modes internal rom internal rom external memory fffffh 0ffffh 0ffe0h 0ffcfh 0f700h 00000h external memory note 1 external memory note 2 notes 1. any extension size area in unshaded part 2. external sfr area chapter 23 local bus interface function 580 user s manual u11316ej4v1ud figure 23-3 sfr sfr sfr sfr sfr note 2 sfr internal ram internal ram internal ram internal rom single-chip mode 1-mbyte extension mode 256-byte to 256-kbyte extension modes internal rom internal rom external memory fffffh fffe0h fffcfh ff700h 0ffffh 00000h external memory note 2 external memory note 1 notes 1. any extension size area in unshaded part 2. external sfr area chapter 23 local bus interface function 581 user s manual u11316ej4v1ud figure 23-4 sfr sfr sfr sfr sfr note 2 sfr internal ram internal rom internal rom internal rom internal ram internal ram internal rom single-chip mode 1-mbyte extension mode 256-byte to 256-kbyte extension modes internal rom internal rom external memory fffffh 0ffffh 10000h 17fffh 0ffe0h 0ffcfh 0f100h 00000h external memory note 1 external memory note 2 notes 1. any extension size area in unshaded part 2. external sfr area chapter 23 local bus interface function 582 user s manual u11316ej4v1ud figure 23-4 sfr sfr sfr sfr sfr note 2 sfr internal ram internal ram internal ram internal rom single-chip mode 1-mbyte expansion mode 256-byte to 256-kbyte expansion mode internal rom internal rom fffffh fffe0h fffcfh ff100h 17fffh 00000h external memory external memory note 1 external memory note 2 notes 1. any extension size area in unshaded part 2. external sfr area chapter 23 local bus interface function 583 user s manual u11316ej4v1ud figure 23-5 sfr sfr sfr sfr sfr note 2 sfr internal ram internal rom internal rom internal rom internal ram internal ram internal rom single-chip mode 1-mbyte extension mode 256-byte to 256-kbyte extension modes internal rom internal rom external memory fffffh 0ffffh 10000h 1ffffh 0ffe0h 0ffcfh 0ee00h 00000h external memory note 1 external memory note 2 notes 1. any extension size area in unshaded part 2. external sfr area chapter 23 local bus interface function 584 user s manual u11316ej4v1ud figure 23-5 sfr sfr sfr sfr sfr note 2 sfr internal ram internal ram internal ram internal rom single-chip mode 1-mbyte expansion mode 256-byte to 256-kbyte expansion mode internal rom internal rom fffffh fffe0h fffcfh ee100h 1ffffh 00000h external memory external memory note 2 external memory note 1 notes 1. any extension size area in unshaded part 2. external sfr area chapter 23 local bus interface function 585 user s manual u11316ej4v1ud figure 23-6 sfr sfr note internal ram 64-kbyte extension modes fffffh logical address output address output address output address 0ffffh 3ffffh fffffh 00000h 0ffffh 00000h 0ffffh 00000h 0fdffh 0fd00h 0ffffh 00000h c0000h bffffh 80000h 7ffffh 40000h 3ffffh 00000h 3ffffh 00000h 3ffffh 00000h 3ffffh c0000h bffffh 80000h 7ffffh 40000h 3ffffh 30000h 2ffffh 20000h 1ffffh 10000h 0ffdfh 0ffd0h 0f6ffh 0f6ffh 00000h sfr sfr note internal ram 256-kbyte extension modes 10000h 0ffdfh 0ffd0h 10000h 0ffdfh 0ffd0h 0f6ffh sfr sfr note internal ram 1-mbyte extension modes 0f6ffh note external sfr area chapter 23 local bus interface function 586 user s manual u11316ej4v1ud figure 23-6 sfr sfr note internal ram 64-kbyte extension mode fffffh logical address output address output address output address 00000h 0ffffh 00000h 0ffffh 0ffffh 00000h 00000h 0ffffh 00000h 0ffffh 00000h 0ffffh 00000h 0ffdfh 0ffd0h f0000h effffh cffffh bffffh e0000h 80000h 7ffffh 40000h 3ffffh 3f6ffh 00000h 00000h 3ffffh 40000h 3ffffh 00000h 00000h 3ffffh 00000h 3ffffh ff6ffh bffffh cffffh 80000h 7ffffh 30000h 2ffffh 20000h 1ffffh 10000h fffdfh fffd0h ff6ffh 0f6ffh 00000h sfr sfr note internal ram 256-kbyte extension mode 3ffdfh 3ffd0h fffdfh fffd0h 30000h sfr sfr note internal ram 1-mbyte extension mode f0000h note external sfr area chapter 23 local bus interface function 587 user s manual u11316ej4v1ud 23.1.3 basic operation of local bus interface the local bus interface accesses external memory using astb, rd, wr, an address/data bus (ad0 to ad7) and address bus (a8 to a19). when the local bus interface is used, p64, p65 and port 4 automatically operate as rd, wr, and ad0 to ad7. with the pd784031, these pins always operate only as rd, wr, and ad0 to ad7. on the address bus, only the pins that correspond to the extension memory size operate as address bus pins. an outline of the memory access timing is shown in figures 23-7 and 23-8. figure 23-7 read timing high address data (input) astb (output) rd (output) ad0 to ad7 a8 to a19 note (output) hi-z hi-z hi-z low address (output) note the number of address bus pins used depends on the extension mode size. figure 23-8 write timing high address astb (output) ad0 to ad7 (output) a8 to a19 note (output) hi-z hi-z hi-z wr (output) data low address note the number of address bus pins used depends on the extension mode size. chapter 23 local bus interface function 588 user s manual u11316ej4v1ud 23.2 wait function when a low-speed memory or i/o is connected externally to the pd784038, waits can be inserted in the external memory access cycle. there are two kinds of wait cycle, an address wait for securing the address decoding time, and an access wait for securing the access time. 23.2.1 wait function control registers (1) memory extension mode register (mm) the ifch bit of the mm performs wait control setting for internal rom accesses, and the aw bit performs address wait setting. the mm can be read or written to with an 8-bit manipulation instruction. the mm format is shown in figure 23-9. when reset is input, the mm register is set to 20h, the same cycle as for external memory is used for internal rom accesses, and the address wait function is validated. figure 23-9 memory extension mode register (mm) format 7 ifch mm 6 0 5 aw 4 0 3 mm3 2 mm2 1 mm1 0 mm0 address wait specification disabled enabled aw 1 0 address after reset r/w r/w 20h 0ffc4h memory extension mode settings (see 23.1 memory extension function ) internal rom fetches fetch performed at same speed as external memory all wait control settings valid high-speed fetches performed wait control specification invalid ifch 1 0 chapter 23 local bus interface function 589 user s manual u11316ej4v1ud (2) programmable wait control registers (pwc1/pwc2) the pwc1 and pwc2 specify the number of waits. pwc1 is an 8-bit register that divides the space from 0 to ffffh into four, and specifies wait control for each of these four spaces. pwc2 is a 16-bit register that divides the space from 10000h to ffffh into four, and specifies wait control for each of these four spaces. the pwc1 can be read or written to with an 8-bit manipulation instruction, and the pwc2 with a 16-bit manipulation instruction. the pwc1 and pwc2 formats are shown in figure 23-9. the high-order 8 bits of the pwc2 are fixed at aah, and therefore ensure that the high-order 8 bits are set to aah. when reset is input, the pwc1 is set to aah, and the pwc2 to aaaah, and 2-wait insertion is performed on the entire space. caution do not set external wait to the internal rom area. otherwise, the cpu may be in the deadlock status which can be cleared only by reset input. chapter 23 local bus interface function 590 user? manual u11316ej4v1ud figure 23-10 programmable wait control register (pwc1/pwc2) format (a) programmable wait control register 1 (pwc1) 7 pw31 pwc1 6 pw30 5 pw21 4 pw20 3 pw11 2 pw10 1 pw01 0 pw00 address after reset r/w r/w aah 0ffc7h 004000h to 007fffh 008000h to 00bfffh 00c000h to 00ffffh note pwn1 addresses subject to wait 000000h to 003fffh pwn0 0 0 1 1 0 1 0 1 no access wait cycle inserted 1 access wait cycle inserted 2 access wait cycles inserted access wait cycle inserted only for wait pin low-level input period (n = 0 to 3) note except part overlapping internal data area (b) programmable wait control register 2 (pwc2) 7 pw71 6 pw70 5 pw61 4 pw60 3 pw51 2 pw50 1 pw41 0 pw40 address after reset r/w r/w aaaah 0ffc8h 020000h to 03ffffh 040000h to 07ffffh 080000h to 0fffffh note pwn1 addresses subject to wait 010000h to 01ffffh pwn0 0 0 1 1 0 1 0 1 no access wait cycle inserted 1 access wait cycle inserted 2 access wait cycles inserted access wait cycle inserted only for wait pin low-level input period (n = 4 to 7) 15 1 pwc2 14 0 13 1 12 0 11 1 10 0 9 1 8 0 note except for part overlapping internal data area caution when the bus hold function is used, access wait control cannot be performed by means of the wait pin, and 0, 1 or 2 waits must be selected for the entire space. chapter 23 local bus interface function 591 user s manual u11316ej4v1ud 23.2.2 address waits address waits are used to secure the address decoding time. if the aw bit of the memory extension mode register (mm) is set (to 1), waits are inserted in every memory access note . when an address wait is inserted, the high-level period of the astb signal is extended by one system clock cycle (62.5 ns: f clk = 16 mhz). note except for the internal ram, internal sfrs, and internal rom during high-speed fetch. if it is specified that the internal rom is accessed in the same cycle as the external rom, an address wait state is inserted even when the internal rom is accessed. figure 23-11 address wait function read/write timing (1/3) (a) read timing with no address wait insertion f clk note high address astb ad0 to ad7 a8 to a19 hi-z hi-z rd input data low address hi-z note f clk : internal system clock frequency. this signal is present inside the pd784038 only. chapter 23 local bus interface function 592 user s manual u11316ej4v1ud figure 23-11 address wait function read/write timing (2/3) (b) read timing with address wait insertion f clk note astb ad0 to ad7 a8 to a19 hi-z hi-z rd hi-z low address input data high address note f clk : internal system clock frequency. this signal is present inside the pd784038 only. chapter 23 local bus interface function 593 user s manual u11316ej4v1ud figure 23-11 address wait function read/write timing (3/3) (c) write timing with no address wait insertion f clk note high address astb ad0 to ad7 a8 to a19 hi-z hi-z wr output data low address hi-z (d) write timing with address wait insertion f clk note high address astb ad0 to ad7 a8 to a19 hi-z hi-z wr output data low address hi-z note f clk : internal system clock frequency. this signal is present inside the pd784038 only. chapter 23 local bus interface function 594 user s manual u11316ej4v1ud 23.2.3 access waits access waits are inserted in the rd or wr signal low-level period, and extend the low-level period by 1/f clk (62.5 ns: f clk = 16 mhz) per cycle. there are two wait insertion methods, using either the programmable wait function that automatically inserts the preset number of cycles, or the external wait function controlled by a wait signal from outside. for wait cycle insertion control, the 1-mbyte memory space is divided into eight as shown in figure 23-12, and control is specified for each space by means of the programmable wait control registers (pwc1/pwc2). waits are not inserted in accesses to internal rom or internal ram using high-speed fetches. in accesses to internal sfrs, waits are inserted at the necessary times regardless of this specification. if access operations are specified as being performed in the same number of cycles as for external rom, waits are inserted also in internal rom accesses in accordance with the pwc1 settings. if there is a space for which control by a wait signal from outside has been selected by means of the pwc1/pwc2, the p66 pin operates as the wait signal input pin. after reset input, the p66 pin operates as a general-purpose input/output port. bus timing in the case of access wait insertion is shown in figures 23-13 to 23-15. cautions 1. the external wait function cannot be used when the bus hold function is used. 2. do not set external wait to the internal rom area. otherwise, the cpu may be in the deadlock status which can be cleared only by reset input. chapter 23 local bus interface function 595 user s manual u11316ej4v1ud figure 23-12 wait control spaces 512 kbytes 256 kbytes 128 kbytes 64 kbytes 16 kbytes 16 kbytes 16 kbytes 16 kbytes fffffh 80000h 03fffh 7ffffh controlled by bits pw70 & pw71 controlled by bits pw60 & pw61 controlled by pwc2 controlled by pwc1 controlled by bits pw50 & pw51 controlled by bits pw40 & pw41 controlled by bits pw30 & pw31 controlled by bits pw20 & pw21 controlled by bits pw10 & pw11 controlled by bits pw00 & pw01 20000h 1ffffh 10000h 0ffffh 0c000h 0bfffh 08000h 07fffh 40000h 3ffffh 04000h 00000h chapter 23 local bus interface function 596 user s manual u11316ej4v1ud figure 23-13 access wait function read timing (1/2) (a) 0 wait cycles set f clk note high address astb (output) ad0 to ad7 a8 to a15 (output) hi-z hi-z rd (output) data (input) low address hi-z (b) 1 wait cycle set f clk note high address astb (output) ad0 to ad7 a8 to a15 (output) hi-z hi-z rd (output) data (input) low address hi-z note f clk : internal system clock frequency. this signal is only present inside the pd784038. chapter 23 local bus interface function 597 user s manual u11316ej4v1ud figure 23-13 access wait function read timing (2/2) (c) 2 wait cycles set high address astb (output) ad0 to ad7 a8 to a15 (output) hi-z rd (output) data (input) low address hi-z f clk note note f clk : internal system clock frequency. this signal is only present inside the pd784038. chapter 23 local bus interface function 598 user s manual u11316ej4v1ud figure 23-14 access wait function write timing (1/2) (a) 0 wait cycles set f clk note high address astb (output) ad0 to ad7 (output) a8 to a15 (output) hi-z hi-z wr (output) data low address hi-z (b) 1 wait cycle set f clk note high address astb (output) ad0 to ad7 (output) a8 to a15 (output) hi-z hi-z wr (output) data low address hi-z note f clk : internal system clock frequency. this signal is only present inside the pd784038. chapter 23 local bus interface function 599 user s manual u11316ej4v1ud figure 23-14 access wait function write timing (2/2) (c) 2 wait cycles set high address astb (output) ad0 to ad7 (output) a8 to a15 (output) hi-z wr (output) data low address hi-z f clk note hi-z note f clk : internal system clock frequency. this signal is only present inside the pd784038. chapter 23 local bus interface function 600 user s manual u11316ej4v1ud figure 23-15 timing with external wait signal (a) read timing high address astb (output) ad0 to ad7 a8 to a15 (output) hi-z rd (output) data (input) low address hi-z f clk note wait (input) (b) write timing high address astb (output) ad0 to ad7 (output) a8 to a15 (output) hi-z wr (output) data low address hi-z f clk note wait (input) note f clk : internal system clock frequency. this signal is only present inside the pd784038. chapter 23 local bus interface function 601 user s manual u11316ej4v1ud 23.3 pseudo-static ram refresh function the pd784038 incorporates a pseudo-static ram refresh function for direct connection of pseudo-static ram. the pseudo-static ram refresh function outputs refresh pulses at any desired intervals. the refresh pulse output interval is specified by the refresh mode register (rfm) setting. the refresh area specification register (rfa) specifies the addresses on which refresh operations can be performed at the same time as memory access operations. this enables bus cycle insertions for refresh operations to be greatly decreased, thus minimizing the reduction in performance due to refresh operations. the pd784038 is provided with a function for supporting self-refresh operations that offers low power consumption by a pseudo-static ram application system. caution the refresh function cannot be used when the bus hold function is used. chapter 23 local bus interface function 602 user s manual u11316ej4v1ud 23.3.1 control registers (1) refresh mode register (rfm) the rfm is an 8-bit register that controls the pseudo-static ram refresh cycle and switching to self-refresh operations. the rfm register can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. rfm format is shown in figure 23-16. reset input clears the rfm register to 00h and sets the refrq pin to port mode, so that it operates as the alternate- function p67 pin. figure 23-16 refresh mode register (rfm) format 7 rflv rfm 6 0 5 0 4 rfen 3 0 2 0 1 rft1 0 rft0 rft1 rft0 refresh pulse output cycle specification 0 0 1 1 0 1 0 1 32/f clk note (2 s) 64/f clk (4 s) 128/f clk (8 s) 256/f clk (16 s) rflv rfen refrq pin output control 0 0 1 1 port mode self-refresh operation (refrq low level) refresh pulse output enabled note f clk : internal system clock frequency (f clk = 16 mhz) address after reset r/w r/w 00h 0ffcch 1 remark : 0 or 1 caution the refresh function cannot be used when the bus hold function is used. in this case, ensure that refreshing is specified as disabled. chapter 23 local bus interface function 603 user? manual u11316ej4v1ud (2) refresh area specification register (rfa) the rfa is an 8-bit register that specifies the areas on which refresh operations can be performed at the same time as memory access operations. the rfa register can be read or written to with an 8-bit manipulation instruction and bit manipulation instruction. rfa format is shown in figure 23-17. reset input clears the rfa register to 00h. figure 23-17 refresh area specification register (rfa) format rfa7 rfa rfa6 rfa5 rfa4 rfa3 rfa2 rfa1 rfa0 address after reset r/w r/w 00h 0ffcdh refresh specification area 0 1 7654 32 10 080000h to 0fffffh 040000h to 07ffffh 020000h to 03ffffh 010000h to 01ffffh 00c000h to 00ffffh 008000h to 00bfffh 004000h to 007fffh 000000h to 003fffh refreshing performed at same time as memory access operations in corresponding block refreshing performed exclusively from memory access operations in corresponding block (n = 0 to 7) rfan 23.3.2 operations (1) pulse refresh operation to support the pulse refresh cycles of pseudo-static ram, refresh pulses are output from the refrq pin in synchronization with bus cycles. the system clock frequency and bits 1 and 0 (rft1/rft0) of the refresh mode register (rfm) are adjusted so that 512 or more refresh pulses are generated in an 8-ms period. table 23-1 system clock frequency and refresh pulse output cycle when pseudo-static ram is used system clock frequency refresh pulse output cycle specification rft1 rft0 (f clk ) mhz 8.192 < f clk 16 128/f clk 10 4.096 < f clk 8.192 64/f clk 01 2.048 < f clk 4.096 32/f clk 00 these pulse refresh operations are performed so that they do not overlap external memory access operations. during a refresh cycle, an external memory access cycle is held pending (astb, rd, wr, etc. are inactive), and during an external memory access cycle, a refresh cycle is held pending. if there is no overlapping with an external memory access operation, the refresh cycle is performed without affecting cpu instruction execution. chapter 23 local bus interface function 604 user s manual u11316ej4v1ud (a) internal memory accesses in the case of internal memory accesses in which the external pseudo-static ram is not accessed, also, refresh bus cycles are output at the intervals specified by the refresh mode (rfm) register so that the data stored in the pseudo-static ram is retained. in this case, cpu instruction execution is not affected. figure 23-18 pulse refresh operation in internal memory access refrq pin output refresh cycle note refresh timing counter note cycle specified by the rft1 and rft0 bits of the rfm chapter 23 local bus interface function 605 user s manual u11316ej4v1ud (b) external memory accesses when an access is made to an address corresponding to a cleared (to 0) bit in the refresh area specification register (rfa), a refresh pulse is always output from the refrq pin at the same time as the rd signal or wr signal, irrespective of the cycle specified by the refresh mode register (rfm). after refresh pulse output, accesses to internal memory or accesses to addresses corresponding to a set (to 1) bit in the rfa continue, and after the time specified by the rft0 and rft1 bits of the rfm has elapsed, a refresh bus cycle is generated so as not to overlap a memory access cycle, and a refresh pulse is output. in this way, refreshing can be performed while memory that does not need refreshing, such as prom, is being accessed, refresh bus cycle insertions can be reduced, and instruction execution can be performed efficiently. figure 23-19 refresh pulse output operation astb read cycle write cycle read cycle read cycle refresh bus cycle write cycle time specified by rft0 & rft1 bits of rfm in case of access to area in which memory access operations and refresh operations are performed simultaneously refresh bus cycle is inserted because refresh pulse is not output within time s p ecified b y rft0 & rft1 bits of rfm in case of access to area in which memory access operations and refresh operations are performed exclusively refrq rd wr chapter 23 local bus interface function 606 user s manual u11316ej4v1ud (2) self-refresh operation this mode is used to retain the contents of pseudo-static ram in standby mode. (a) self-refresh operating mode setting when bit 4 (rfen) of the refresh mode (rfm) register is set to 1 , and bit 7 (rflv) to 0 , a low level is output from the refrq pin, and the self-refresh operating mode is specified for the pseudo-static ram. (b) return from self-refresh operation refresh pulse output to the pseudo-static ram is disabled approximately 200 ns note after the refrq pin output level changes from low to high. therefore, the pd784038 arranges for refresh pulses not to be output during the disabled time by raising the refrq pin in synchronization with the refresh timing counter. to enable this low-to-high transition of the refrq pin level to be recognized, the rflv bit read level is set (to 1) when the refrq pin level changes from low to high. note this time varies according to the speed rank, etc. of the pseudo-static ram. figure 23-20 timing for return from self-refresh operation approximately min. 200 ns note refrq rflv bit software set o p eration execution self refresh mode refresh timing counter output note refreshing disabled time chapter 23 local bus interface function 607 user s manual u11316ej4v1ud 23.4 bus hold function the bus hold function is provided for the connection of a device that functions as the bus master, such as a dma controller. in response to a request from the bus master device, all local bus interface pins are set to high impedance (except hldak), and local bus interface mastership is passed to that device. the bus hold function cannot be used when the external wait function or refresh function is used. 23.4.1 hold mode register (hldm) the hldm is an 8-bit register that specifies enabling/disabling of the bus hold function. hldm format is shown in figure 23-21. when reset is input, the hldm register is cleared to 00h, so that the bus hold function is disabled. the hldrq and hldak pins are set to port mode and operate as the p66 and p67 pins. figure 23-21 hold mode register (hldm) format 7 hlde hldm 6 0 5 0 4 0 3 0 2 0 1 0 0 0 disabled port or wait port or refrq enabled hlde p66 p67 hldrq hldak 1 0 address after reset r/w r/w 00h 0ffc5h bus hold enabling/disabling caution the bus hold function must be disabled when the external wait function or refresh function is used. chapter 23 local bus interface function 608 user s manual u11316ej4v1ud 23.4.2 operation when the hlde bit of the hold mode register (hldm) is set (to 1), the bus hold function is enabled. when the bus hold function is enabled, pins p66 and p67 operate as the hldrq and hldak pins respectively. the hldrq pin becomes high-impedance, and the hldak pin outputs a low-level signal. if a high-level signal is input to the hldrq pin when the bus hold function is enabled, at the end of the access operation being executed the address bus (a8 to a19), address/data bus (ad0 to ad7), rd, wr, and astb pins are all set to high- impedance, the hldak pin output level is driven high, and the hold mode is established. at this time, it is recommended to connect a pull-up resistor to the rd and wr pins and a pull-down resistor to the astb pin because the address bus, address/data bus, rd, wr, and astb pins go into a high-impedance state. while the hldak pin is high (in the hold mode) the pd784038 does not use the local bus interface, and therefore an external dma controller, etc. is free to access the memory. when the hldrq pin input level changes from high to low, the hold mode is released, the hldak pin level changes from high to low, and then the pd784038 resumes use of the local bus. a transition to the hold mode is performed between bus cycles, and the instruction being executed may be suspended. when a program is fetched from the internal memory, instructions can be executed until it comes to an instruction that uses the local bus interface. therefore, instruction execution is not stopped unless the external memory is accessed. also, if a transition to the hold mode is made during execution of an instruction that does not use the local bus interface when a program is fetched from the external memory, the pd784038 continues execution of prefetched instructions until it comes to an instruction that uses the local bus interface, and suspends instruction execution when it comes to an instructio n that uses the local bus interface, or when there are no more prefetched instructions. when the hold mode is released, execution of the suspended instruction is resumed from the point at which it was suspended. when a program is fetched from the internal rom or ram, execution of instructions until it comes to an instruction that uses the local bus interface continues. chapter 23 local bus interface function 609 user s manual u11316ej4v1ud figure 23-22 hold mode timing hi-z hi-z hi-z hi-z hi-z hi-z a8 to a19 astb ad0 to ad7 rd hldrq hldak wr 23.5 cautions (1) when the bus hold function is used, the external wait function cannot be used (access wait control by means of the wait pin), and 0, 1 or 2 waits must be selected for the entire space. (2) the refresh function cannot be used when the bus hold function is used. in this case, ensure that refreshing is specified as disabled. (3) do not set external wait to the internal rom area. otherwise, the cpu may be in the deadlock status which can be cleared only by reset input. 610 user? manual u11316ej4v1ud chapter 24 standby function 24.1 configuration and function the pd784038 has a standby function that enables the system power consumption to be reduced. the standby function includes three modes as follows: halt mode........ in this mode the cpu operating clock is stopped. intermittent operation in combination with the normal operating mode enables the total system power consumption to be reduced. idle mode......... in this mode the oscillator continues operating while the entire remainder of the system is stopped. normal program operation can be restored at a low power consumption close to that of the stop mode and in a time equal to that of the halt mode. stop mode........in this mode the oscillator is stopped and the entire system is stopped. ultra-low power consumption can be achieved, consisting of leakage current only. these modes are set by software. the standby mode (stop/idle/halt mode) transition diagram is shown in figure 24-1, and the standby function block diagram in figure 24-2. figure 24-1 standby mode transition diagram wait of oscillation stabilization program operation macro service macro service request end of 1st service end of macro service macro service request end of 1st service stop setting reset input nmi, intp4, intp5 input note 1 idle setting reset input nmi, intp4, intp5 input note 1 interrupt request note 2 reset input halt setting masked interrupt request halt (standby) idle (standby) stop (standby) end of oscillation stabilization time notes 1. when intp4 and intp5 are not masked 2. unmasked interrupt request only remark only external input is valid as nmi. the watchdog timer must not be used to release the standby mode (stop, halt, or idle mode) chapter 24 standby function 611 user s manual u11316ej4v1ud figure 24-2 standby function block diagram extc system clock oscillator fxx/2 fxx/4 fxx/8 fxx/16 frequency divider oscillation stabilization timer (20) osts0 osts1 osts2 extc nmi intp4, intp5 reset rising edge detection rising edge detection falling edge detection falling edge detection selector selector selector esnmi es40, es50 es41, es51 interrupt intc mk ism macro service request selector to peripheral circuit ram protect to peripheral circuit cpu clk hlt f/f idle f/f stp f/f2 stp f/f1 macro service request halt bit setting stop bit setting q s r q q s r q q s r q q s r q valid edge fxx chapter 24 standby function 612 user? manual u11316ej4v1ud 24.2 control registers 24.2.1 standby control register (stbc) the stbc is used to select the stop mode setting and the internal system clock. to prevent entry into standby mode due to an inadvertent program loop, the stbc register can only be written to with a dedicated instruction. this dedicated instruction, mov stbc, #byte, has a special code configuration (4 bytes), and a write is only performed if the 3rd and 4th bytes of the operation code are mutual 1? complements. if the 3rd and 4th bytes of the operation code are not mutual 1? complements, a write is not performed and an operand error interrupt is generated. in this case, the return address saved in the stack area is the address of the instruction that was the source of the error, and thus the address that was the source of the error can be identified from the return address saved in the stack area. if recovery from an operand error is simply performed by means of an retb instruction, an endless loop will result. as an operand error interrupt is only generated in the event of an inadvertent program loop (with the nec electronics assembler, ra78k4, only the correct dedicated instruction is generated when mov stbc, #byte is written), system initialization should be performed by the program. other write instructions (?ov stbc, a? ?nd stbc, #byte? ?et1 stbc.7? etc.) are ignored and do not perform any operation. that is, a write is not performed to the stbc, and an interrupt such as an operand error interrupt is not generated. the stbc can be read at any time by a data transfer instruction. reset input sets the stbc register to 30h. the format of the stbc is shown in figure 24-3. chapter 24 standby function 613 user s manual u11316ej4v1ud figure 24-3 standby control register (stbc) format 7 0 stbc 6 0 5 ck1 4 ck0 3 2 0 1 stp 0 hlt stp hlt operating mode address after reset r/w 0ffc0h 30h r/w 0 0 1 1 0 1 0 1 normal operating mode halt mode stop mode idle mode ck1 ck0 internal system clock selection 0 0 1 1 0 1 0 1 f xx /2 (16 mhz) f xx /4 (8 mhz) f xx /8 (4 mhz) f xx /16 (2 mhz) (f xx = 32 mhz) cautions 1. if the stop mode is used when using external clock input, the extc bit of the oscillation stabilization time specification register (osts) must be set (to 1) before setting stop mode. if the stop mode is used with the extc bit cleared (to 0) when using external clock input, the pd784038 may suffer damage or reduced reliability. when setting the extc bit of osts to 1, be sure to input a clock in phase reverse to that of the clock input to the x1 pin, to the x2 pin (refer to 4.3.1 clock generation circuit). 2. execute an nop instruction three times after the standby instruction (after the standby mode has been released). otherwise, the standby instruction cannot be executed if execution of the standby instruction and an interrupt request contend, and the interrupt is acknowledged after two or more instructions following the standby instruction have been executed. the instruction that is executed before acknowledging the interrupt is the one that is executed within up to 6 clocks after the standby instruction has been executed. example mov stbc, #byte nop nop nop chapter 24 standby function 614 user s manual u11316ej4v1ud 24.2.2 oscillation stabilization time specification register (osts) the osts specifies the oscillator operation and the oscillation stabilization time when stop mode is released. the extc bit of the osts specifies whether crystal/ceramic oscillation or an external clock is used. stop mode can be set when external clock input is used only when the extc bit is set (to 1). bits osts0 to osts2 of the osts select the oscillation stabilization time when stop mode is released. in general, an oscillation stabilization time of at least 40 ms should be selected when a crystal resonator is used, and at least 4 ms when a ceramic oscillator is used. the time taken for oscillation stabilization is affected by the crystal resonator or ceramic resonator used, and the capacitance of the connected capacitor. therefore, if you want to set a short oscillation stabilization time, you should consu lt the crystal resonator or ceramic resonator manufacturer. the osts can be written to only with an 8-bit transfer instruction. reset input clears the osts register to 00h. the format of the osts is shown in figure 24-4. figure 24-4 oscillation stabilization time specification register (osts) format 7 extc osts 6 0 5 0 4 0 3 0 2 osts2 1 osts1 0 osts0 extc osts2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 osts1 0 0 1 1 0 0 1 1 osts0 address after reset r/w 0ffcfh 00h r/w 0 1 0 1 0 1 0 1 extc external clock selection oscillation stabilization time selection bits 0 1 when crystal/ceramic oscillation is used when external clock is used 2 20 /f xx (32.80 ms) 2 19 /f xx (16.40 ms) 2 18 /f xx (8.19 ms) 2 17 /f xx (4.10 ms) 2 16 /f xx (2.05 ms) 2 15 /f xx (1.02 ms) 2 14 /f xx (512 s) 2 13 /f xx (256 s) 512/f xx (16 s) (f xx = 32 mhz) cautions 1. when crystal/ceramic oscillation is used, the extc bit of the oscillation stabilization time specification register (osts) must be cleared (to 0) before use. if the extc bit is set (to 1), oscillation will stop. 2. if the stop mode is used when using external clock input, the extc bit must be set (to 1) before setting stop mode. if the stop mode is used with the extc bit cleared (to 0) the pd784038 may suffer damage or reduced reliability. when setting the extc bit of osts to 1, be sure to input a clock in phase reverse to that of the clock input to the x1 pin, to the x2 pin (refer to 4.3.1 clock generation circuit). chapter 24 standby function 615 user s manual u11316ej4v1ud 24.3 halt mode 24.3.1 halt mode setting and operating states the halt mode is selected by setting (to 1) the hlt bit of the standby control (stbc) register. the only writes that can be performed on the stbc are 8-bit data writes by means of a dedicated instruction. halt mode setting is therefore performed by means of the mov stbc/#byte instruction. write a nop instruction three times after the instruction that sets the halt mode (after releasing the halt mode). otherwise, two or more instructions may be executed before an interrupt is acknowledged. as a result, the execution sequence of the interrupt processing and instructions may be changed. to prevent troubles due to changes in the execution sequence, the above processing is necessary. caution if halt mode setting is performed when a condition that releases halt mode is in effect, halt mode is not entered, and execution of the next instruction, or a branch to a vectored interrupt service program, is performed. to ensure that a definite halt mode setting is made, interrupt requests should be cleared (to 0), etc. before entering halt mode. table 24-1 operating states in halt mode clock oscillator operating internal system clock operating cpu operation stopped note i/o lines retain state prior to halt mode setting peripheral functions continue operating internal ram retained bus lines ad0 to ad7 high-impedance a8 to a19 retained rd, wr output high level astb output low level refrq output continue operating hldrq input continue operating (input) hldak output continue operating note macro service processing is executed. 24.3.2 halt mode release halt mode can be released by the following three sources. non-maskable interrupt request (nmi pin input only) maskable interrupt request (vectored interrupt/context switching/macro service) reset input release sources and an outline of operations after release are shown in table 24-2. figure 24-5 shows operations after halt mode release. chapter 24 standby function 616 user s manual u11316ej4v1ud table 24-2 halt mode release and operations after release release source mk note 1 ie note 2 state on release operation after release reset input normal reset operation non-maskable non-maskable interrupt service program interrupt request acknowledgment interrupt request not being executed (nmi pin input low-priority non-maskable interrupt only, excluding service program being executed watchdog timer) service program for same request being execution of instruction after mov stbc/ note 6 executed #byte instruction (interrupt request that high-priority non-maskable interrupt released halt mode is held pending service program being executed note 3 ) maskable 0 1 interrupt service program not being interrupt request acknowledgment interrupt request executed (excluding macro low-priority maskable interrupt service service request) program being executed prsl bit note 4 cleared (to 0) during execution of priority level 3 interrupt service program same-priority maskable interrupt service execution of instruction after mov stbc/ program being executed #byte instruction (interrupt request that (if prsl bit note 4 is cleared (to 0), excluding released halt mode is held pending note 3 ) execution of priority level 3 interrupt service program) high-priority interrupt service program being executed 00 1 halt mode maintained macro service 0 macro service processing execution request end condition not established halt mode again end condition established if vcie note 5 = 1: halt mode again if vcie note 5 = 0: same as release by maskable interrupt request 1 halt mode maintained notes 1. interrupt mask bit in individual interrupt request source 2. interrupt enable flag in program status word (psw) 3. pending interrupt requests are acknowledged when acknowledgment becomes possible. 4. bit in interrupt mode control register (imc) 5. bit in macro service mode register of macro service control word in individual macro service request source 6. the watchdog timer cannot be used to release the halt mode. chapter 24 standby function 617 user s manual u11316ej4v1ud figure 24-5 operation after halt mode release (1/4) (1) when interrupt generates after halt mode has been set interrupt request halt mode release interrupt processing main routine halt mode mov stbc, #byte (2) reset after halt mode has been set reset input normal reset operation main routine halt mode mov stbc, #byte chapter 24 standby function 618 user s manual u11316ej4v1ud figure 24-5 operation after halt mode release (2/4) (3) when halt mode is set while interrupt routine with priority higher than or same as that of interrupt of release source main routine int halt mode release interrupt of halt mode release source kept pending execution of pending interrupt mov stbc, #byte halt mode (4) when halt mode is set while interrupt routine with priority lower than that of interrupt of release source int mov stbc, #byte halt mode halt mode release execution of interrupt of halt mode release source main routine chapter 24 standby function 619 user s manual u11316ej4v1ud figure 24-5 operation after halt mode release (3/4) (5) when macro service request is generated in halt mode (a) when end condition of macro service is satisfied and interrupt request is generated immediately (vcie = 0) last macro service request macro service processing halt mode release servicing of interrupt request due to end of macro service mov stbc, #byte main routine halt mode (b) when end condition of macro service is not satisfied, or if end condition of macro service is satisfied but interrupt request is not generated immediately (vcie = 1) last macro service request macro service processing halt mode release mov stbc, #byte main routine halt mode interrupt processing chapter 24 standby function 620 user s manual u11316ej4v1ud figure 24-5 operation after halt mode release (4/4) (6) when interrupt generates during execution of instruction that temporarily keeps interrupt pending, and if halt mode is set while that interrupt is kept pending halt mode release interrupt processing mov stbc, #byte main routine ei interrupt request interrupt is kept pending for duration of 8 clocks (7) when halt instruction and interrupt contend interrupt processing mov stbc, #byte main routine interrupt request halt mode is not executed instructions are executed up to the 6th clock chapter 24 standby function 621 user s manual u11316ej4v1ud (1) release by non-maskable interrupt when a non-maskable interrupt is generate, the pd784038 is released from halt mode irrespective of whether the interrupt acknowledgment enabled state (ei) or disabled state (di) is in effect. when the pd784038 is released from halt mode, if the non-maskable interrupt that released halt mode can be acknowledged, acknowledgment of that non-maskable interrupt is performed and a branch is made to the service program. if the interrupt cannot be acknowledged, the instruction following the instruction that set the halt mode (the mov stbc/#byte instruction) is executed, and the non-maskable interrupt that released the halt mode is acknowledged when acknowledgment becomes possible. see 22.6 non-maskable interrupt acknowledgment operation for details of non-maskable interrupt acknowledgment. caution the watchdog timer cannot be used to release the halt mode. (2) release by maskable interrupt request halt mode release by a maskable interrupt request can only be performed by an interrupt for which the interrupt mask flag is 0. when halt mode is released, if an interrupt can be acknowledged when the interrupt request enable flag (ie) is set (to 1), a branch is made to the interrupt service program. if the interrupt cannot be acknowledged and if the ie flag is cleared (to 0), execution is resumed from the instruction following the instruction that set the halt mode. see 22.7 maskable interrupt acknowledgment operation for details of interrupt acknowledgment. with macro service, halt mode is released temporarily, service is performed once, then halt mode is restored. when macro service has been performed the specified number of times, halt mode is released if the vcic bit in the macro service mode register of the macro service control word is cleared (to 0). the operation after release in this case is the same as for release by a maskable interrupt described earlier. if the vcie bit is set (to 1), the halt mode is entered again and is released by the next interrupt request. chapter 24 standby function 622 user s manual u11316ej4v1ud table 24-3 halt mode release by maskable interrupt request release source mk note 1 ie note 2 state on release operation after release maskable 0 1 interrupt service program not being interrupt request acknowledgment interrupt request executed (excluding macro low-priority maskable interrupt service service request) program being executed prsl bit note 4 cleared (to 0) during execution of priority level 3 interrupt service program same-priority maskable interrupt service execution of instruction after mov stbc/ program being executed #byte instruction (interrupt request that (if prsl bit note 4 is cleared (to 0), excluding released halt mode is held pending note 3 ) execution of priority level 3 interrupt service program) high-priority interrupt service program being executed 00 1 halt mode maintained macro service 0 macro service processing execution request end condition not established halt mode again end condition established if vcie note 5 = 1: halt mode again if vcie note 5 = 0: same as release by maskable interrupt request 1 halt mode maintained notes 1. interrupt mask bit in individual interrupt request source 2. interrupt enable flag in program status word (psw) 3. pending interrupt requests are acknowledged when acknowledgment becomes possible. 4. bit in interrupt mode control register (imc) 5. bit in macro service mode register of macro service control word in individual macro service request source (3) release by reset input the program is executed after branching to the reset vector address, as in a normal reset operation. however, internal ram contents retain their value directly before halt mode was set. chapter 24 standby function 623 user s manual u11316ej4v1ud 24.4 stop mode 24.4.1 stop mode setting and operating states the stop mode is selected by setting (to 1) the stp bit of the standby control register (stbc) register. the only writes that can be performed on the stbc register are 8-bit data writes by means of a dedicated instruction. stop mode setting is therefore performed by means of the mov stbc/#byte instruction. if interrupts are enabled (when the ie flag of psw is set to 1), write a nop instruction three times after the instruction that sets the stop mode (after releasing the stop mode). otherwise, two or more instructions may be executed before an interrupt is acknowledged. as a result, the execution sequence of the interrupt processing and instructions may be changed. to prevent troubles due to changes in the execution sequence, the above processing is necessary. caution if the stop mode is set when the condition to release the halt mode is satisfied (refer to 24.3.2 halt mode release), the stop mode is not set, but the next instruction is executed or execution branches to a vectored interrupt service program. to accurately set the stop mode, clear the interrupt request before setting the stop mode. table 24-4 operating states in stop mode clock oscillator oscillation stopped internal system clock stopped cpu operation stopped i/o lines retain state prior to stop mode setting peripheral functions all operation stopped note internal ram retained bus lines ad0 to ad7 high-impedance a8 to a19 high-impedance rd, wr output high-impedance astb output high-impedance refrq output retained hldrq input high-impedance hldak output low level note a/d converter operation is stopped, but if the cs bit of the a/d converter mode register (adm) is set (to 1), the power consumption does not decrease. d/a converter operation is not stopped. cautions 1. when the stop mode is used in a system that uses an external clock, the extc bit of the osts must be set (to 1). if stop mode setting is performed in a system to which an external clock is input when the extc bit of the osts is cleared (to 0), the power consumption increases. when setting the extc bit of osts to 1, be sure to input a clock in phase reverse to that of the clock input to the x1 pin, to the x2 pin (refer to 4.3.1 clock generation circuit). 2. the cs bit of the a/d converter mode (adm) register should be cleared (to 0). 3. d/a converter operation is not stopped simply by setting the stop mode. in order to reduce the power consumption, the dacen (n = 0, 1) bits of the d/a converter mode register (dam) must both be cleared (to 0). when dacen is cleared (to 0), the anon (n = 0, 1) pin output level becomes high- impedance. chapter 24 standby function 624 user s manual u11316ej4v1ud 24.4.2 stop mode release stop mode is released by nmi input, intp4 input, and reset input. release sources and an outline of operations after release are shown in table 24-5. figure 24-6 shows operations after stop mode release. table 24-5 stop mode release and operations after release release source mk note 1 ism note 2 ie note 3 state after release operation after release reset input normal reset operation nmi pin input non-maskable interrupt service interrupt request acknowledgment program not being executed low-priority non-maskable interrupt service program being executed nmi pin input service program being execution of instruction after mov executed stbc/#byte instruction (interrupt high-priority non-maskable interrupt request that released stop mode is service program being executed held pending note 4 ) intp4/intp5 0 0 1 interrupt service program not being interrupt request acknowledgment pin input executed low-priority maskable interrupt service program being executed prsl bit note 5 cleared (to 0) during execution of priority level 3 interrupt service program same-priority maskable interrupt execution of instruction after mov service program being executed stbc/#byte instruction (interrupt (if prsl bit note 5 is cleared (to 0), request that released stop mode is excluding execution of priority level 3 held pending note 4 ) interrupt service program) high-priority interrupt service program being executed 000 1 0 stop mode maintained 1 notes 1. interrupt mask bit in individual interrupt request source 2. macro service enable flag in individual interrupt request source 3. interrupt enable flag in program status word (psw) 4. pending interrupt requests are acknowledged when acknowledgment becomes possible. 5. bit in interrupt mode control register (imc) chapter 24 standby function 625 user s manual u11316ej4v1ud figure 24-6 operation after stop mode release (1/2) (1) when interrupt generates after stop mode has been set interrupt request stop mode release interrupt processing main routine stop mode mov stbc, #byte (2) reset after stop mode has been set reset input normal reset operation main routine stop mode mov stbc, #byte chapter 24 standby function 626 user s manual u11316ej4v1ud figure 24-6 operation after stop mode release (2/2) (3) when stop mode is set while interrupt routine with priority higher than or same as that of interrupt of release source main routine int stop mode release interrupt of stop mode release source kept pending execution of pending interrupt mov stbc, #byte stop mode (4) when stop mode is set while interrupt routine with priority lower than that of interrupt of release source int mov stbc, #byte stop mode stop mode release execution of interrupt of stop mode release source main routine chapter 24 standby function 627 user s manual u11316ej4v1ud (1) stop mode release by nmi input the oscillator resumes oscillation when the valid edge specified by external interrupt mode register 0 (intm0) is input to the nmi input. stop mode is released after the oscillation stabilization time specified by the oscillation stabilization time specification register (osts) elapses. when the pd784038 is released from stop mode, if a non-maskable interrupt by nmi pin input can be acknowledged, a branch is made to the nmi interrupt service program. if the interrupt cannot be acknowledged (if the stop mode is set in an nmi interrupt service program, etc.), execution is resumed from the instruction following the instruction that set the stop mode, and a branch is made to the nmi interrupt service program when acknowledgment becomes possible (by execution of an reti instruction, etc.). see 22.6 non-maskable interrupt acknowledgment operation for details of nmi interrupt acknowledgment. figure 24-7 stop mode release by nmi input oscillator fxx/2 stp f/f1 nmi input rising edge specified stp f/f2 oscillator stopped stop oscillation stabilization count time chapter 24 standby function 628 user s manual u11316ej4v1ud (2) stop mode release by intp4 or intp5 input when masking of interrupts by intp4 and intp5 input is released and macro service is disabled, the oscillator resumes oscillation when the valid edge specified by external interrupt mode register 1 (intm1) is input to the intp4 or intp5 input. following this, stop mode is released after the oscillation stabilization time specified by the oscillation stabilization time specification register (osts) elapses. when the pd784038 is released from stop mode, if an interrupt can be acknowledged when the interrupt enable flag (ie) is set (to 1), a branch is made to the interrupt service program. if the interrupt cannot be acknowledged and if the ie flag is cleared (to 0), execution is resumed from the instruction following the instruction that set the stop mode. see 22.7 maskable interrupt acknowledgment operation for details of interrupt acknowledgment. figure 24-8 stop mode release by intp4/intp5 input intp4, intp5 input rising edge specified oscillator fxx/2 stp f/f1 stp f/f2 oscillation stopped stop oscillation stabilization count time (3) stop mode release by reset input when reset input falls from high to low and the reset state is established, the oscillator resumes oscillation. the oscillation stabilization time should be secured while reset is active. thereafter, normal operation is started when reset rises. unlike an ordinary reset operation, data memory retains its contents prior to stop mode setting. chapter 24 standby function 629 user s manual u11316ej4v1ud 24.5 idle mode 24.5.1 idle mode setting and operating states the idle mode is selected by setting (to 1) both the stp bit and the hlt bit of the standby control (stbc) register. the only writes that can be performed on the stbc are 8-bit data writes by means of a dedicated instruction. idle mode setting is therefore performed by means of the mov stbc/#byte instruction. write a nop instruction three times after the instruction that sets the idle mode (after releasing the idle mode). otherwise, two or more instructions may be executed before an interrupt is acknowledged. as a result, the execution sequence of the interrupt processing and instructions may be changed. to prevent troubles due to changes in the execution sequence, the above processing is necessary. caution if the idle mode is set when the condition to release the halt mode is satisfied (refer to 24.3.2 halt mode release), the idle mode is not set, but the next instruction is executed or execution branches to a vectored interrupt service program. to accurately set the idle mode, clear the interrupt request before setting the idle mode. table 24-6 operating states in idle mode clock oscillator oscillation stopped internal system clock stopped cpu operation stopped i/o lines retain state prior to idle mode setting peripheral functions all operation stopped note internal ram retained bus lines ad0 to ad7 high-impedance a8 to a19 high-impedance rd, wr output high-impedance astb output high-impedance refrq output retained hldrq input high-impedance hldak output low level note a/d converter operation is stopped, but if the cs bit of the a/d converter mode register (adm) is set, the power consumption does not decrease. d/a converter operation is not stopped. cautions 1. the cs bit of the a/d converter mode (adm) register should be reset. 2. d/a converter operation is not stopped simply by setting the idle mode. in order to reduce the power consumption, the dacen (n = 0, 1) bits of the d/a converter mode register (dam) must both be cleared (to 0). when dacen is cleared (to 0), the anon (n = 0, 1) pin output level becomes high- impedance. chapter 24 standby function 630 user? manual u11316ej4v1ud 24.5.2 idle mode release idle mode is released by nmi input, intp4 input, intp5 input, or reset input. release source and an outline of operations after release are shown in table 24-7. figure 24-9 shows operations after idle mode release. table 24-7 idle mode release and operations after release release source mk note 1 ism note 2 ie note 3 state after release operation after release reset input normal reset operation nmi pin input non-maskable interrupt service interrupt request acknowledgment program not being executed low-priority non-maskable interrupt service program being executed nmi pin input service program being execution of instruction after mov executed stbc/#byte instruction (interrupt high-priority non-maskable interrupt request that released idle mode is service program being executed held pending note 4 ) intp4/intp5 0 0 1 interrupt service program not being interrupt request acknowledgment pin input executed low-priority maskable interrupt service program being executed prsl bit note 5 cleared (to 0) during execution of priority level 3 interrupt service program same-priority maskable interrupt execution of instruction after mov service program being executed stbc/#byte instruction (interrupt (if prsl bit note 5 is cleared (to 0), request that released idle mode is excluding execution of priority level 3 held pending note 4 ) interrupt service program) high-priority interrupt service program being executed 000 10 idle mode maintained 1 notes 1. interrupt mask bit in individual interrupt request source 2. macro service enable flag in individual interrupt request source 3. interrupt enable flag in program status word (psw) 4. pending interrupt requests are acknowledged when acknowledgment becomes possible. 5. bit in interrupt mode control register (imc) chapter 24 standby function 631 user s manual u11316ej4v1ud figure 24-9 operation after idle mode release (1/2) (1) when interrupt generates after idle mode has been set interrupt request idle mode release interrupt processing main routine idle mode mov stbc, #byte (2) reset after idle mode has been set reset input normal reset operation main routine idle mode mov stbc, #byte chapter 24 standby function 632 user s manual u11316ej4v1ud figure 24-9 operation after idle mode release (2/2) (3) when idle mode is set while interrupt routine with priority higher than or same as that of interrupt of release source main routine int idle mode release interrupt of idle mode release source kept pending execution of pending interrupt mov stbc, #byte idle mode (4) when idle mode is set while interrupt routine with priority lower than that of interrupt of release source int mov stbc, #byte idle mode idle mode release execution of interrupt of idle mode release source main routine chapter 24 standby function 633 user s manual u11316ej4v1ud (1) idle mode release by nmi input idle mode is released when the valid edge specified by external interrupt mode register 0 (intm0) is input to the nmi input. when the pd784038 is released from idle mode, if a non-maskable interrupt by nmi pin input can be acknowledged, a branch is made to the nmi interrupt service program. if the interrupt cannot be acknowledged (if the idle mode is set in an nmi interrupt service program, etc.), execution is resumed from the instruction following the instruction that set the idle mode, and a branch is made to the nmi interrupt service program when acknowledgment becomes possible (by execution of an reti instruction, etc.). see 22.6 non-maskable interrupt acknowledgment operation for details of nmi interrupt acknowledgment. (2) idle mode release by intp4 or intp5 input when masking of interrupts by intp4 and intp5 input is released and macro service is disabled, idle mode is released when the valid edge specified by external interrupt mode register 1 (intm1) is input to the intp4 or intp5 input. when the pd784038 is released from idle mode, if an interrupt can be acknowledged when the interrupt enable flag (ie) is set (to 1), a branch is made to the interrupt service program. if the interrupt cannot be acknowledged and if the ie flag is cleared (to 0), execution is resumed from the instruction following the instruction that set the idle mode. see 22.7 maskable interrupt acknowledgment operation for details of interrupt acknowledgment. chapter 24 standby function 634 user s manual u11316ej4v1ud 24.6 check items when stop mode/idle mode is used check items required to reduce the power consumption when stop mode/idle mode is used are shown below. (1) is the output level of each output pin appropriate? the appropriate output level for each pin varies according to the next-stage circuit. you should select the output level that minimizes the power consumption. if high level is output when the input impedance of the next-stage circuit is low, a current will flow from the power supply to the port, resulting in an increased power consumption. this applies when the next-stage circuit is a cmos ic, etc. when the power supply is off, the input impedance of a cmos ic is low. in order to suppress the power consumption, or to prevent an adverse effect on the reliability of the cmos ic, low level should be output. if a high level is output, latchup may result when power is turned on again. depending on the next-stage circuit, inputting low level may increase the power consumption. in this case, high- level or high-impedance output should be used to reduce the power consumption. if the next-stage circuit is a cmos ic, the power consumption of the cmos ic may increase if the output is made high-impedance when power is supplied to it (the cmos ic may also be overheated and damaged). in this case you should output an appropriate level, or pull the output high or low with a resistor. the method of setting the output level depends on the port mode. when a port is in control mode, the output level is determined by the status of the on-chip hardware, and therefore the on-chip hardware status must be taken into consideration when setting the output level. in port mode, the output level can be set by writing to the port output latch and port mode register by software. when a port is in control mode, its output level can be set easily by changing to port mode. (2) is the input pin level appropriate? the voltage level input to each pin should be in the range between v ss potential and v dd potential. if a voltage outside this range is applied, the power consumption will increase and the reliability of the pd784038 may be adversely affected. also ensure that an intermediate potential is not applied. (3) are pull-up resistors necessary? an unnecessary pull-up resistor will increase the power consumption and cause a latchup of other devices. a mode should be specified in which pull-up resistors are used only for parts that require them. if there is a mixture of parts that do and do not require pull-up resistors, for parts that do, you should connect a pull- up resistor externally and specify a mode in which the on-chip pull-up resistor is not used. chapter 24 standby function 635 user? manual u11316ej4v1ud (4) is processing of the address bus, address/data bus, etc., appropriate? in stop mode and idle mode, the address bus, address/data bus, rd and wr pins become high-impedance. normally, these pins are pulled high with a pull-up resistor. if this pull-up resistor is connected to the backed-up power supply, then if the input impedance of circuitry connected to the non-backed-up power supply is low, a current will flow through the pull-up resistor, and the power consumption will increase. therefore, the pull-up resistor should be connected to the non-backed-up power supply side as shown in figure 24-10. also, in stop mode and idle mode the astb pin also becomes high impedance, and the refrq/hldak pin adopts a fixed level. countermeasures should be taken with reference to the points noted in (1). figure 24-10 example of address/data bus processing v dd v dd in/out cmos ic, etc. v ss v ss non-backed-up power supply adn (n = 0 to 7) pd784038 backed-up power supply the voltage level input to the wait/hldrq pin should be in the range between v ss potential and v dd potential. if a voltage outside this range is applied, the power consumption will increase and the reliability of the pd784038 may be adversely affected. (5) a/d converter the current flowing to the av dd , av ref1 pins can be reduced by clearing (to 0) the cs bit (bit 7) of the a/d converter mode register (adm). make sure that the av dd pin is not at the same potential as the v dd pin. unless power is supplied to the av dd pin in the stop mode, not only does the power consumption increase, but the reliability is also affected. (6) d/a converter in the stop mode and idle mode the d/a converter still consumes a certain power. clearing (to 0) the both dacen (n = 0, 1) bits of the d/a converter mode register (dam) sets the anon (n = 0/1) output to high impedance, enabling the power consumption to be reduced. (power consumption is not reduced if only one of the dacen bits is cleared to 0). the power consumption at resistor string can be eliminated by setting the voltage input to the av ref2 pin to the same potential as av ref3 . the anon output when the dacen bit of the dam is set (to 1) will be at the same potential as av ref3 , and therefore the av ref3 pin voltage should be set so as to minimize the power consumption of the next-stage circuit. the power consumption of the pd784038 can be minimized by clearing both the dacen bits of dam to 0. however, the output of the anon pin goes into a high-impedance state. also, a voltage should not be applied to the anon pins from off-chip, as this may result in an increase in the power consumption, and the pd784038 may suffer damage or reduced reliability. chapter 24 standby function 636 user s manual u11316ej4v1ud 24.7 cautions (1) if halt/stop/idle mode (standby mode hereafter) setting is performed when a condition that release halt mode (refer to 24.3.2 halt mode release ) is satisfied, standby mode is not entered, and execution of the next instruction, or a branch to a vectored interrupt service program, is performed. to ensure that a definite standby mode setting is made, interrupt requests should be cleared, etc. before entering standby mode. (2) when crystal/ceramic oscillation is used, the extc bit must be cleared (to 0) before use. if the extc bit is set (to 1), oscillation will stop. (3) when the stop mode is used in a system that uses an external clock, the extc bit of the osts must be set (to 1). if stop mode setting is performed in a system to which an external clock is input when the extc bit of the osts is cleared (to 0), the power consumption increases. when setting the extc bit of osts to 1, be sure to input a clock in phase reverse to that of the clock input to the x1 pin, to the x2 pin (refer to 4.3.1 clock generation circuit ). (4) in stop mode and idle mode, the cs bit of the a/d converter mode adm register should be cleared (to 0). (5) d/a converter operation is not stopped simply by setting the stop mode or idle mode. in order to reduce the power consumption, the dacen (n = 0, 1) bits of the d/a converter mode register (dam) must both be cleared (to 0). when dacen is cleared (to 0), the anon (n = 0, 1) pin output level becomes high-impedance. (6) execute an nop instruction three times after the standby instruction (after the standby mode has been released). otherwise, the standby instruction cannot be executed if execution of the standby instruction and an interrupt request contend, and the interrupt is acknowledged after two or more instructions following the standby instruction have been executed. the instruction that is executed before acknowledging the interrupt is the one that is executed within up to 6 clocks after the standby instruction has been executed. example mov stbc, #byte nop nop nop 637 user? manual u11316ej4v1ud chapter 25 reset function 25.1 reset function when low level is input to the reset input pin, a system reset is affected, the various hardware units are set to the states shown in table 25-2, and all pins except the power supply pins and the x1 and x2 pins are placed in the high- impedance state. table 25-1 shows the pin statuses on reset and after reset release. when the reset input changes from low to high level, the reset state is released, the contents of address 00000h of the reset vector table are set in bits 0 to 7 of the program counter (pc), the contents of address 00001h in bits 8 to 15, and 0000b in bits 16 to 19, a branch is made, and program execution is started at the branch destination address. a reset start can therefore be performed from any address in the base area. the contents of the various registers should be initialized as required in the program in the base area. to prevent from malfunction due to noise, the reset input pin incorporates an analog delay noise elimination circuit (see figure 25-1 ). figure 25-1 reset signal acknowledgment delay pc initialization, etc. execution of instruction at reset start address reset start delay delay reset end internal reset signal reset (input) chapter 25 reset function 638 user s manual u11316ej4v1ud in a reset operation upon powering on, the reset signal must be kept active until the oscillation stabilization time has elapsed (approx. 40 ms, depending on the resonator used). figure 25-2 power-on reset operation oscillation stabilization time v dd delay pc initialization, etc. execution of instruction at reset start address internal reset signal reset end reset (input) remark f clk : internal system clock frequency table 25-1 pin statuses during reset input and after reset release pin name input/output on reset directly after reset release p00 to p07 input/output hi-z hi-z (input port mode) p10/pwm0 to p17 input/output hi-z hi-z (input port mode) p20/nmi to p27/si input hi-z hi-z (input port) p30/rxd to p37/to3 input/output hi-z hi-z (input port mode) p40/ad0 to p47/ad7 input/output hi-z hi-z (input port mode) note 1 p50/a8 to p57/a15 input/output hi-z hi-z (input port mode) note 1 p60/a16 to p63/a19 note 2 input/output hi-z hi-z (input port mode) note 1 p64/rd, p65/wr input/output hi-z hi-z (input port mode) note 1 p66/wait, p67/refrq input/output hi-z hi-z (input port mode) p70/ani0 to p77/ani7 input/output hi-z hi-z (input port mode) astb/clkout output hi-z 0 ano0, ano1 output hi-z outputs av ref3 pin input voltage notes 1. with the pd784031, these pins function as the address/data bus pins, and output signal to fetch the reset vector address from address 0000h (refer to figure 25-3 (a)). 2. with the pd784031, these pins function only as the output port pins, and output 0 after reset release. chapter 25 reset function 639 user s manual u11316ej4v1ud table 25-2 hardware states after reset (1/2) hardware state after reset program counter (pc) set with contents of reset vector table (0000h/0001h). stack pointer (sp) undefined note 1 program status word (psw) 02h on-chip ram data memory undefined note 1 general-purpose registers ports ports 0, 1, 2, 3, 4, 5, 6 note 2 , 7 undefined (high impedance) port mode registers pm0, 1, 3, 4, 5, 6 note 3 , 7 ffh port mode control registers (pmc1, pmc3) 00h pull-up resistor option register (puo) 00h real-time output port control register (rtpc) 00h timer/counter timer registers (tm0, tm1w, tm2w, tm3w) 0000h compare registers (cr00, cr01, cr10lw, cr20w, cr30w) undefined capture registers (cr02, cr12w, cr22w) capture/compare registers (cr11w, cr21w) timer control registers (tmc0, tmc1) 00h timer output control register (toc) capture/compare control registers crc0 10h crc1, crc2 00h prescaler mode registers (prm0, prm1) 00h one-shot pulse output control register (ospc) 00h pwm pwm control register (pwmc) 05h pwm prescaler register (pwpr) 00h pwm modulo registers (pwm0, pwm1) undefined a/d converter a/d converter mode register (adm) 00h a/d conversion result register (adcr) undefined d/a converter d/a converter mode register (dam) 03h d/a conversion value setting registers (dacs0, dacs1) 00h notes 1. when halt mode, stop mode or idle mode is released by reset input, the value before that mode was set is retained. 2. pd784031: x0h 3. pd784031: fxh chapter 25 reset function 640 user s manual u11316ej4v1ud table 25-2 hardware states after reset (2/2) hardware state after reset serial interface clocked serial interface mode registers (csim, csim1, csim2) 00h shift registers (sio, sio1, sio2) undefined asynchronous serial interface mode registers (asim, asim2) 00h asynchronous serial interface status registers (asis, asis2) 00h i 2 c bus control register (iicc) 00h serial receive buffers (rxb, rxb2) undefined serial transmit shift registers (txs, txs2) undefined baud rate generator control registers (brgc, brgc2) 00h prescaler mode register for serial clock (sprm) 04h slave address register (sva) note 01h clock output function (clom) 00h memory extension mode register (mm) 20h programmable wait control registers pwc1 aah pwc2 aaaah refresh function refresh mode register (rfm) 00h refresh area specification register (rfa) 00h hold mode register (hldm) 00h interrupts interrupt control registers (pic0, pic1, pic2, pic3, pic4, pic5, cic00, 43h cic01, cic10, cic11, cic20, cic21, cic30, adic, seric, sric, stic, seric2, sric2, stic2, csiic, csiic1, csiic2, spcic note ) interrupt mask registers mk0 ffffh mk1l ffh in-service priority register (ispr) 00h interrupt mode control register (imc) 00h external interrupt mode registers (intm0, intm1) 00h sampling clock selection register (scs0) 00h standby control register (stbc) 30h oscillation stabilization time specification register (osts) 00h internal memory size switching register (ims) ffh note pd784038y subseries only chapter 25 reset function 641 user s manual u11316ej4v1ud figure 25-3 reset input timing (a) pd784031 hi-z hi-z a8 to a19 (output) astb (output) hi-z ad0 to ad7 hi-z av ref2 av ref3 hi-z other i/o ports hi-z hi-z rd (output) ano0, ano1 reset (input) wr (output) reset period reset release instruction execution period program (input) address (output) (b) pd784038 hi-z av ref2 av ref3 hi-z other i/o ports ano0, ano1 reset (input) hi-z astb (output) reset period reset release instruction execution period chapter 25 reset function 642 user s manual u11316ej4v1ud 25.2 caution reset input when powering on must remain at the low level until oscillation stabilizes after the supply voltage has reached the prescribed voltage. 643 user? manual u11316ej4v1ud chapter 26 pd78p4038 programming the pd78p4038 incorporates a 128-kbyte prom as program memory. when programming the pd78p4038, the prom programming mode is set by means of the v pp pin and the reset pin. for the connection of unused pins, see 1.3.2 prom programming mode in 1.3 pin configuration (top view). 26.1 operating modes when +5 v or +12.5 v is applied to the v pp pin and a low-level signal is applied to the reset pin, the pd78p4038 is placed in the prom programming mode. this is one of the operating modes shown in table 26-1 below according to the setting of the ce, oe, and pgm pins. the prom contents can be read by setting the read mode. table 26-1 prom programming operating modes pins reset v pp v dd ce oe pgm d0 to d7 operating mode page data latch l +12.5 v +6.5 v h l h data input page write h h l high-impedance byte write l h l data input program verify l l h data output program inhibit h h high-impedance ll read +5 v +5 v l l h data output output disable l h high-impedance standby h high-impedance remark : l or h chapter 26 pd78p4038 programming 644 user? manual u11316ej4v1ud (1) read mode read mode is set by setting ce to l and oe to l. (2) output disable mode if oe is set to h, data output becomes high impedance and the output disable mode is set. therefore, if multiple pd78p4038s are connected to the data bus, data can be read from any one device by controlling the oe pin. (3) standby mode setting ce to h sets the standby mode. in this mode, data output becomes high-impedance irrespective of the status of oe. (4) page data latch mode setting ce to h, pgm to h, and oe to l at the start of the page write mode sets the page data latch mode. in this mode, 1-page 4-byte data is latched in the internal address/data latch circuit. (5) page write mode after 1-page 4-byte address and data are latched in the page data latch mode, a page write is executed by applying a 0.1 ms program pulse (active-low) to the pgm pin while ce = h and oe = h. after this, program verification can be performed by setting ce to l and oe to l. if programming is not performed by one program pulse, repeated write and verify operations are executed x times (x 10). (6) byte write mode a byte write is executed by applying a 0.1 ms program pulse (active-low) to the pgm pin while ce = l and oe = h. after this, program verification can be performed by setting oe to l. if programming is not performed by one program pulse, repeated write and verify operations are executed x times (x 10). (7) program verify mode setting ce to l, pgm to h, and oe to l sets the program verify mode. after writing is performed, this mode should be used to check whether the data has been written correctly. (8) program inhibit mode the program inhibit mode is used when the oe pins, v pp pins and pins d0 to d7 of multiple pd78p4038s are connected in parallel, and you wish to write to one of these devices. the page write mode or byte write mode described above is used to perform a write. at this time, a write is not performed on devices on which the pgm pin is driven high. chapter 26 pd78p4038 programming 645 user? manual u11316ej4v1ud 26.2 prom write procedure figure 26-1 page program mode flowchart end of write verify 4 bytes fail no start address = g v dd = 6.5 v, v pp = 12.5 v x = 0 latch address = address + 1 latch address = address + 1 latch address = address + 1 latch x = x + 1 0.1 ms program pulse address = n? verification of all bytes v dd = 4.5 to 5.5 v, v pp = v dd address = address + 1 x = 10 ? defective product yes fail pass no yes all pass pass remark g = start address n = last address of program chapter 26 pd78p4038 programming 646 user s manual u11316ej4v1ud figure 26-2 page program mode timing v pp a0, a1 data input v dd a2 to a16 d0 to d7 data output oe ce pgm v ih v il v ih v il v ih v il v dd + 1.5 v dd v pp v dd page data latch page verify page program chapter 26 pd78p4038 programming 647 user s manual u11316ej4v1ud figure 26-3 byte program mode flowchart end of write verify fail no start address = g v dd = 6.5 v, v pp = 12.5 v x = 0 x = x + 1 0.1 ms program pulse address = n? verification of all bytes v dd = 4.5 to 5.5 v, v pp = v dd address = address + 1 x = 10? defective product yes fail pass no yes all pass pass remark g = start address n = last address of program chapter 26 pd78p4038 programming 648 user s manual u11316ej4v1ud figure 26-4 byte program mode timing d0 to d7 a0 to a16 v pp v pp v dd v dd v dd + 1.5 v dd v ih v il v ih v il v ih v il oe pgm ce program program verify data output data input cautions 1. ensure that v dd is applied before v pp , and cut after v pp . 2. ensure that v pp does not become +13.5 v or over including overshoot. 3. removing the device while +12.5 v is being applied to v pp may have an adverse affect on reliability. chapter 26 pd78p4038 programming 649 user? manual u11316ej4v1ud 26.3 prom reading procedure prom contents can be read onto the external data bus (d0 to d7) using the following procedure. (1) fix the reset pin low, and supply +5 v to the v pp pin. unused pins are handled as shown in 1.3.2 prom programming mode in 1.3 pin configuration (top view). (2) supply +5 v to the v dd and v pp pins. (3) input address of data to be read to pins a0 to a16. (4) read mode. (5) output data to pins d0 to d7. the timing for steps (2) to (5) above is shown in figure 26-5. figure 26-5 prom read timing address input a0 to a16 d0 to d7 hi-z hi-z ce (input) oe (input) data output 26.4 screening of one-time prom product because of its construction, the one-time prom product ( pd78p4038gc-8bt, 78p4038ygc-8bt, 78p4038gk-9eu, 78p4038ygk-9eu) cannot be fully tested by nec electronics before shipment. after the necessary data has been written, it is recommended that screening be carried out by performing prom verification after high-temperature storage under the following conditions. storage temperature storage time 125 c 24 hours 26.5 cautions (1) ensure that v dd is applied before v pp , and cut after v pp . (2) ensure that v pp does not become +13.5 v or over including overshoot. (3) removing the device while +12.5 v is being applied to v pp may have an adverse affect on reliability. 650 user? manual u11316ej4v1ud chapter 27 instruction operations 27.1 legend (1) operand identifiers and descriptions (1/2) identifier description r, r note 1 x(r0), a(r1), c(r2), b(r3), r4, r5, r6, r7, r8, r9, r10, r11, e(r12), d(r13), l(r14), h(r15) r1 note 1 x(r0), a(r1), c(r2), b(r3), r4, r5, r6, r7 r2 r8, r9, r10, r11, e(r12), d(r13), l(r14), h(r15) r3 v, u, t, w rp, rp note 2 ax(rp0), bc(rp1), rp2, rp3, vp(rp4), up(rp5), de(rp6), hl(rp7) rp1 note 2 ax(rp0), bc(rp1), rp2, rp3 rp2 vp(rp4), up(rp5), de(rp6), hl(rp7) rg, rg vvp(rg4), uup(rg5), tde(rg6), whl(rg7) sfr special function register symbol sfrp special function register symbol (register for which 16-bit operation is possible) post note 2 ax(rp0), bc(rp1), rp2, rp3, vp(rp4), up(rp5)/psw, de(rp6), hl(rp7) multiple descriptions are permissible. however, up is only used with push/pop instructions, and psw with pushu/popu instructions. mem [tde], [whl], [tde+], [whl+], [tde?, [whl?, [vvp], [uup]: register indirect addressing [tde+byte], [whl+byte], [sp+byte], [uup+byte], [vvp+byte]: based addressing imm24 [a], imm24 [b], imm24 [de], imm24 [hl]: indexed addressing [tde+a], [tde+b], [tde+c], [whl+a], [whl+b], [whl+c], [vvp+de], [vvp+hl]: based indexed addressing mem1 all mem except [whl+] and [whl? mem2 [tde], [whl] mem3 [ax], [bc], [rp2], [rp3], [vvp], [uup], [tde], [whl] notes 1. setting the rss bit to 1 enables r4 to r7 to be used as x, a, c, and b, but this function should only be used when using a 78k/iii series program. 2. setting the rss bit to 1 enables rp2 and rp3 to be used as ax and bc, but this function should only be used when using a 78k/iii series program. chapter 27 instruction operations 651 user? manual u11316ej4v1ud (1) operand identifiers and descriptions (2/2) identifier description saddr, saddr fd20h to ff1fh immediate data or label saddr1 fe00h to feffh immediate data or label saddr2 fd20h to fdffh, ff00h to ff1fh immediate data or label saddrp fd20h to ff1eh immediate data or label (16-bit operation) saddrp1 fe00h to feffh immediate data or label (16-bit operation) saddrp2 fd20h to fdffh, ff00h to ff1eh immediate data or label (16-bit operation) saddrg fd20h to fefdh immediate data or label (24-bit operation) saddrg1 fe00h to fefdh immediate data or label (24-bit operation) saddrg2 fd20h to fdffh immediate data or label (24-bit operation) addr24 0h to ffffffh immediate data or label addr20 0h to fffffh immediate data or label addr16 0h to ffffh immediate data or label addr11 800h to fffh immediate data or label addr8 0fe00h to 0feffh note immediate data or label addr5 40h to 7eh immediate data or label imm24 24-bit immediate data or label word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label n 3-bit immediate data locaddr 0h or 0fh note the addresses shown here apply when 0h is specified by the location instruction. when 0fh is specified by the location instruction, f0000h should be added to the address values shown. (2) operand column symbols symbol description + auto-increment auto-decrement # immediate data ! 16-bit absolute address !! 24-bit/20-bit absolute address $ 8-bit relative address $! 16-bit relative address / bit inversion [ ] indirect addressing [%] 24-bit indirect addressing chapter 27 instruction operations 652 user? manual u11316ej4v1ud (3) flag column symbols symbol description (blank) no change 0 cleared to 0 1 set to 1 set or cleared depending on result p p/v flag operates as parity flag v p/v flag operates as overflow flag r previously saved value is restored (4) operation column symbols symbol description jdisp8 signed two? complement data (8 bits) indicating relative address distance between start address of next instruction and branch address jdisp16 signed two? complement data (16 bits) indicating relative address distance between start address of next instruction and branch address pc hw pc bits 16 to 19 pc lw pc bits 0 to 15 (5) number of bytes of instruction that includes mem in operands mem mode register indirect addressing based indexed based indexed addressing addressing addressing number of bytes 1 2 note 352 note one-byte instruction only when [tde], [whl], [tde+], [tde-], [whl+], or [whl? is written as mem in an mov instruction. (6) number of bytes of instruction that includes saddr, saddrp, r or rp in operands for some instructions that include saddr, saddrp, r, or rp in their operands, two ?ytes?entries are given, separated by a slash (??. the entry that applies is shown in the table below. identifier left-hand ?ytes?figure right-hand ?ytes?figure saddr saddr2 saddr1 saddrp saddrp2 saddrp1 rr1 r2 rp rp1 rp2 (7) description of instructions that include mem in operands and string instructions operands tde, whl, vvp, and uup (24-bit registers) can also be written as de, hl, vp, and up respectively. however, they are still treated as tde, whl, vvp, and uup (24-bit registers) when written as de, hl, vp, and up. chapter 27 instruction operations 653 user? manual u11316ej4v1ud 27.2 list of operations (1) 8-bit data transfer instruction: mov mnemonic operands bytes operation flags s z ac p/v cy mov r, #byte 2/3 r byte saddr, #byte 3/4 (saddr) byte sfr, #byte 3 sfr byte !addr16, #byte 5 (saddr16) byte !!addr24, #byte 6 (addr24) byte r, r 2/3 r r a, r 1/2 a r a, saddr2 2 a (saddr2) r, saddr 3 r (saddr) saddr2, a 2 (saddr2) a saddr, r 3 (saddr) r a, sfr 2 a sfr r, sfr 3 r sfr sfr, a 2 sfr a sfr, r 3 sfr r saddr, saddr 4 (saddr) (saddr? r, !addr16 4 r (addr16) !addr16, r 4 (addr16) r r, !!addr24 5 r (addr24) !!addr24, r 5 (addr24) r a, [saddrp] 2/3 a ((saddrp)) a, [%saddrg] 3/4 a ((saddrg)) a, mem 1-5 a (mem) [saddrp], a 2/3 ((saddrp)) a [%saddrg], a 3/4 ((saddrg)) a mem, a 1-5 (mem) a pswl, #byte 3 psw l byte pswh, #byte 3 psw h byte pswl, a 2 psw l a pswh, a 2 psw h a a, pswl 2 a psw l a, pswh 2 a psw h r3, #byte 3 r3 byte a, r3 2 a r3 r3, a 2 r3 a chapter 27 instruction operations 654 user? manual u11316ej4v1ud (2) 16-bit data transfer instruction: movw mnemonic operands bytes operation flags s z ac p/v cy movw rp, #word 3 rp word saddrp, #word 4/5 (saddrp) word sfrp, #word 4 sfrp word !addr16, #word 6 (addr16) word !!addr24, #word 7 (addr24) word rp, rp 2 rp rp ax, saddrp2 2 ax (saddrp2) rp, saddrp 3 rp (saddrp) saddrp2, ax 2 (saddrp2) ax saddrp, rp 3 (saddrp) rp ax, sfrp 2 ax sfrp rp, sfrp 3 rp sfrp sfrp, ax 2 sfrp ax sfrp, rp 3 sfrp rp saddrp, saddrp 4 (saddrp) (saddrp? rp, !addr16 4 rp (addr16) !addr16, rp 4 (addr16) rp rp, !!addr24 5 rp (addr24) !!addr24, rp 5 (addr24) rp ax, [saddrp] 3/4 ax ((saddrp)) ax, [%saddrg] 3/4 ax ((saddrg)) ax, mem 2-5 ax (mem) [saddrp], ax 3/4 ((saddrp)) ax [%saddrg], ax 3/4 ((saddrg)) ax mem, ax 2-5 (mem) ax chapter 27 instruction operations 655 user? manual u11316ej4v1ud (3) 24-bit data transfer instruction: movg mnemonic operands bytes operation flags s z ac p/v cy movg rg, #imm24 5 rg imm24 rg, rg 2 rg rg rg, !!addr24 5 rg (addr24) !!addr24, rg 5 (addr24) rg rg, saddrg 3 rg (saddrg) saddrg, rg 3 (saddrg) rg whl, [%saddrg] 3/4 whl ((saddrg)) [%saddrg], whl 3/4 ((saddrg)) whl whl, mem1 2-5 whl (mem1) mem1, whl 2-5 (mem1) whl (4) 8-bit data exchange instruction: xch mnemonic operands bytes operation flags s z ac p/v cy xch r, r 2/3 r ? r a, r 1/2 a ? r a, saddr2 2 a ? (saddr2) r, saddr 3 r ? (saddr) r, sfr 3 r ? sfr saddr, saddr 4 (saddr) ? (saddr? r, !addr16 4 r ? (addr16) r, !!addr24 5 r ? (addr24) a, [saddrp] 2/3 a ? ((saddrp)) a, [%saddrg] 3/4 a ? ((saddrg)) a, mem 2-5 a ? (mem) chapter 27 instruction operations 656 user? manual u11316ej4v1ud (5) 16-bit data exchange instruction: xchw mnemonic operands bytes operation flags s z ac p/v cy xchw rp, rp 2 rp ? rp ax, saddrp2 2 ax ? (saddrp2) rp, saddrp 3 rp ? (saddrp) rp, sfrp 3 rp ? sfrp ax, [saddrp] 3/4 ax ? ((saddrp)) ax, [%saddrg] 3/4 ax ? ((saddrg)) ax, !addr16 4 ax ? (addr16) ax, !!addr24 5 ax ? (addr24) saddrp, saddrp 4 (saddrp) ? (saddrp? ax, mem 2-5 ax ? (mem) (6) 8-bit operation instructions: add, addc, sub, subc, cmp, and, or, xor mnemonic operands bytes operation flags s z ac p/v cy add a, #byte 2 a, cy a + byte v r, #byte 3 r, cy r + byte v saddr, #byte 3/4 (saddr), cy (saddr) + byte v sfr, #byte 4 sfr, cy sfr + byte v r, r 2/3 r, cy r + r v a, saddr2 2 a, cy a + (saddr2) v r, saddr 3 r, cy r + (saddr) v saddr, r 3 (saddr), cy (saddr) + r v r, sfr 3 r, cy r + sfr v sfr, r 3 sfr, cy sfr + r v saddr, saddr 4 (saddr), cy (saddr) + (saddr? v a, [saddrp] 3/4 a, cy a + ((saddrp)) v a, [%saddrg] 3/4 a, cy a + ((saddrg)) v [saddrp], a 3/4 ((saddrp)), cy ((saddrp)) + a v [%saddrg], a 3/4 ((saddrg)), cy ((saddrg)) + a v a, !addr16 4 a, cy a + (addr16) v a, !!addr24 5 a, cy a + (addr24) v !addr16, a 4 (addr16), cy (addr16) + a v !!addr24, a 5 (addr24), cy (addr24) + a v a, mem 2-5 a, cy a + (mem) v mem, a 2-5 (mem), cy (mem) + a v chapter 27 instruction operations 657 user? manual u11316ej4v1ud mnemonic operands bytes operation flags s z ac p/v cy addc a, #byte 2 a, cy a + byte + cy v r, #byte 3 r, cy r + byte + cy v saddr, #byte 3/4 (saddr), cy (saddr) + byte + cy v sfr, #byte 4 sfr, cy sfr + byte + cy v r, r 2/3 r, cy r + r?+ cy v a, saddr2 2 a, cy a + (saddr2) + cy v r, saddr 3 r, cy r + (saddr) + cy v saddr, r 3 (saddr), cy (saddr) + r + cy v r, sfr 3 r, cy r + sfr + cy v sfr, r 3 sfr, cy sfr + r + cy v saddr, saddr 4 (saddr), cy (saddr) + (saddr? + cy v a, [saddrp] 3/4 a, cy a + ((saddrp)) + cy v a, [%saddrg] 3/4 a, cy a + ((saddrg)) + cy v [saddrp], a 3/4 ((saddrp)), cy ((saddrp)) + a + cy v [%saddrg], a 3/4 ((saddrg)), cy ((saddrg)) + a + cy v a, !addr16 4 a, cy a + (addr16) + cy v a, !!addr24 5 a, cy a + (addr24) + cy v !addr16, a 4 (addr16), cy (addr16) + a + cy v !!addr24, a 5 (addr24), cy (addr24) + a + cy v a, mem 2-5 a, cy a + (mem) + cy v mem, a 2-5 (mem), cy (mem) + a + cy v chapter 27 instruction operations 658 user? manual u11316ej4v1ud mnemonic operands bytes operation flags s z ac p/v cy sub a, #byte 2 a, cy a ?byte v r, #byte 3 r, cy r ?byte v saddr, #byte 3/4 (saddr), cy (saddr) ?byte v sfr, #byte 4 sfr, cy sfr ?byte v r, r 2/3 r, cy r ?r v a, saddr2 2 a, cy a (saddr2) v r, saddr 3 r, cy r ?(saddr) v saddr, r 3 (saddr), cy (saddr) r v r, sfr 3 r, cy r ?sfr v sfr, r 3 sfr, cy sfr ?r v saddr, saddr 4 (saddr), cy (saddr) ?(saddr? v a, [saddrp] 3/4 a, cy a ?((saddrp)) v a, [%saddrg] 3/4 a, cy a ?((saddrg)) v [saddrp], a 3/4 ((saddrp)), cy ((saddrp)) a v [%saddrg], a 3/4 ((saddrg)), cy ((saddrg)) a v a, !addr16 4 a, cy a ?(addr16) v a, !!addr24 5 a, cy a ?(addr24) v !addr16, a 4 (addr16), cy (addr16) ?a v !!addr24, a 5 (addr24), cy (addr24) ?a v a, mem 2-5 a, cy a ?(mem) v mem, a 2-5 (mem), cy (mem) a v chapter 27 instruction operations 659 user? manual u11316ej4v1ud mnemonic operands bytes operation flags s z ac p/v cy subc a, #byte 2 a, cy a ?byte ?cy v r, #byte 3 r, cy r ?byte ?cy v saddr, #byte 3/4 (saddr), cy (saddr) ?byte ?cy v sfr, #byte 4 sfr, cy sfr ?byte ?cy v r, r 2/3 r, cy r ?r??cy v a, saddr2 2 a, cy a (saddr2) ?cy v r, saddr 3 r, cy r ?(saddr) ?cy v saddr, r 3 (saddr), cy (saddr) ?r ?cy v r, sfr 3 r, cy r sfr ?cy v sfr, r 3 sfr, cy sfr ?r ?cy v saddr, saddr 4 (saddr), cy (saddr) ?(saddr? ?cy v a, [saddrp] 3/4 a, cy a ?((saddrp)) ?cy v a, [%saddrg] 3/4 a, cy a ?((saddrg)) ?cy v [saddrp], a 3/4 ((saddrp)), cy ((saddrp)) ?a ?cy v [%saddrg], a 3/4 ((saddrg)), cy ((saddrg)) ?a ?cy v a, !addr16 4 a, cy a ?(addr16) ?cy v a, !!addr24 5 a, cy a ?(addr24) ?cy v !addr16, a 4 (addr16), cy (addr16) ?a ?cy v !!addr24, a 5 (addr24), cy (addr24) ?a ?cy v a, mem 2-5 a, cy a ?(mem) ?cy v mem, a 2-5 (mem), cy (mem) a ?cy v chapter 27 instruction operations 660 user? manual u11316ej4v1ud mnemonic operands bytes operation flags s z ac p/v cy cmp a, #byte 2 a ?byte v r, #byte 3 r ?byte v saddr, #byte 3/4 (saddr) ?byte v sfr, #byte 4 sfr ?byte v r, r 2/3 r r v a, saddr2 2 a (saddr2) v r, saddr 3 r (saddr) v saddr, r 3 (saddr) ?r v r, sfr 3 r sfr v sfr, r 3 sfr ?r v saddr, saddr 4 (saddr) ?(saddr? v a, [saddrp] 3/4 a ?((saddrp)) v a, [%saddrg] 3/4 a ?((saddrg)) v [saddrp], a 3/4 ((saddrp)) ?a v [%saddrg], a 3/4 ((saddrg)) ?a v a, !addr16 4 a ?(addr16) v a, !!addr24 5 a ?(addr24) v !addr16, a 4 (addr16) ?a v !!addr24, a 5 (addr24) ?a v a, mem 2-5 a ?(mem) v mem, a 2-5 (mem) a v chapter 27 instruction operations 661 user? manual u11316ej4v1ud mnemonic operands bytes operation flags s z ac p/v cy and a, #byte 2 a a byte p r, #byte 3 r r byte p saddr, #byte 3/4 (saddr) (saddr) byte p sfr, #byte 4 sfr sfr byte p r, r 2/3 r r r p a, saddr2 2 a a (saddr2) p r, saddr 3 r r (saddr) p saddr, r 3 (saddr) (saddr) r p r, sfr 3 r r sfr p sfr, r 3 sfr sfr r p saddr, saddr 4 (saddr) (saddr) (saddr? p a, [saddrp] 3/4 a a ((saddrp)) p a, [%saddrg] 3/4 a a ((saddrg)) p [saddrp], a 3/4 ((saddrp)) ((saddrp)) a p [%saddrg], a 3/4 ((saddrg)) ((saddrg)) a p a, !addr16 4 a a (addr16) p a, !!addr24 5 a a (addr24) p !addr16, a 4 (addr16) (addr16) a p !!addr24, a 5 (addr24) (addr24) a p a, mem 2-5 a a (mem) p mem, a 2-5 (mem) (mem) a p chapter 27 instruction operations 662 user? manual u11316ej4v1ud mnemonic operands bytes operation flags s z ac p/v cy or a, #byte 2 a a byte p r, #byte 3 r r byte p saddr, #byte 3/4 (saddr) (saddr) byte p sfr, #byte 4 sfr sfr byte p r, r 2/3 r r r p a, saddr2 2 a a (saddr2) p r, saddr 3 r r (saddr) p saddr, r 3 (saddr) (saddr) r p r, sfr 3 r r sfr p sfr, r 3 sfr sfr r p saddr, saddr 4 (saddr) (saddr) (saddr? p a, [saddrp] 3/4 a a ((saddrp)) p a, [%saddrg] 3/4 a a ((saddrg)) p [saddrp], a 3/4 ((saddrp)) ((saddrp)) a p [%saddrg], a 3/4 ((saddrg)) ((saddrg)) a p a, !addr16 4 a a (addr16) p a, !!addr24 5 a a (addr24) p !addr16, a 4 (addr16) (addr16) a p !!addr24, a 5 (addr24) (addr24) a p a, mem 2-5 a a (mem) p mem, a 2-5 (mem) (mem) a p chapter 27 instruction operations 663 user? manual u11316ej4v1ud mnemonic operands bytes operation flags s z ac p/v cy xor a, #byte 2 a a byte p r, #byte 3 r r byte p saddr, #byte 3/4 (saddr) (saddr) byte p sfr, #byte 4 sfr sfr byte p r, r 2/3 r r r p a, saddr2 2 a a (saddr2) p r, saddr 3 r r (saddr) p saddr, r 3 (saddr) (saddr) r p r, sfr 3 r r sfr p sfr, r 3 sfr sfr r p saddr, saddr 4 (saddr) (saddr) (saddr? p a, [saddrp] 3/4 a a ((saddrp)) p a, [%saddrg] 3/4 a a ((saddrg)) p [saddrp], a 3/4 ((saddrp)) ((saddrp)) a p [%saddrg], a 3/4 ((saddrg)) ((saddrg)) a p a, !addr16 4 a a (addr16) p a, !!addr24 5 a a (addr24) p !addr16, a 4 (addr16) (addr16) a p !!addr24, a 5 (addr24) (addr24) a p a, mem 2-5 a a (mem) p mem, a 2-5 (mem) (mem) a p chapter 27 instruction operations 664 user? manual u11316ej4v1ud (7) 16-bit operation instructions: addw, subw, cmpw mnemonic operands bytes operation flags s z ac p/v cy addw ax, #word 3 ax, cy ax + word v rp, #word 4 rp, cy rp + word v rp, rp 2 rp, cy rp + rp v ax, saddrp2 2 ax, cy ax + (saddrp2) v rp, saddrp 3 rp, cy rp + (saddrp) v saddrp, rp 3 (saddrp), cy (saddrp) + rp v rp, sfrp 3 rp, cy rp + sfrp v sfrp, rp 3 sfrp, cy sfrp + rp v saddrp, #word 4/5 (saddrp), cy (saddrp) + word v sfrp, #word 5 sfrp, cy sfrp + word v saddrp, saddrp 4 (saddrp), cy (saddrp) + (saddrp? v subw ax, #word 3 ax, cy ax ?word v rp, #word 4 rp, cy rp ?word v rp, rp 2 rp, cy rp ?rp v ax, saddrp2 2 ax, cy ax ?(saddrp2) v rp, saddrp 3 rp, cy rp ?(saddrp) v saddrp, rp 3 (saddrp), cy (saddrp) ?rp v rp, sfrp 3 rp, cy rp ?sfrp v sfrp, rp 3 sfrp, cy sfrp ?rp v saddrp, #word 4/5 (saddrp), cy (saddrp) ?word v sfrp, #word 5 sfrp, cy sfrp ?word v saddrp, saddrp 4 (saddrp), cy (saddrp) (saddrp? v cmpw ax, #word 3 ax ?word v rp, #word 4 rp ?word v rp, rp 2 rp rp v ax, saddrp2 2 ax ?(saddrp2) v rp, saddrp 3 rp (saddrp) v saddrp, rp 3 (saddrp) rp v rp, sfrp 3 rp sfrp v sfrp, rp 3 sfrp ?rp v saddrp, #word 4/5 (saddrp) word v sfrp, #word 5 sfrp ?word v saddrp, saddrp 4 (saddrp) (saddrp? v chapter 27 instruction operations 665 user? manual u11316ej4v1ud (8) 24-bit operation instructions: addg, subg mnemonic operands bytes operation flags s z ac p/v cy addg rg, rg 2 rg, cy rg + rg v rg, # imm24 5 rg, cy rg + # imm24 v whl, saddrg 3 whl, cy whl + (saddrg) v subg rg, rg 2 rg, cy rg ?rg v rg, # imm24 5 rg, cy rg imm24 v whl, saddrg 3 whl, cy whl ?(saddrg) v (9) multiplication instructions: mulu, muluw, mulw, divuw, divux mnemonic operands bytes operation flags s z ac p/v cy mulu r 2/3 ax a r muluw rp 2 ax (upper half), rp (lower half) ax rp mulw rp 2 ax (upper half), rp (lower half) ax rp divuw r 2/3 ax (quotient), r (remainder) ax r note 1 divux rp 2 axde (quotient), rp (remainder) axde rp note 2 notes 1. when r = 0, r x, ax ffffh 2. when rp = 0, pr de, axde ffffffffh (10) special operation instructions: macw, macsw, sacw mnemonic operands bytes operation flags s z ac p/v cy macw byte 3 axde (b) (c) + axde, b b + 2, v c c + 2, byte byte ?1 end if (byte = 0 or p/v = 1) macsw byte 3 axde (b) (c) + axde, b b + 2, v c c + 2, byte byte ?1 if byte = 0 then end if p/v = 1 then if overflow axde 7fffffffh, end if underflow axde 80000000h, end sacw [tde + ], [whl + ] 4 ax |(tde) ?(whl)| + ax, v tde tde + 2, whl whl + 2 c c ?1 end if (c = 0 or cy = 1) chapter 27 instruction operations 666 user? manual u11316ej4v1ud (11) increment/decrement instructions: inc, dec, incw, decw, incg, decg mnemonic operands bytes operation flags s z ac p/v cy inc r 1/2 r r + 1 v saddr 2/3 (saddr) (saddr) + 1 v dec r 1/2 r r ? v saddr 2/3 (saddr) (saddr) ?1 v incw rp 2/1 rp rp + 1 saddrp 3/4 (saddrp) (saddrp) + 1 decw rp 2/1 rp rp ?1 saddrp 3/4 (saddrp) (saddrp) ?1 incg rg 2 rg rg + 1 decg rg 2 rg rg ?1 (12) adjustment instructions: adjba, adjbs, cvtbw mnemonic operands bytes operation flags s z ac p/v cy adjba 2 decimal adjust accumulator after addition p adjbs 2 decimal adjust accumulator after subtract p cvtbw 1 x a, a 00h if a 7 = 0 x a, a ffh if a 7 = 1 chapter 27 instruction operations 667 user? manual u11316ej4v1ud (13) shift/rotate instructions: ror, rol, rorc, rolc, shr, shl, shrw, shlw, ror4, rol4 mnemonic operands bytes operation flags s z ac p/v cy ror r, n 2/3 (cy, r7 r0 , rm ?1 rm ) n times n = 0 to 7 p rol r, n 2/3 (cy, r0 r7 , rm + 1 rm ) n times n = 0 to 7 p rorc r, n 2/3 (cy r0 , r7 cy, rm ?1 rm ) n times n = 0 to 7 p rolc r, n 2/3 (cy r7 , r0 cy, rm + 1 rm ) n times n = 0 to 7 p shr r, n 2/3 (cy r0 , r7 0, rm ?1 rm ) n times n = 0 to 7 0p shl r, n 2/3 (cy r7 , r0 0, rm + 1 rm ) n times n = 0 to 7 0p shrw rp, n 2 (cy rp0 , rp15 0, rpm ?1 rpm) n times 0p n = 0 to 7 shlw rp, n 2 (cy rp15 , rp0 0, rpm + 1 rpm) n times 0p n = 0 to 7 ror4 mem3 2 a 3 ?0 (mem3) 3 ?0 , (mem3) 7 ?4 a 3 ?0 , (mem3) 3 ?0 (mem3) 7 ?4 rol4 mem3 2 a 3 ?0 (mem3) 7 ?4 , (mem3) 3 ?0 a 3 ?0 , (mem3) 7 ?4 (mem3) 3 ?0 (14) bit manipulation instructions: mov1, and1, or1, xor1, not1, set1, clr1 mnemonic operands bytes operation flags s z ac p/v cy mov1 cy, saddr. bit 3/4 cy (saddr. bit) cy, sfr. bit 3 cy sfr. bit cy, x. bit 2 cy x. bit cy, a. bit 2 cy a. bit cy, pswl. bit 2 cy pswl. bit cy, pswh. bit 2 cy pswh. bit cy, !addr16. bit 5 cy !addr16.bit cy, !!addr24. bit 2 cy !!addr24. bit cy, mem2. bit 2 cy mem2. bit saddr. bit, cy 3/4 (saddr. bit) cy sfr. bit, cy 3 sfr. bit cy x. bit, cy 2 x.bit cy a. bit, cy 2 a. bit cy pswl. bit, cy 2 psw l . bit cy pswh. bit, cy 2 psw h . bit cy !addr16. bit, cy 5 !addr16.bit cy !!addr24.bit, cy 6 !!addr24.bit cy mem2. bit, cy 2 mem2. bit cy chapter 27 instruction operations 668 user? manual u11316ej4v1ud mnemonic operands bytes operation flags s z ac p/v cy and1 cy, saddr. bit 3/4 cy cy (saddr. bit) cy, /saddr. bit 3/4 cy cy (saddr. bit) cy, sfr. bit 3 cy cy sfr. bit cy, /sfr. bit 3 cy cy sfr. bit cy, x. bit 2 cy cy x. bit cy, /x. bit 2 cy cy x. bit cy, a. bit 2 cy cy a. bit cy, /a. bit 2 cy cy a. bit cy, pswl. bit 2 cy cy psw l . bit cy, /pswl. bit 2 cy cy psw l . bit cy, pswh. bit 2 cy cy psw h . bit cy, /pswh. bit 2 cy cy psw h . bit cy, !addr16. bit 5 cy cy !addr16. bit cy, /!addr16. bit 5 cy cy !addr16. bit cy, !!addr24. bit 2 cy cy !!addr24. bit cy, /!!addr24. bit 6 cy cy !!addr24. bit cy, mem2. bit 2 cy cy mem2. bit cy, /mem2. bit 2 cy cy mem2. bit or1 cy, saddr. bit 3/4 cy cy (saddr. bit) cy, /saddr. bit 3/4 cy cy (saddr. bit) cy, sfr. bit 3 cy cy sfr. bit cy, /sfr. bit 3 cy cy sfr. bit cy, x. bit 2 cy cy x. bit cy, /x. bit 2 cy cy x. bit cy, a. bit 2 cy cy a. bit cy, /a. bit 2 cy cy a. bit cy, pswl. bit 2 cy cy psw l . bit cy, /pswl. bit 2 cy cy psw l . bit cy, pswh. bit 2 cy cy psw h . bit cy, /pswh. bit 2 cy cy psw h . bit cy, !addr16. bit 5 cy cy !addr16. bit cy, /!addr16. bit 5 cy cy !addr16. bit cy, !!addr24. bit 2 cy cy !!addr24. bit cy, /!!addr24. bit 6 cy cy !!addr24. bit cy, mem2. bit 2 cy cy mem2. bit cy, /mem2. bit 2 cy cy mem2. bit chapter 27 instruction operations 669 user? manual u11316ej4v1ud mnemonic operands bytes operation flags s z ac p/v cy xor1 cy, saddr. bit 3/4 cy cy (saddr. bit) cy, sfr. bit 3 cy cy sfr. bit cy, x. bit 2 cy cy x. bit cy, a. bit 2 cy cy a. bit cy, pswl. bit 2 cy cy pswl. bit cy, pswh. bit 2 cy cy pswh. bit cy, !addr16. bit 5 cy cy !addr16. bit cy, !!addr24. bit 2 cy cy !!addr24. bit cy, mem2. bit 2 cy cy mem2. bit not1 saddr. bit 3/4 (saddr. bit) (saddr. bit) sfr. bit 3 sfr. bit sfr. bit x. bit 2 x. bit x. bit a. bit 2 a. bit a. bit pswl. bit 2 pswl. bit psw l . bit pswh. bit 2 pswh. bit psw h . bit !addr16. bit 5 !addr16. bit !addr16. bit !!addr24. bit 2 !!addr24. bit !!addr24. bit mem2. bit 2 mem2. bit mem2. bit cy 1 cy cy set1 saddr. bit 2/3 (saddr. bit) 1 sfr. bit 3 sfr. bit 1 x. bit 2 x. bit 1 a. bit 2 a. bit 1 pswl. bit 2 pswl. bit 1 pswh. bit 2 pswh. bit 1 !addr16. bit 5 !addr16. bit 1 !!addr24. bit 2 !!addr24. bit 1 mem2. bit 2 mem2. bit 1 cy 1 cy 11 clr1 saddr. bit 2/3 (saddr. bit) 0 sfr. bit 3 sfr. bit 0 x. bit 2 x. bit 0 a. bit 2 a. bit 0 pswl. bit 2 pswl. bit 0 pswh. bit 2 pswh. bit 0 !addr16. bit 5 !addr16. bit 0 !!addr24. bit 2 !!addr24. bit 0 mem2. bit 2 mem2. bit 0 cy 1 cy 00 chapter 27 instruction operations 670 user? manual u11316ej4v1ud (15) stack manipulation instructions: push, pushu, pop, popu, movg, addwg, subwg, incg, decg mnemonic operands bytes operation flags s z ac p/v cy push psw 1 (sp ?2) psw, sp sp ?2 sfrp 3 (sp ?2) sfrp, sp sp ?2 sfr 3 (sp ?1) sfr, sp sp ?1 post 2 {(sp ?2) post, sp sp ?2} m times note rg 2 (sp ?3) rg, sp sp ?3 pushu post 2 {(uup ?2) post, uup uup ?2} m times note pop psw 1 psw (sp), sp sp + 2 rrrrr sfrp 3 sfrp (sp), sp sp + 2 sfr 3 sfr (sp), sp sp + 1 post 2 {post (sp), sp sp + 2} m times note rg 2 rg (sp), sp sp + 3 popu post 2 {post (uup), uup uup + 2} m times note movg sp, # imm24 5 sp imm24 sp, whl 2 sp whl whl, sp 2 whl sp addwg sp, #word 4 sp sp + word subwg sp, #word 4 sp sp ?word incg sp 2 sp sp + 1 decg sp 2 sp sp ?1 note m = number of registers specified by ?ost chapter 27 instruction operations 671 user? manual u11316ej4v1ud (16) call/return instructions: call, callf, callt, brk, brkcs, ret, reti, retb, retcs, retcsb mnemonic operands bytes operation flags s z ac p/v cy call !addr16 3 (sp ?3) (pc + 3), sp sp ?3, pc hw 0, pc lw addr16 !!addr20 4 (sp ?3) (pc + 4), sp sp ?3, pc addr20 rp 2 (sp ?3) (pc + 2), sp sp ?3, pc hw 0, pc lw rp rg 2 (sp ?3) (pc + 2), sp sp ?3, pc rg [rp] 2 (sp ?3) (pc + 2), sp sp ?3, pc hw 0, pc lw (rp) [rg] 2 (sp ?3) (pc + 2), sp sp ?3, pc (rg) $!addr20 3 (sp ?3) (pc + 3), sp sp ?3, pc pc + 3 + jdisp16 callf !addr11 2 (sp ?3) (pc + 2), sp sp ?3, pc 19 ?12 0, pc11 1, pc 10 ?0 addr11 callt [addr5] 1 (sp ?3) (pc + 1), sp sp ?3, pc hw 0, pc lw (addr5) brk 1 (sp ?2) psw, (sp ?1) 0 ?3 (pc + 1) hw , (sp ?4) (pc + 1) lw , sp sp ?4 pc hw 0, pc lw (003eh) brkcs rbn 2 pc lw rp2, rp3 psw, rbs2 ?0 n, rss 0, ie 0, rp3 8 ?11 pc hw , pc hw 0 ret 1 pc (sp), sp sp + 3 ret1 1 pc lw (sp), pc hw (sp + 3) 0 ?3 , rrrrr psw (sp + 2), sp sp + 4 clears to 0 flag with highest priority of flags of ispr that are set (to 1) retb 1 pc lw (sp), pc hw (sp + 3) 0 ?3 , rrrrr psw (sp + 2), sp sp + 4 retcs !addr16 3 psw rp3, pc lw rp2, rp2 addr16, rrrrr pc hw rp3 8 ?11 clears to 0 flag with highest priority of flags of ispr that are set (to 1) retcsb !addr16 4 psw rp3, pc lw rp2, rp2 addr16, rrrrr pc hw rp3 8 ?11 chapter 27 instruction operations 672 user? manual u11316ej4v1ud (17) unconditional branch instruction: br mnemonic operands bytes operation flags s z ac p/v cy br !addr16 3 pc hw 0, pc lw addr16 !!addr20 4 pc addr20 rp 2 pc hw 0, pc lw rp rg 2 pc rg [rp] 2 pc hw 0, pc lw (rp) [rg] 2 pc (rg) $addr20 2 pc pc + 2 + jdisp8 $!addr20 3 pc pc + 3 + jdisp16 chapter 27 instruction operations 673 user? manual u11316ej4v1ud (18) conditional branch instructions: bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz mnemonic operands bytes operation flags s z ac p/v cy bnz $addr20 2 pc pc + 2 + jdisp8 if z = 0 bne bz $addr20 2 pc pc + 2 + jdisp8 if z = 1 be bnc $addr20 2 pc pc + 2 + jdisp8 if cy = 0 bnl bc $addr20 2 pc pc + 2 + jdisp8 if cy = 1 bl bnv $addr20 2 pc pc + 2 + jdisp8 if p/v = 0 bpo bv $addr20 2 pc pc + 2 + jdisp8 if p/v = 1 bpe bp $addr20 2 pc pc + 2 + jdisp8 if s = 0 bn $addr20 2 pc pc + 2 + jdisp8 if s = 1 blt $addr20 3 pc pc + 3 + jdisp8 if p/v s = 1 bge $addr20 3 pc pc + 3 + jdisp8 if p/v s = 0 ble $addr20 3 pc pc + 3 + jdisp8 if (p/v s) z = 1 bgt $addr20 3 pc pc + 3 + jdisp8 if (p/v s) z = 0 bnh $addr20 3 pc pc + 3 + jdisp8 if z cy = 1 bh $addr20 3 pc pc + 3 + jdisp8 if z cy = 0 bf saddr. bit, $addr20 4/5 pc pc + 4 note + jdisp8 if (saddr. bit) = 0 sfr. bit, $addr20 4 pc pc + 4 + jdisp8 if sfr. bit = 0 x. bit, $addr20 3 pc pc + 3 + jdisp8 if x. bit = 0 a. bit, $addr20 3 pc pc + 3 + jdisp8 if a. bit = 0 pswl. bit, $addr20 3 pc pc + 3 + jdisp8 if pswl. bit = 0 pswh. bit, $addr20 3 pc pc + 3 + jdisp8 if pswh. bit = 0 !addr16. bit, $addr20 6 pc pc + 3 + jdisp8 if !addr16. bit = 0 !!addr24. bit, $addr20 3 pc pc + 3 + jdisp8 if !!addr24. bit = 0 mem2. bit, $addr20 3 pc pc + 3 + jdisp8 if mem2. bit = 0 note when the number of bytes is 4. when 5, the operation is: pc pc + 5 + jdisp8. chapter 27 instruction operations 674 user? manual u11316ej4v1ud mnemonic operands bytes operation flags s z ac p/v cy bt saddr. bit, $addr20 3/4 pc pc + 3 note 1 + jdisp8 if (saddr. bit) = 1 sfr. bit, $addr20 4 pc pc + 4 + jdisp8 if sfr. bit = 1 x. bit, $addr20 3 pc pc + 3 + jdisp8 if x. bit = 1 a. bit, $addr20 3 pc pc + 3 + jdisp8 if a. bit = 1 pswl. bit, $addr20 3 pc pc + 3 + jdisp8 if psw l . bit = 1 pswh. bit, $addr20 3 pc pc + 3 + jdisp8 if psw h . bit = 1 !addr16. bit, $addr20 6 pc pc + 3 + jdisp8 if !addr16. bit = 1 !!addr24. bit, $addr20 3 pc pc + 3 + jdisp8 if !!addr24. bit = 1 mem2. bit, $addr20 3 pc pc + 3 + jdisp8 if mem2. bit = 1 btclr saddr. bit, $addr20 4/5 {pc pc + 4 note 2 + jdisp8, (saddr. bit) 0} if (saddr. bit) = 1 sfr. bit, $addr20 4 {pc pc + 4 + jdisp8, sfr. bit 0} if sfr. bit = 1 x. bit, $addr20 3 {pc pc + 3 + jdisp8, x. bit 0} if x. bit = 1 a. bit, $addr20 3 {pc pc + 3 + jdisp8, a. bit 0} if a. bit = 1 pswl. bit, $addr20 3 {pc pc + 3 + jdisp8, psw l . bit 0} if psw l . bit = 1 pswh. bit, $addr20 3 {pc pc + 3 + jdisp8, psw h . bit 0} if psw h . bit = 1 !addr16. bit, $addr20 6 {pc pc + 3 + jdisp8, !addr16. bit 0} if !addr16. bit = 1 !!addr24. bit, $addr20 3 {pc pc + 3 + jdisp8, !!addr24. bit 0} if !!addr24. bit = 1 mem2. bit, $addr20 3 {pc pc + 3 + jdisp8, mem2. bit 0} if mem2. bit = 1 notes 1. when the number of bytes is 3. when 4, the operation is: pc pc + 4 + jdisp8. 2. when the number of bytes is 4. when 5, the operation is: pc pc + 5 + jdisp8. chapter 27 instruction operations 675 user? manual u11316ej4v1ud mnemonic operands bytes operation flags s z ac p/v cy bfset saddr. bit, $addr20 4/5 {pc pc + 4 note 1 + jdisp8, (saddr. bit) 1} if (saddr. bit) = 0 sfr. bit, $addr20 4 {pc pc + 4 + jdisp8, sfr. bit 1} if sfr. bit = 0 x. bit, $addr20 3 {pc pc + 3 + jdisp8, x. bit 1} if x. bit = 0 a. bit, $addr20 3 {pc pc + 3 + jdisp8, a. bit 1} if a. bit = 0 pswl. bit, $addr20 3 {pc pc + 3 + jdisp8, psw l . bit 1} if psw l . bit = 0 pswh. bit, $addr20 3 {pc pc + 3 + jdisp8, psw h . bit 1} if psw h . bit = 0 !addr16. bit, $addr20 6 {pc pc + 3 + jdisp8, !addr16. bit 1} if !addr16. bit = 0 !!addr24. bit, $addr20 3 {pc pc + 3 + jdisp8, !!addr24. bit 1} if !!addr24. bit = 0 mem2. bit, $addr20 3 {pc pc + 3 + jdisp8, mem2. bit 1} if mem2. bit = 0 dbnz b, $addr20 2 b b ?1, pc pc + 2 + jdisp8 if b 0 c, $addr20 2 c c ?1, pc pc + 2 + jdisp8 if c 0 $addr, $addr20 3/4 (saddr) (saddr) ?1, pc pc + 3 note 2 = jdisp8 if (saddr) 0 notes 1. when the number of bytes is 4. when 5, the operation is: pc pc + 5 + jdisp8. 2. when the number of bytes is 3. when 4, the operation is: pc pc + 4 + jdisp8. (19) cpu control instructions: mov, location, sel, swrs, nop, ei, di mnemonic operands bytes operation flags s z ac p/v cy mov stbc, #byte 4 stbc byte wdm, #byte 4 wdm byte location locaddr 4 sfr, internal data area location address upper word specification sel rbn 2 rss 0, rbs2 ?0 n rbn, alt 2 rss 1, rbs2 ?0 n swrs 2 rss rss nop 1 no operaton ei 1 ie 1 (enable interrupt) di 1 ie 0 (disable interrupt) chapter 27 instruction operations 676 user? manual u11316ej4v1ud (20) special instructions: chkl, chkla mnemonic operands bytes operation flags s z ac p/v cy chkl sfr 3 (pin level) (output latch) p chkla sfr 3 a (pin level) (output latch) p (21) string instructions: movtblw, movm, xchm, movbk, xchbk, cmpme, cmpmne, cmpmc, cmpmnc, cmpbke, cmpbkne, cmpbkc, cmpbknc mnemonic operands bytes operation flags s z ac p/v cy movtblw !addr8, byte 4 (addr8 + 2) (addr8), byte byte ?1, addr8 addr8 ?2 end if byte = 0 movw [tde + ], a 2 (tde) a, tde tde + 1, c c ?1 end if c = 0 [tde ?], a 2 (tde) a, tde tde ?1, c c ?1 end if c = 0 xchm [tde + ], a 2 (tde) ? a, tde tde + 1, c c ?1 end if c = 0 [tde ?], a 2 (tde) ? a, tde tde ?1, c c ?1 end if c = 0 movbk [tde + ], [whl +] 2 (tde) (whl), tde tde + 1, whl whl + 1, c c ?1 end if c = 0 [tde ?], [whl ? 2 (tde) (whl), tde tde ?1, whl whl ?1, c c ?1 end if c = 0 xchbk [tde + ], [whl +] 2 (tde) ? (whl), tde tde +1, whl whl + 1, c c ?1 end if c = 0 [tde ?], [whl ? 2 (tde) ? (whl), tde tde ?1, whl whl ?1, c c ?1 end if c = 0 cmpme [tde + ], a 2 (tde) ?a, tde tde + 1, c c ?1 end if c = 0 or z = 0 v [tde ?], a 2 (tde) ?a, tde tde ?1, c c ?1 end if c = 0 or z = 0 v cmpmne [tde + ], a 2 (tde) ?a, tde tde + 1, c c ?1 end if c = 0 or z = 1 v [tde ?], a 2 (tde) ?a, tde tde ?1, c c ?1 end if c = 0 or z = 1 v cmpmc [tde + ], a 2 (tde) ?a, tde tde + 1, c c ?1 end if c = 0 or cy = 0 v [tde ?], a 2 (tde) ?a, tde tde ?1, c c ?1 end if c = 0 or cy = 0 v cmpmnc [tde + ], a 2 (tde) ?a, tde tde + 1, c c ?1 end if c = 0 or cy = 1 v [tde ?], a 2 (tde) ?a, tde tde ?1, c c ?1 end if c = 0 or cy = 1 v cmpbke [tde + ], [whl +] 2 (tde) (whl), tde tde + 1, v whl whl + 1, c c ?1 end if c = 0 or z = 0 [tde ?], [whl ? 2 (tde) (whl), tde tde ?1, v whl whl ?1, c c ?1 end if c = 0 or z = 0 chapter 27 instruction operations 677 user? manual u11316ej4v1ud mnemonic operands bytes operation flags s z ac p/v cy cmpbkne [tde + ], [whl +] 2 (tde) ?(whl), tde tde + 1, v whl whl + 1, c c ?1 end if c = 0 or z = 1 [tde ?], [whl ? 2 (tde) ?(whl), tde tde ?1, v whl whl ?1, c c ?1 end if c = 0 or z = 1 cmpbkc [tde + ], [whl +] 2 (tde) ?(whl), tde tde + 1, v whl whl + 1, c c ?1 end if c = 0 or cy = 0 [tde ?], [whl ? 2 (tde) ?(whl), tde tde ?1, v whl whl ?1, c c ?1 end if c = 0 or cy = 0 cmpbknc [tde + ], [whl +] 2 (tde) ?(whl), tde tde + 1, v whl whl + 1, c c ?1 end if c = 0 or cy = 1 [tde ?], [whl ? 2 (tde) ?(whl), tde tde ?1, v whl whl ?1, c c ?1 end if c = 0 or cy = 1 chapter 27 instruction operations 678 user? manual u11316ej4v1ud 27.3 instructions listed by type of addressing (1) 8-bit instructions (combinations expressed by writing a for r are shown in parentheses) mov, xch, add, addc, sub, subc, and or xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, shr, shl, ror4, rol4, dbnz, push, pop, movm, xchm, cmpme, cmpmne, cmpmnc, cmpmc, movbk, xchbk, cmpbke, cmpbkne, cmpbknc, cmpbkc, chkl, chkla table 27-1 list of instructions by 8-bit addressing (1/2) 2nd operand r saddr # byte a sfr 1st operand r saddr a (mov) (mov) mov (mov) note 6 mov add note 1 (xch) xch (xch) note 6 (xch) (add) note 1 (add) note 1 (add) notes 1, 6 (add) note 1 r mov (mov) mov mov mov add note 1 (xch) xch xch xch (add) note 1 add note 1 add note 1 add note 1 saddr mov (mov) note 6 mov mov add note 1 (add) note 1 add note 1 xch add note 1 sfr mov mov mov add note 1 (add) note 1 add note 1 !addr16 mov (mov) mov !!addr24 add note 1 mem mov [saddrp] add note 1 [%saddrg] mem3 r3 mov mov pswl pswh b, c stbc, wdm mov [tde +] (mov) [tde ? (add) note 1 movm note 4 (see the following page for the explanation of note .) chapter 27 instruction operations 679 user? manual u11316ej4v1ud table 27-1 list of instructions by 8-bit addressing (2/2) 2nd operand !addr16 mem r3 [whl +] [saddrp] pswl n none note 2 1st operand !!addr24 [%saddrg] pswh [whl ? a (mov) mov mov (mov) (xch) xch (xch) add note 1 add note 1 (add) note 1 r mov ror note 3 mulu xch divuw inc dec saddr inc dec dbnz sfr push pop chkl chkla !addr16 !!addr24 mem [saddrp] [%saddrg] mem3 ror4 rol4 r3 pswl pswh b, c dbnz stbc, wdm [tde +] [tde ? movbk note 5 notes 1. addc, sub, subc, and, or, xor and cmp are the same as add. 2. there is no 2nd operand, or the 2nd operand is not an operand address. 3. rol, rorc, rolc, shr and shl are the same as ror. 4. xchm, cmpme, cmpmne, cmpmnc and cmpmc are the same as movm. 5. xchbk, cmpbke, cmpbkne, cmpbknc and cmpbkc are the same as movbk. 6. if saddr is saddr2 in this combination, there is a short code length instruction. chapter 27 instruction operations 680 user? manual u11316ej4v1ud (2) 16-bit instructions (combinations expressed by writing ax for rp are shown in parentheses) movm, xchw, addw, subw, cmpw, muluw, mulw, divux, incw, decw, shrw, shlw, push, pop, addwg, subwg, pushu, popu, movtblw, macw, macsw, sacw table 27-2 list of instructions by 16-bit addressing (1/2) 2nd operand r saddr # word a sfrp 1st operand r saddr ax (movw) (movw) (movw) (movw) note 3 movw addw note 1 (xchw) (xchw) (xchw) note 3 (xchw) (add) note 1 (addw) note 1 (addw) notes 1,3 (addw) note 1 rp movw (movw) movw movw movw addw note 1 (xchw) xchw xchw xchw (addw) note 1 addw note 1 addw note 1 addw note 1 saddrp movw (movw) note 3 movw movw addw note 1 (addw) note 1 addw note 1 xchw addw note 1 sfrp movw movw movw addw note 1 (addw) note 1 addw note 1 !addr16 movw (movw) movw !!addr24 mem movw [saddrp] [%saddrg] psw sp addwg subwg post [tde +] (movw) byte (see the following page for the explanation of note .) chapter 27 instruction operations 681 user? manual u11316ej4v1ud table 27-2 list of instructions by 16-bit addressing (2/2) 2nd operand mem !!addr16 [saddrp] [whl +] byte n none note 2 1st operand !!addr24 [%saddrg] ax (movw) movw (movw) xchw xchw (xchw) rp movw shrw mulw note 4 shlw incw decw saddrp incw decw sfrp push pop !addr16 movtblw !!addr24 mem [saddrp] [%saddrg] psw push pop sp post push pop pushu popu [tde +] sacw byte macw macsw notes 1. subw and cmpw are the same as addw. 2. there is no 2nd operand, or the 2nd operand is not an operand address. 3. if saddrp is saddrp2 in this combination, there is a short code length instruction. 4. muluw and divux are the same as mulw. chapter 27 instruction operations 682 user? manual u11316ej4v1ud (3) 24-bit instructions (combinations expressed by writing whl for rg are shown in parentheses) movg, addg, subg, incg, decg, push, pop table 27-3 list of instructions by 24-bit addressing 2nd operand rg # imm24 whl saddrg !!addr24 mem1 [%saddrg] sp none note 1st operand rg whl (movg) (movg) (movg) (movg) (movg) movg movg movg (addg) (addg) (addg) addg (subg) (subg) (subg) subg rg movg (movg) movg movg movg incg addg (addg) addg decg subg (subg) subg push pop saddrg (movg) movg !!addr24 (movg) movg mem1 movg [%saddrg) movg sp movg movg incg decg note there is no 2nd operand, or the 2nd operand is not an operand address. (4) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr, bfset table 27-4 list of instructions by bit manipulation instruction addressing 2nd operand saddr. bit sfr. bit /saddr.bit /sfr. bit a.bit x. bit /a. bit /x. bit cy pswl. bit pswh. bit /pswl. bit /pswh. bit none note mem2. bit /mem2. bit !addr16. bit /!addr16. bit 1st operand !!addr24. bit /!!addr24. bit cy mov1 and1 not1 and1 set1 set1 or1 clr1 xor1 saddr. bit mov1 not1 sfr. bit set1 a. bit clr1 x. bit bf pswl. bit bt pswh. bit btclr mem2. bit bfset !addr16. bit !!addr24. bit note there is no 2nd operand, or the 2nd operand is not an operand address. chapter 27 instruction operations 683 user? manual u11316ej4v1ud (5) call/return instructions / branch instructions call, callf, callt, brk, ret, reti, retb, retcs, retcsb, brkcs, br, bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz table 27-5 list of instructions by call/return instruction / branch instruction addressing instruction address $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] rbn none operand basic bc note call call call call call call call callf callt brkcs brk instructions br br br br br br br br ret retcs reti retcsb retb compound bf instructions bt btclr bfset dbnz note bnz, bne, bz, be, bnc, bnl, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, and bh are the same as bc. (6) other instructions adjba, adjbs, cvtbw, location, sel, not, ei, di, swrs 684 user? manual u11316ej4v1ud chapter 28 electrical specifications absolute maximum ratings (t a = 25 c) caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. d/a converter reference input voltage parameter symbol conditions rating unit supply voltage v dd ?.5 to +7.0 v av dd av ss to v dd + 0.5 v av ss ?.5 to +0.5 v input voltage v i1 ?.5 to v dd + 0.5 v v i2 pd78p4038, 78p4038y only. ?.5 to +13.5 v test/v pp pin and p21/intp0/a9 pin in prom programming mode output voltage v o ?.5 to v dd + 0.5 v output low current i ol at one pin 15 ma total of all output pins 100 ma output high current i oh at one pin ?0 ma total of all output pins ?00 ma a/d converter reference input av ref1 ?.5 to v dd + 0.3 v voltage av ref2 ?.5 to v dd + 0.3 v av ref3 ?.5 to v dd + 0.3 v operating ambient temperature t a ?0 to +85 c storage temperature t stg ?5 to +150 c chapter 28 electrical specifications 685 user? manual u11316ej4v1ud operating conditions operating ambient temperature (t a ) : ?0 to +85 c rise time and fall time (t r , t f ) (at pins which are not specified) : 0 to 200 s power supply voltage and clock cycle time : see figure 28-1 . figure 28-1 power supply voltage and clock cycle time capacitance (t a = 25 c, v dd = v ss = 0 v) parameter input capacitance output capacitance i/o capacitance symbol c i c o c io conditions f = 1 mhz 0 v on pins other than measured pins min. typ. max. 10 10 10 unit pf pf pf 10,000 4,000 1,000 125 100 62.5 10 01234567 guaranteed operating range power supply voltage [v] clock cycle time t cyk [ns] chapter 28 electrical specifications 686 user s manual u11316ej4v1ud oscillator characteristics (t a = ?0 to +85 c, v dd = +4.5 to 5.5 v, v ss = 0 v) caution when using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. remark for the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. resonator ceramic or crystal resonator external clock recommended circuit parameter oscillator frequency (f xx ) x1 input frequency (f x ) x1 input rise and fall times (t xr , t xf ) x1 input high-level and low- level widths (t wxh , t wxl ) min. 4 4 0 10 max. 32 32 10 125 unit mhz mhz ns ns v ss1 x1 x2 c2 c1 x1 x2 hcmos inverter chapter 28 electrical specifications 687 user s manual u11316ej4v1ud oscillator characteristics (t a = ?0 to +85 c, v dd = +2.7 to 5.5 v, v ss = 0 v) caution when using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. remark for the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. resonator ceramic resonator or crystal external clock recommended circuit parameter oscillator frequency (f xx ) x1 input frequency (f x ) x1 input rise and fall times (t xr , t xf ) x1 input high-level and low- level widths (t wxh , t wxl ) min. 4 4 0 10 max. 16 16 10 125 unit mhz mhz ns ns v ss1 x1 x2 c2 c1 x1 x2 hcmos inverter chapter 28 electrical specifications 688 user s manual u11316ej4v1ud dc characteristics (t a = ?0 to +85 c, v dd = av dd = +2.7 to 5.5 v, v ss = av ss = 0 v) (1/2) notes 1. pd784038 subseries: x1, x2, reset, p12/asck2/sck2, p20/nmi, p21/intp0, p22/intp1, p23/intp2/ ci, p24/intp3, p25/intp4/asck/sck1, p26/intp5, p27/si0, p32/sck0/scl, p33/so0/sda,test pd784038y subseries: x1, x2, reset, p12/asck2/sck2, p20/nmi, p21/intp0, p22/intp1, p23/intp2/ ci, p24/intp3, p25/intp4/asck/sck1, p26/intp5, p27/si0,test 2. pd784031, 784031y, 784031(a): ad0 to ad7, a8 to a15 other: p40/ad0 to p47/ad7, p50/a8 to p57/a15 3. pd784031, 784031y, 784031(a): p60/a16 to p63/a19, rd, wr, p66/wait/hldrq, p67/refrq/hldak other: p60/a16 to p63/a19, p64/rd, p65/wr, p66/wait/hldrq, p67/refrq/hldak 4. p00 to p07 5. p10 to p17 6. p32/sck0/scl, p33/so0/sda ( pd784038y subseries only) parameter input low voltage input high voltage output low voltage output high voltage x1 input low current x1 input high current symbol v il1 v il2 v il3 v ih1 v ih2 v ih3 v ol1 v ol2 v ol3 v oh1 v oh2 i il i ih conditions for pins other than those described in notes 1 , 2 , 3 , 4 , and 6 for pins described in notes 1 , 2 , 3 , 4 , and 6 v dd = +5.0 v 10% for pins described in notes 2 , 3 , and 4 for pins other than those described in notes 1 and 6 for pins described in notes 1 and 6 v dd = +5.0 v 10% for pins described in notes 2 , 3 , and 4 i ol = 2 ma for pins other than those described in note 6 i ol = 3 ma for pins described in note 6 i ol = 6 ma for pins described in note 6 v dd = +5.0 v 10% i ol = 8 ma for pins described in notes 2 and 5 i oh = 2 ma v dd = +5.0 v 10% i oh = 5 ma for pins described in note 4 extc = 0 0 v v i v il2 extc = 0 v ih2 v i v dd min. 0.3 0.3 0.3 0.7v dd 0.8v dd 2.2 v dd 1.0 v dd 1.4 typ. max. 0.3v dd 0.2v dd +0.8 v dd + 0.3 v dd + 0.3 v dd + 0.3 0.4 0.4 0.6 1.0 30 +30 unit v v v v v v v v v v v v a a chapter 28 electrical specifications 689 user s manual u11316ej4v1ud dc characteristics (t a = ?0 to +85 c, v dd = av dd = +2.7 to 5.5 v, v ss = av ss = 0 v) (2/2) parameter input leakage current output leakage current v dd supply current pull-up resistor symbol i l| i lo i dd1 i dd2 i dd3 r l conditions 0 v v i v dd for pins other than x1 when extc = 0 0 v v o v dd operation mode f xx = 32 mhz v dd = +5.0 v 10% f xx = 16 mhz v dd = +2.7 to 3.3 v halt mode f xx = 32 mhz v dd = +5.0 v 10% f xx = 16 mhz v dd = +2.7 to 3.3 v idle mode f xx = 32 mhz (extc = 0) v dd = +5.0 v 10% f xx = 16 mhz v dd = +2.7 to 3.3 v v i = 0 v min. 15 typ. 25 12 13 8 max. 10 10 45 25 26 12 12 8 80 unit a a ma ma ma ma ma ma k ? chapter 28 electrical specifications 690 user s manual u11316ej4v1ud ac characteristics (t a = ?0 to +85 c, v dd = av dd = +2.7 to 5.5 v, v ss = av ss = 0 v) (1) read/write operation (1/2) remarks t: t cyk (system clock cycle time) a: 1 (during address wait); otherwise 0 n: number of wait states (n 0) unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter address setup time astb high-level width address hold time (from astb ) address hold time (from rd ) delay from address to rd address float time (from rd ) delay from address to data input delay from astb to data input delay from rd to data input delay from astb to rd data hold time (from rd ) delay from rd to address active delay from rd to astb rd low-level width address hold time (from wr ) delay from address to wr delay from astb to data output delay from wr to data output delay from astb to wr symbol t sast t wsth t hstla t hra t dar t fra t daid t dstid t drid t dstr t hrid t dra t drst t wrl t hwa t daw t dstod t dwod t dstw min. (0.5 + a) t 15 (0.5 + a) t 31 (0.5 + a) t 17 (0.5 + a) t 40 0.5t 24 0.5t 34 0.5t 14 (1 + a) t 9 (1 + a) t 15 0.5t 9 0 0.5t 8 0.5t 12 1.5t 8 1.5t 12 0.5t 17 (1.5 + n) t 30 (1.5 + n) t 40 0.5t 14 (1 + a) t 5 (1 + a) t 15 0.5t 9 max. 0 (2.5 + a + n) t 37 (2.5 + a + n) t 52 (2 + n) t 40 (2 + n) t 60 (1.5 + n) t 50 (1.5 + n) t 70 0.5t + 19 0.5t + 35 0.5t 11 after program is read after data is read conditions v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v chapter 28 electrical specifications 691 user s manual u11316ej4v1ud (1) read/write operation (2/2) note the hold time includes the time during which v oh1 and v ol1 are held under the load conditions of c l = 50 pf and r l = 4.7 k ? . remarks t: t cyk (system clock cycle time) n: number of wait states (n 0) (2) bus hold timing remarks t: t cyk (system clock cycle time) a: 1 (during address wait); otherwise 0 n: number of wait states (n 0) unit ns ns ns ns ns ns ns parameter data setup time (to wr ) data hold time (from wr ) note delay from wr to astb wr low-level width symbol t sodw t hwod t dwst t wwl min. (1.5 + n) t 30 (1.5 + n) t 40 0.5t 5 0.5t 25 0.5t 12 (1.5 + n) t 30 (1.5 + n) t 40 max. conditions v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v unit ns ns ns ns ns ns ns ns parameter delay from hldrq to float delay from hldrq to hldak delay from float to hldak delay from hldrq to hldak delay from hldak to active min. 1t 20 1t 30 max. (6 + a + n) t + 50 (7 + a + n) t + 30 (7 + a + n) t + 40 1t + 30 2t + 40 2t + 60 conditions v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v symbol t fhqc t dhqhhah t dcfha t dhqlhal t dhac chapter 28 electrical specifications 692 user s manual u11316ej4v1ud (3) external wait timing remarks t: t cyk (system clock cycle time) a: 1 (during address wait); otherwise 0 n: number of wait states (n 0) (4) refresh timing remark t: t cyk (system clock cycle time) parameter delay from address to wait input delay from astb to wait input hold time from astb to wait delay from astb to wait delay from rd to wait input hold time from rd to wait delay from rd to wait delay from wait to data input delay from wait to wr delay from wait to rd delay from wr to wait input hold time from wr to wait delay from wr to wait unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. (0.5 + n) t + 5 (0.5 + n) t +10 nt + 5 nt + 10 0.5t 0.5t nt + 5 nt + 10 max. (2 + a) t 40 (2 + a) t 60 1.5t 40 1.5t 60 (1.5 + n) t 40 (1.5 + n) t 60 t 50 t 70 (1 + n) t 40 (1 + n) t 60 0.5t 5 0.5t 10 t 50 t 75 (1 + n) t 40 (1 + n) t 70 conditions v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v symbol t dawt t dstwt t hstwth t dstwth t drwtl t hrwt t drwth t dwtid t dwtw t dwtr t dwwtl t hwwt t dwwth unit ns ns ns ns ns ns ns ns ns parameter random read/write cycle time refrq low-level pulse width delay from astb to refrq delay from rd to refrq delay from wr to refrq delay from refrq to astb refrq high-level pulse width max. min. 3t 1.5t 25 1.5t 30 0.5t 9 1.5t 9 1.5t 9 0.5t 15 1.5t 25 1.5t 30 symbol t rc t wrfql t dstrfq t drrfq t dwrfq t drfqst t wrfqh conditions v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v chapter 28 electrical specifications 693 user s manual u11316ej4v1ud serial operation (t a = ?0 to +85 c, v dd = +2.7 to 5.5 v, av ss = v ss = 0 v) (1) csi remarks 1. the values in this table are those when c l is 100 pf. 2. t : serial clock cycle set by software. the minimum value is 16/f xx . 3. f xx : oscillator frequency (2) i 2 c ( pd784038y subseries only) unit ns s ns s ns s ns ns ns ns parameter serial clock cycle time (sck0) serial clock low-level width (sck0) serial clock high-level width (sck0) si0 setup time (to sck0 ) si0 hold time (to sck0 ) so0 output delay time (to sck0 ) min. 10/f xx + 380 t 5/f xx + 150 0.5t 40 5/f xx + 150 0.5t 40 40 5/f xx + 40 0 0 max. 5/f xx + 150 5/f xx + 400 conditions input external clock when sck0 and so0 are cmos i/o output input external clock when sck0 and so0 are cmos i/o output input external clock when sck0 and so0 are cmos i/o output cmos push-pull output (3-wire serial i/o mode) open-drain output (2-wire serial i/o mode), r l = 1 k ? symbol t cysk0 t wskl0 t wskh0 t sssk0 t hssk0 t dsbsk1 t dsbsk2 parameter scl clock frequency time to hold low scl clock time to hold high scl clock data hold time data setup time rise time of sda or scl signal fall time of sda or scl signal load capacitance of each bus line symbol f scl t low t high t hd ; dat t su ; dat t r t f cb unit khz s s ns ns ns ns pf i 2 c bus in standard mode f xx = 4 to 32 mhz min. max. 0 100 4.7 4.0 300 250 1,000 300 400 i 2 c bus in standard mode f xx = 8 to 32 mhz min. max. 0 400 1.3 0.6 300 900 100 20 + 0.1cb 300 20 + 0.1cb 300 400 chapter 28 electrical specifications 694 user s manual u11316ej4v1ud parameter serial clock cycle time (sck1, sck2) serial clock low-level width (sck1, sck2) serial clock high-level width (sck1, sck2) setup time for si1 and si2 (to sck1, sck2 ) hold time for si1 and si2 (to sck1, sck2 ) output delay time for so1 and so2 (to sck1, sck2 ) output hold time for so1 and so2 (to sck1, sck2 ) (3) ioe1, ioe2 remarks 1. the values in this table are those when c l is 100 pf. 2. t: serial clock cycle set by software. the minimum value is 16/f xx . (4) uart, uart2 unit ns ns ns ns ns ns ns ns ns ns ns ns ns min. 250 500 t 85 210 0.5t 40 85 210 0.5t 40 40 40 0 0.5t cysk1 40 max. 50 symbol t cysk1 t wskl1 t wskh1 t sssk1 t hssk1 t dsosk t hsosk conditions input v dd = +5.0 v 10% v dd = +2.7 to 5.5 v output internal, divided by 16 input v dd = +5.0 v 10% v dd = +2.7 to 5.5 v output internal, divided by 16 input v dd = +5.0 v 10% v dd = +2.7 to 5.5 v output internal, divided by 16 when data is transferred unit ns ns ns ns ns ns parameter asck clock input cycle time asck clock low-level width asck clock high-level width symbol t cyask t waskl t waskh min. 125 250 52.5 85 52.5 85 max. conditions v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v chapter 28 electrical specifications 695 user s manual u11316ej4v1ud clock output note operation note not provided in the pd784031, 784031y, and 784031(a). remark n: divided frequency ratio set by software in the cpu (n = 1, 2, 4, 8, 16) t: t cyk (system clock cycle time) unit ns ns ns ns ns ns ns ns ns parameter clkout cycle time clkout low-level width clkout high-level width clkout rise time clkout fall time min. nt 0.5t cycl 10 0.5t cycl 20 0.5t cycl 10 0.5t cycl 20 max. 10 20 10 20 conditions v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v v dd = +5.0 v 10% v dd = +2.7 to 5.5 v symbol t cycl t cll t clh t clr t clf chapter 28 electrical specifications 696 user s manual u11316ej4v1ud other operations (a) pd784035, 784036, 784037, 784038, 78p4038, 78p4038y, 784031(a), 784035(a), 784036(a) remark t cysmp : sampling clock set by software t cycpu : cpu operation clock set by software in the cpu (b) pd784031, 784031y, 784035y, 784036y, 784037y, 784038y remark t cysmp : sampling clock set by software t cycpu : cpu operation clock set by software in the cpu unit s s ns ns ns ns s s s s parameter nmi low-level width nmi high-level width intp0 low-level width intp0 high-level width low-level width for intp1- intp3 and ci high-level width for intp1- intp3 and ci low-level width for intp4 and intp5 high-level width for intp4 and intp5 reset low-level width reset high-level width symbol t wnil t wnih t wit0l t wit0h t wit1l t wit1h t wit2l t wit2h t wrsl t wrsh min. 10 10 4t cysmp 4t cysmp 4t cycpu 4t cycpu 10 10 10 10 max. conditions unit s s ns ns ns ns s s s s parameter nmi low-level width nmi high-level width intp0 low-level width intp0 high-level width low-level width for intp1- intp3 and ci high-level width for intp1- intp3 and ci low-level width for intp4 and intp5 high-level width for intp4 and intp5 reset low-level width reset high-level width symbol t wnil t wnih t wit0l t wit0h t wit1l t wit1h t wit2l t wit2h t wrsl t wrsh min. 10 10 3t cysmp 3t cysmp 3t cycpu 3t cycpu 10 10 10 10 max. conditions chapter 28 electrical specifications 697 user? manual u11316ej4v1ud a/d converter characteristics (t a = ?0 to +85 c, v dd = av dd = av ref1 = +2.7 to 5.5 v, v ss = av ss = 0 v) note quantization error ( 1/2 lsb) is not included. this parameter is indicated as the ratio (%fsr) to the full- scale value. remark f xx : oscillation frequency conditions fr = 1 fr = 0 fr = 1 fr = 0 f xx = 32 mhz, cs = 1 stop mode, cs = 0 min. 8 120 180 24 36 ?.3 typ. 8 1,000 0.5 2.0 1.0 max. 8 1.0 1.0 1.0 0.8 1/2 av ref1 + 0.3 1.5 5.0 20 symbol t conv t samp v ian r an ai ref1 ai dd1 ai dd2 parameter resolution total error note ( pd784031, 784031y, 784031(a), mask rom version) total error note ( pd78p4038, 78p4038y) linearity calibration note quantization error conversion time sampling time analog input voltage analog input impedance av ref1 current av dd supply current v dd = av dd = +5.0 v 10% v dd = av dd = +2.7 to 4.5 v t a = -10 to +85 c unit bit %fsr %fsr %fsr %fsr lsb t cyk t cyk t cyk t cyk v m ? ma ma a chapter 28 electrical specifications 698 user s manual u11316ej4v1ud d/a converter characteristics (t a = ?0 to +85 c, v dd = av dd = +2.7 to 5.5 v, v ss = av ss = 0 v) parameter resolution total error settling time output resistance analog reference voltage resistance of av ref2 and av ref3 reference power supply input current symbol r o av ref2 av ref3 r airef ai ref2 ai ref3 conditions load conditions: v dd = av dd = av ref2 4 m ? , 30 pf = +2.7 to 5.5 v av ref3 = 0 v v dd = av dd = +2.7 to 5.5 v av ref2 = 0.75v dd av ref3 = 0.25v dd load conditions: v dd = av dd = av ref2 2 m ? , 30 pf = +2.7 to 5.5 v av ref3 = 0 v v dd = av dd = +2.7 to 5.5 v av ref2 = 0.75v dd av ref3 = 0.25v dd load conditions: 2 m ? , 30 pf dacs0, 1 = 55 h dacs0, 1 = 55 h min. 8 0.75v dd 0 4 0 5 typ. 10 8 max. 0.6 0.8 0.8 1.0 10 v dd 0.25v dd 5 0 unit bit % % % % s k ? v v k ? ma ma chapter 28 electrical specifications 699 user s manual u11316ej4v1ud data retention characteristics (t a = ?0 to +85 c) note reset, p20/nmi, p21/intp0, p22/intp1, p23/intp2/ci, p24/intp3, p25/intp4/asck/sck1, p26/intp5, p27/si0, p32/sck0/scl, and p33/so0/sda pins ac timing test points parameter data retention voltage data retention current note ( pd784031, 784031y, 784031(a), mask rom version) data retention current ( pd78p4038, 78p4038y) v dd rise time v dd fall time v dd hold time (to stop mode setting) stop clear signal input time oscillation settling time input low voltage input high voltage conditions stop mode v dddr = +2.7 to 5.5 v v dddr = +2.5 v v dddr = +2.7 to 5.5 v v dddr = +2.5 v crystal ceramic resonator specific pins note min. 2.5 200 200 0 0 30 5 0 0.9v dddr typ. 10 2 30 10 max. 5.5 50 10 50 40 0.1v dddr v dddr unit v a a a a s s ms ms ms ms v v symbol v dddr i dddr i dddr t rvd t fvd t hvd t drel t wait v il v ih 0.8v dd or 2.2 v 0.8 v 0.8v dd or 2.2 v 0.8 v test points v dd - 1 v 0.45 v chapter 28 electrical specifications 700 user s manual u11316ej4v1ud timing waveform (1) read operation (2) write operation astb a8-a19 ad0-ad7 rd t wsth t sast t dstid t hstla t drst t fra t drid t dar t wrl t dstr t daid t hra t dra t hrid astb a8-a19 ad0-ad7 wr t wsth t sast t hstla t dwst t daw t dstw t hwod t dstod t dwod t sodw t wwl t hwa chapter 28 electrical specifications 701 user s manual u11316ej4v1ud hold timing external wait signal input timing (1) read operation (2) write operation astb a8-a19 ad0-ad7 rd wait t dstwt t hstwth t dstwth t dawt t dwtid t dwtr t drwtl t hrwt t drwth astb a8-a19 ad0-ad7 wr wait t dstwt t hstwth t dstwth t dawt t dwtw t dwwtl t hwwt t dwwth hldrq hldak t dhqhhah t fhqc t dcfha t dhac t dhqlhal adtb, a8-a19, ad0-ad7, rd, wr chapter 28 electrical specifications 702 user s manual u11316ej4v1ud refresh timing waveform (1) random read/write cycle (2) when refresh memory is accessed for a read and write at the same time (3) refresh after a read (4) refresh after a write astb wr rd t rc t rc t rc t rc t rc t wrfql astb rd, wr refrq t dstrfq t drfqst t wrfqh astb rd refrq t drfqst t drrfq t wrfql astb wr refrq t drfqst t dwrfq t wrfql chapter 28 electrical specifications 703 user s manual u11316ej4v1ud serial operation (1) csi (2) i 2 c ( pd784038y subseries only) (3) ioe1, ioe2 (4) uart, uart2 t high t r t hd;dat t su;dat t f t low scl sda asck, asck2 t waskh t waskl t cyask sck si so output data input data t sssk0 t hssk0 t dsbsk1 t wskl0 t wskh0 t cysk0 sck si so output data input data t sssk1 t hssk1 t dsosk t hsosk t wskl1 t wskh1 t cysk1 chapter 28 electrical specifications 704 user s manual u11316ej4v1ud clock output note timing note not provided in the pd784031, 784031y, and 784031(a). interrupt input timing reset input timing clkout t clh t cll t cycl t clf t clr nmi intp0 ci, intp1-intp3 intp4, intp5 t wnih t wnil t wit0h t wit0l t wit1h t wit1l t wit2h t wit2l reset t wrsh t wrsl chapter 28 electrical specifications 705 user s manual u11316ej4v1ud external clock timing data retention characteristics x1 t wxh t wxl t cyx t xf t xr v dd reset nmi (clearing by falling edge) nmi (clearing by rising edge) t hvd t fvd t rvd t drel v dddr stop mode setting t wait chapter 28 electrical specifications 706 user s manual u11316ej4v1ud parameter high-level input voltage low-level input voltage input leakage current high-level output voltage low-level output voltage output leakage current v ddp supply voltage v pp supply voltage v ddp supply current v pp supply current symbol v ih v il i lip v oh v ol i lo v dd v pp i dd i pp dc programming characteristics (t a = 25 5 c, v ss = 0 v) : pd78p4038 and 78p4038y only min. 2.2 0.3 2.4 6.25 4.5 12.2 typ. 6.5 5.0 12.5 10 10 5 1.0 max. v ddp + 0.3 0.8 10 0.45 10 6.75 5.5 12.8 40 40 50 100 unit v v a v v a v v v v ma ma ma a conditions 0 v i v ddp note i oh = 400 a i ol = 2.1 ma 0 v o v ddp , oe = v ih program memory write mode program memory read mode program memory write mode program memory read mode program memory write mode program memory read mode program memory write mode program memory read mode v pp = v ddp note the v ddp represents the v dd pin as viewed in the programming mode. chapter 28 electrical specifications 707 user s manual u11316ej4v1ud ac programming characteristics (t a = 25 5 c, v ss = 0 v) : pd78p4038 and 78p4038y only prom write mode (page program mode) parameter address setup time ce set time input data setup time address hold time input data hold time output data hold time v pp setup time v ddp setup time initial program pulse width oe set time valid data delay time from oe oe pulse width in the data latch pgm setup time ce hold time oe hold time symbol t as t ces t ds t ah t ahl t ahv t dh t df t vps t vds t pw t oes t oe t lw t pgms t ceh t oeh min. 2 2 2 2 2 0 2 0 2 2 0.095 2 1 2 2 2 typ. 0.1 1 max. 130 0.105 2 unit s s s s s s s ns s s ms s ns s s s s conditions chapter 28 electrical specifications 708 user s manual u11316ej4v1ud prom read mode note t df is the time measured from when either oe or ce reaches v ih , whichever is faster. prom write mode (byte program mode) parameter address setup time ce set time input data setup time address hold time input data hold time output data hold time v pp setup time v ddp setup time initial program pulse width oe set time valid data delay time from oe symbol t as t ces t ds t ah t dh t df t vps t vds t pw t oes t oe symbol t acc t ce t oe t df t oh unit s s s s s ns s s ms s ns conditions max. 130 0.105 2 typ. 0.1 1 min. 2 2 2 2 2 0 2 2 0.095 2 typ. 1 1 min. 0 0 ce = oe = v il oe = v il ce = v il ce = v il or oe = v il ce = oe = v il conditions parameter data output time from address delay from ce to data output delay from oe to data output data hold time to oe or ce note data hold time to address unit ns s s ns ns max. 200 2 2 60 chapter 28 electrical specifications 709 user s manual u11316ej4v1ud prom write mode timing (page program mode) : pd78p4038 and 78p4038y only page data latch page program program verify data output hi-z hi-z hi-z a2-a16 a0, a1 d0-d7 v pp v ddp v pp v ddp + 1.5 v ddp v ddp ce pgm oe v ih v il v ih v il v ih v il t as t ahl t ds t dh t vps data input t pgms t oe t vds t ahv t df t ah t oeh t ces t ceh t pw t oes t lw chapter 28 electrical specifications 710 user s manual u11316ej4v1ud program program verify a0-a16 v pp v ddp v pp v ddp + 1.5 v ddp v ddp ce pgm v ih v il v ih v il t ds t pw hi-z hi-z hi-z d0-d7 v ih v il t as t ds t vps t vds t ces t df t ah t dh t oes t oe data input data output oe a0-a16 ce oe hi-z hi-z d0-d7 data output t ce valid address t acc note 1 t oh t oe note 1 t df note 2 prom write mode timing (byte program mode) : for reading within t acc , the delay of the oe input from falling edge of ce must be within t acc -t oe . 2. t df is the time measured from when either oe or ce reaches v ih , whichever is faster. chapter 29 package drawings 711 user? manual u11316ej4v1ud chapter 29 package drawings 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.20 0.20 14.00 0.20 0.13 0.825 i 17.20 0.20 j c 14.00 0.20 h 0.32 0.06 0.65 (t.p.) k 1.60 0.20 p 1.40 0.10 q 0.125 0.075 l 0.80 0.20 f 0.825 n 0.10 m 0.17 + 0.03 ? 0.07 p80gc-65-8bt-1 s 1.70 max. r3 + 7 ? 3 41 60 40 61 21 80 20 1 s s n j detail of lead end c d a b r k m l p i s q g f m h chapter 29 package drawings 712 user s manual u11316ej4v1ud 80-pin plastic tqfp (fine pitch) (12x12) item millimeters g h 0.22 0.05 1.25 a 14.0 0.2 c 12.0 0.2 d f 1.25 14.0 0.2 b 12.0 0.2 m n 0.08 0.145 0.05 p q 0.1 0.05 1.0 j 0.5 (t.p.) k l 0.5 1.0 0.2 i 0.08 s 1.1 0.1 r 3 + 4 ? 3 r h k l j f q g i t u s p detail of lead end note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. 60 41 40 21 61 80 120 m s s cd a b n m p80gk-50-9eu-1 t 0.25 u 0.6 0.15 chapter 29 package drawings 713 user s manual u11316ej4v1ud 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.2 0.4 14.0 0.2 0.13 0.825 i 17.2 0.4 j c 14.0 0.2 h 0.30 0.10 0.65 (t.p.) k 1.6 0.2 l 0.8 0.2 f 0.825 s80gc-65-3b9-6 n p q 0.10 2.7 0.1 0.1 0.1 r s 5 5 3.0 max. m 0.15 + 0.10 ? 0.05 60 61 40 80 1 21 20 41 s s n j detail of lead end c d a b r k m l p i s q g f m h 714 user? manual u11316ej4v1ud chapter 30 recommended soldering conditions this product should be soldered and mounted under the following recommended conditions. for details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. remark the soldering conditions for the pd784031ygc-8bt, 784031gc(a)-3b9, 784035ygk- -9eu, 784035gc(a)- -3b9, 784036ygk- -9eu, 784036gc(a)- -3b9, and 78p4038ygk-9eu are undetermined. contact an nec electronics sales representative for details. table 30-1 surface mounting type soldering conditions (1/2) (1) pd784031gc-8bt: 80-pin plastic qfp (14 x 14, 1.4 mm thickness) pd784035gc- -8bt: 80-pin plastic qfp (14 x 14, 1.4 mm thickness) pd784035ygc- -8bt: 80-pin plastic qfp (14 x 14, 1.4 mm thickness) pd784036gc- -8bt: 80-pin plastic qfp (14 x 14, 1.4 mm thickness) pd784036ygc- -8bt: 80-pin plastic qfp (14 x 14, 1.4 mm thickness) pd784037gc- -8bt: 80-pin plastic qfp (14 x 14, 1.4 mm thickness) pd784037ygc- -8bt: 80-pin plastic qfp (14 x 14, 1.4 mm thickness) pd784038gc- -8bt: 80-pin plastic qfp (14 x 14, 1.4 mm thickness) pd784038ygc- -8bt: 80-pin plastic qfp (14 x 14, 1.4 mm thickness) pd78p4038gc-8bt: 80-pin plastic qfp (14 x 14, 1.4 mm thickness) pd78p4038ygc-8bt: 80-pin plastic qfp (14 x 14, 1.4 mm thickness) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-00-2 (at 210 c or higher), count: two times or less vps package peak temperature: 215 c, time: 40 seconds max. vp15-00-2 (at 200 c or higher), count: two times or less wave soldering solder bath temperature: 260 c max., time: 10 seconds max., ws60-00-1 count: once, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating). chapter 30 recommended soldering conditions 715 user? manual u11316ej4v1ud table 30-1 surface mounting type soldering conditions (2/2) (2) pd784031gk-9eu: 80-pin plastic tqfp (fine pitch) (12 x 12) pd784031ygk-9eu: 80-pin plastic tqfp (fine pitch) (12 x 12) pd784035gk- -9eu: 80-pin plastic tqfp (fine pitch) (12 x 12) pd784036gk- -9eu: 80-pin plastic tqfp (fine pitch) (12 x 12) pd784037gk- -9eu: 80-pin plastic tqfp (fine pitch) (12 x 12) pd784037ygk- -9eu: 80-pin plastic tqfp (fine pitch) (12 x 12) pd784038gk- -9eu: 80-pin plastic tqfp (fine pitch) (12 x 12) pd784038ygk- -9eu: 80-pin plastic tqfp (fine pitch) (12 x 12) pd78p4038gk-9eu: 80-pin plastic tqfp (fine pitch) (12 x 12) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-107-2 (at 210 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) vps package peak temperature: 215 c, time: 40 seconds max. vp15-107-2 (at 200 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) note after opening the dry pack, store it at 25 c or less and 65%rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). 716 user? manual u11316ej4v1ud appendix a differences with pd784026 subseries table a-1 differences with pd784026 subseries (1/3) item pd784026 subseries pd784038 subseries operating frequency 4 mhz f xx 25 mhz 4 mhz f xx 32 mhz (target value) minimum instruction 160 ns (at 25 mhz) 125 ns (at 32 mhz) execution time internal rom/ram pd784020 : none/512 bytes pd784031 : none/2,048 bytes capacity pd784021 : none/2,048 bytes pd784035 : 48 kbytes/2,048 bytes pd784025 : 48 kbytes/2,048 bytes pd784036 : 64 kbytes/2,048 bytes pd784026 : 64 kbytes/2,048 bytes pd784037 : 96 kbytes/3,584 bytes pd78p4026 : 64 kbytes/2,048 bytes (prom) pd784038 : 128 kbytes/4,352 bytes pd78p4038 : 128 kbytes/4,352 bytes (prom) prom size selection two types of memory size can be selected four types of memory size can be selected according to mask rom model. according to mask rom model. 76543210 76543210 ims ims7 ims6 ims5 ims4 ims3 ims2 ims1 ims0 ims ims7 ims6 ims5 ims4 ims3 ims2 ims1 ims0 ims7 to 0 memory size ims7 to 0 memory size ffh same as pd784026 ffh same as pd784038 efh same as pd784025 eeh same as pd784037 dch same as pd784036 cch same as pd784035 d/a conversion mode resistor string mode r-2r resistor ladder mode remark n = 0, 1 remark n = 0, 1 dacsn dacen internal bus reset 88 av ref2 av ref3 anon r r r r tap selector selector av ref2 av ref3 anon r r r 2r 2r 2r 2r dacsn dacen internal bus appendix a differences with pd784026 subseries 717 user? manual u11316ej4v1ud table a-1 differences with pd784026 subseries (2/3) item pd784026 subseries pd784038 subseries serial interface ?uart/ioe (3-wire serial i/o) 2 channels ?uart/ioe (3-wire serial i/o) 2 channels ?csi (3-wire serial i/o, sbi) 1 channel ?csi (3-wire serial i/o, 2-wire serial i/o) 1 channel appendix a differences with pd784026 subseries 718 user? manual u11316ej4v1ud table a-1 differences from pd784026 subseries (3/3) item pd784026 subseries pd784038 subseries serial interface 719 user? manual u11316ej4v1ud appendix b development tools the following development tools are available for system development using the pd784038 subseries. figure b-1 shows the development tools. ? for pc98-nx series unless otherwise specified, products supported by ibm pc/at tm and compatible machines can be used for the pc98-nx series. when using the pc98-nx series, refer to the explanation of ibm pc/at and compatible machines. for windows unless otherwise specified, ?indows?indicates the following oss. ? windows 3.1 ? windows 95, 98, 2000 ? windows nt tm ver. 4.0 appendix b development tools 720 user? manual u11316ej4v1ud figure b-1 development tool configuration (1/2) (1) when using in-circuit emulator ie-78k4-ns language processing software ? assembler package ? c compiler package ? c library source file ? device file debugging tools ? system simulator ? integrated debugger ? device file embedded software ? real-time os host machine (pc) interface adapter, pc card interface, etc. prom writing environment prom programmer prom write adapter on-chip prom product in-circuit emulator emulation board emulation probe power supply unit conversion socket or conversion adapter target system appendix b development tools 721 user s manual u11316ej4v1ud figure b-1 development tool configuration (2/2) (2) when using in-circuit emulator ie-784000-r remark parts enclosed by broken lines vary depending on the product. refer to b.3.1 hardware . language processing software ? assembler package ? c compiler package ? c library source file ? device file debugging tools ? system simulator ? integrated debugger ? device file embedded software ? real-time os host machine (pc or ews) interface board prom writing environment prom programmer prom write adapter on-chip prom product in-circuit emulator interface adapter emulation board i/o emulation board probe board emulation probe conversion board emulation probe conversion socket or conversion adapter target system appendix b development tools 722 user? manual u11316ej4v1ud b.1 language processing software sp78k4 78k/iv series development tools (software) common to the 78k/iv series are combined in this software package package. part number: s sp78k4 ra78k4 assembler package program that converts a program written in mnemonic to an executable microcontroller object code. in addition, this assembler package has functions to create symbol tables and optimize branch instructions, etc. automatically. use this in combination with the device file (df784038) sold separately. appendix b development tools 723 user? manual u11316ej4v1ud remark the part number differs depending on the host machine and operating system used. s sp78k4 host machine os supply medium ab17 pc-9800 series, japanese windows cd-rom bb17 ibm pc/at compatibles english windows s ra78k4 s cc78k4 host machine os supply medium ab13 pc-9800 series, japanese windows 3.5-inch 2hd fd bb13 ibm pc/at compatibles english windows ab17 japanese windows cd-rom bb17 english windows 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) s df784038 s cc78k4-l host machine os supply medium ab13 pc-9800 series, japanese windows 3.5-inch 2hd fd bb13 ibm pc/at compatibles english windows 3p16 hp9000 series 700 hp-ux (rel. 10.10) dat 3k13 sparcstation sunos (rel. 4.1.4) 3.5-inch 2hd fd 3k15 solaris (rel. 2.5.1) 1/4-inch cgmt appendix b development tools 724 user? manual u11316ej4v1ud b.2 prom writing tools (1) hardware pg-1500 this prom programmer can program single-chip microcontrollers containing prom in a stand-alone mode or under the control of the host machine, when a board supplied as an accessory and an optionally available prom programmer adapter are connected. it can also program representative proms, from 256-kbit to 4-mbit models. pa-78p4026gc this is a prom programmer adapter for the pd78p4038 and is connected to the pg-1500. pa-78p4038gk pa-78p4026gc: for 80-pin plastic qfp (gc-3b9, gc-8bt type) pa-78p4038gk: 80-pin plastic tqfp (fine pitch) (gk-9eu type) (2) software pg-1500 controller the pg-1500 controller connects the pg-1500 and the host machine with a serial and parallel interfaces to control the pg-1500 on the host machine. host machine os supply media part number pc-9800 series ms-dos 3.5" 2hd s5a13pg1500 (ver.3.30 to ver.6.2 note1 ) 5" 2hd s5a10pg1500 ibm pc/at and note 2 3.5" 2hd s7b13pg1500 compatible machines 5" 2hd s7b10pg1500 notes 1. ver. 5.0 or above of ms-dos has a task swap function, but this function cannot be used with the above software. 2. the following oss for the ibm pc are supported. (ver. 5.0 or above of ms-dos has a task swap function, but this function cannot be used with the above software.) os version pc dos ver.5.02 to ver.6.3 j6.1/v to j6.3/v (only the english version is supported.) ms-dos ver.5.0 to ver.6.22 5.0/v to 6.2/v (only the english version is supported.) ibm dos tm j5.02/v (only english version is supported.) appendix b development tools 725 user? manual u11316ej4v1ud b.3 debugging tools b.3.1 hardware (1/2) (1) when using in-circuit emulator ie-78k4-ns ie-78k4-ns in-circuit emulator used to debug hardware and software when developing application in-circuit emulator systems using the 78k/iv series. supports the integrated debugger (id78k4-ns). use in combination with an interface adapter to connect to the power supply unit, emulation probe, and host machine. ie-70000-mc-ps-b adapter to supply power from a socket of ac 100 v to 240 v power supply unit ie-70000-98-if-c interface adapter required when a pc-9800 series pc (except notebook type) is used interface adapter as the host machine for the ie-78k4-ns (c bus supported) ie-70000-cd-if-a pc card and interface cable required when a notebook pc is used as the host pc card interface machine for the ie-78k4-ns (pcmcia socket supported) ie-70000-pc-if-c interface adapter required when using an ibm pc/at compatible as the host machine interface adapter for the ie-78k4-ns (isa bus supported) ie-70000-pci-if-a interface adapter required when using a pc that incorporates pci bus as the host interface adapter machine for the ie-78k4-ns ie-784038-ns-em1 board to emulate the peripheral hardware specific to device. used in combination with emulation board an in-circuit emulator. np-80gk probe used to connect the in-circuit emulator and the target system. this is for an 80 emulation probe pin plastic tqfp (fine pitch) (gk-9eu type). tgk-080sdw conversion adapter to connect the np-80gk and a target system board on which an conversion adapter 80-pin plastic tqfp (fine pitch) (gk-9eu type) can be mounted (refer to figure b-4 ) np-80gc-tq probe used to connect the in-circuit emulator and the target system. this is for an 80-pin np-h80gc-tq plastic qfp (gc-3b9 or gc-8bt type). emulation probe tgc-080sbp conversion socket to connect the np-80gc-tq or np-h80gc-tq and a target system board conversion socket (refer on which an 80-pin plastic qfp (gc-3b9 or gc-8bt type) can be mounted to figure b-3 ) remarks 1. np-80gk, np-80gc-tq, and np-h80gc-tq are products made by naito densei machida mfg.co., ltd. for further information, contact naito densei machida mfg. co., ltd. (tel: +81-45-475-4191) 2. tgk-080sdw and tgc-080sbp products made by tokyo eletech corporation. for further information, contact daimaru kogyo, ltd. tokyo electronics department (tel: +81-3-3820-7112) osaka electronics department (tel: +81-6-6244-6672) 3. the tgk-080sdw and tgc-080sbp are sold individually. appendix b development tools 726 user? manual u11316ej4v1ud b.3.1 hardware (2/2) (2) when using in-circuit emulator ie-784000-r ie-784000-r the ie-784000-r is an in-circuit emulator common to the 78k/iv series, and is used in in-circuit emulator combination with ie-784000-r-em and ie-784038-r-em1, which are sold separately. this in- circuit emulator debugs the connected host machine. an integrated debugger (id78k4) and device file (sold separately) are required to enable debugging in c language and structured assembly language at the source program level. more efficient debugging and program verification is possible with functions such as c0 coverage. connect to a host machine via ethernet tm or a dedicated bus. an interface adapter (sold separately) is required for connection. ie-70000-98-if-c interface adapter required when a pc-9800 series (except notebook type pc) is used interface adapter as the host machine for the ie-784000-r (c bus supported) ie-70000-pc-if-c interface adapter required when using an ibm pc/at compatible as the host machine interface adapter (isa bus supported) ie-78000-r-sv3 interface adapter and cable required when an ews is used as the host machine for interface adapter the ie-784000-r. connect to a board inside the ie-784000-r. note that 10base-5 is supported as the ethernet. a commercial conversion adapter is required for other systems. ie-784000-r-em emulation board common to 78k/iv series ie-784038-r-em1 board to emulate peripheral hardware specific to device emulation board ie-78k4-r-ex2 conversion board for 80-pin packages required when using the ie-784038-r-em1 on emulation probe conversion board ie-784000-r ep-78054gk-r probe to connect the in-circuit emulator and the target system. for 80-pin plastic emulation probe tqfp (fine pitch)(gk-9eu type). tgk-080sdw conversion adapter to connect the ep-78054gk-r and a target system board on conversion adapter which an 80-pin plastic tqfp (fine pitch)(gk-9eu type) can be mounted (refer to figure b-7 ) ep-78230gc-r probe to connect the in-circuit emulator and the target system. for 80-pin plastic qfp emulation probe (gc-3b9 or gc-8bt type). ev-9200gc-80 conversion socket to connect the ep-78230gc-r and a target system board on which conversion socket an 80-pin plastic qfp (gc-3b9 or gc-8bt type) can be mounted (refer to figures b-5 and b-6 ) remarks 1. tgk-080sdw is a product made by tokyo eletech corporation. for further information, contact daimaru kogyo, ltd. tokyo electronics department (tel: +81-3-3820-7112) osaka electronics department (tel: +81-6-6244-6672) 2. the ev-9200gc-80 is sold in sets of 5. 3. the tgk-080sdw is sold individually. appendix b development tools 727 user? manual u11316ej4v1ud b.3.2 software sm78k4 this enables debugging at the c source level or assembler level while simulating system simulator operation of the target system on the host machine. the sm78k4 operates on windows. by using the sm78k4, logic verification and performance verification can be performed separately to hardware development without using an in-circuit emulator, thus improving development efficiency and software quality. use the sm78k4 in combination with the device file (df784038) sold separately. part number: s sm78k4 remark the part number differs depending on the host machine and operating system used. s sm78k4 host machine os supply medium ab13 ibm pc/at compatible japanese windows 3.5-inch 2hc fd bb13 english windows ab17 japanese windows cd-rom bb17 english windows id78k4-ns windows and osf/motif tm are employed as the gui for pc and ews respectively providing users with their unique look and operability. in addition, the enhanced c language supported debug function enables the result of a trace to be displayed at the c language level using the window integration function in which the source program, disassemble display, and memory display are linked to the result of trace. moreover, the efficiency of debugging programs that use a real-time os can be raised by installing function expansion modules such as task debuggers and system performance analyzers. control program to debug the 78k/iv series. use these integrated debuggers in combination with the device file (df784038) sold separately. part number: s id78k4-ns, s id78k4 remark the part number differs depending on the host machine and operating system used. s id78k4-ns s id78k4 host machine os supply medium ab13 ibm pc/at compatible japanese windows 3.5-inch 2hc fd bb13 english windows ab17 japanese windows cd-rom bb17 english windows integrated debugger (supporting in-circuit emulator ie-78k4-ns) id78k4 integrated debugger (supporting in-circuit emulator ie-784000-r) appendix b development tools 728 user s manual u11316ej4v1ud b.4 cautions on designing target system the connection condition diagrams for the emulation probe, conversion socket, and conversion adapter are shown below. design the system considering the shape of components, etc. to be mounted on the target system in accordance with this configuration. figure b-2 distance between in-circuit emulator and conversion socket note 350 mm in case of the np-h80gc-tq. target system conversion socket tgc-080sbp conversion adapter tgk-080sdw emulation probe np-80gc-tq, np-h80gc-tq, np-80gk emulation board ie-784038-ns-em1 cn2 connection 150 mm note cn2 cn1 in-circuit emulator ie-78k4-ns appendix b development tools 729 user? manual u11316ej4v1ud figure b-3 target system connection conditions (1) remark np-80gc-tq and np-h80gc-tq are products made by naito densei machida mfg. co., ltd. emulation board ie-784038-ns-em1 emulation probe np-80gc-tq, np-h80gc-tq 50 mm 25 mm 35 mm 35 mm 60 mm 10 mm 18.7 mm 10 mm conversion socket tgc-080sbp target system pin 1 appendix b development tools 730 user s manual u11316ej4v1ud figure b-4 target system connection conditions (2) remark np-80gk is a product made by naito densei machida mfg. co., ltd. tgk-080sdw is a product made by tokyo eletech corporation. emulation board ie-784038-ns-em1 emulation probe np-80gk 34 mm 25 mm 40 mm 45 mm 65 mm 23 mm 18 mm 11 mm conversion adapter tgk-080sdw target system pin 1 appendix b development tools 731 user s manual u11316ej4v1ud b.5 conversion socket (ev-9200gc-80) and conversion adapter (tgk-080sdw) (1) the package drawing of the conversion socket (ev-9200gc-80) and recommended board installation pattern figure b-5 package drawing of ev-9200gc-80 (reference) (unit: mm) a f d 1 no.1 pin index e ev-9200gc-80 b c m n o l k s r q p i h j g ev-9200gc-80-g1e item millimeters inches a b c d e f g h i j k l m n o p q r s 18.0 14.4 14.4 18.0 4-c 2.0 0.8 6.0 16.0 18.7 6.0 16.0 18.7 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.709 0.567 0.567 0.709 4-c 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014 0.091 0.059 appendix b development tools 732 user? manual u11316ej4v1ud figure b-6 recommended board installation pattern of ev-9200gc-80 (reference) (unit: mm) a f d e c b g j k l h i 0.026 item millimeters inches a b c d e f g h i j k l 19.7 15.0 15.0 19.7 6.0 + 0.001 0.002 +0.003 0.002 +0.001 0.002 +0.003 0.002 +0.003 0.002 +0.003 0.002 +0.001 0.001 +0.001 0.002 0.002 dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). caution appendix b development tools 733 user s manual u11316ej4v1ud (2) package drawing of the conversion adapter (tgk-080sdw) combined with the emulation probe and mounted on the board. figure b-7 tgk-080sdw package drawing (reference) (unit: mm) note made by tokyo eletech corp. item millimeters inches b 0.25 0.010 c 5.3 0.209 a 0.5x19=9.5 0.10 0.020x0.748=0.374 0.004 d 5.3 0.209 h 1.85 0.2 0.073 0.008 i 3.5 0.138 j 2.0 0.079 e 1.3 0.051 f 3.55 g 0.3 0.012 0.140 item millimeters inches b c 0.5x19=9.5 0.020x0.748=0.374 a 18.0 0.709 d h i 1.58 0.062 j 1.2 0.047 e 0.5x19=9.5 0.020x0.748=0.374 f 11.77 0.463 k 7.64 0.301 l 1.2 0.047 m q 1.2 0.047 r 1.58 0.062 s 3.55 0.140 n 1.58 0.062 o 1.2 p 7.64 0.301 0.047 w 6.8 0.268 x 8.24 0.324 y 14.8 0.583 t c 2.0 c 0.079 u 12.31 v 10.17 0.400 0.485 z 1.4 0.2 0.055 0.008 0.5 1.58 0.020 0.062 g 18.0 0.709 k 3.0 0.118 n 1.4 0.2 0.055 0.008 o 1.4 0.2 0.055 0.008 p h=1.8 1.3 h=0.071 0.051 l 0.25 m 14.0 0.551 0.010 q 0~5 0.000~0.197 11.77 0.5 0.463 0.020 tgk-080sdw-g1e t 2.4 0.094 u 2.7 0.106 v 3.9 0.154 r 5.9 s 0.8 0.031 0.232 e f g p r q q q o o o n ijjj lllm b c a t h d k s m2 screw u a v e c d b w x y z m f r u t v g s k j i h l n o p protrusion : 4 places q 734 user? manual u11316ej4v1ud appendix c embedded software the following embedded software is available for more efficient program development or maintenance of the pd784038, 784038y subseries. real-time operating system rx78k4 real-time os this is a real-time os complying with the itron specification. the rx78k4 nucleus and tools to create multiple information tables (configurator) have been added. use the rx78k4 in combination with the assembler package (ra78k4) and device file (df784038) (sold separately). 735 user? manual u11316ej4v1ud appendix d register index d.1 register index (register name) [h] hold mode register (hldm) ........................................ 607 [i] i2c bus control register (iicc) ........................... 451, 466 in-service priority register (ispr) ................................ 496 internal memory size switching register (ims) ............. 83 interrupt control register .............................................. 508 interrupt mask register (mk0h, mk0l, mk1l) ........... 512 interrupt mode control register (imc) ......................... 514 [m] macro service mode register ....................................... 541 memory extension mode register (mm) ............. 575, 588 [o] one-shot pulse output control register (ospc) ......... 197 oscillation stabilization time specification register (osts) .............................................................................. 107, 614 [p] port 0 (p0) .................................................................... 115 port 0 buffer register (p0l, p0h) ................................ 176 port 0 mode register (pm0) ......................................... 116 port 1 (p1) .................................................................... 120 port 1 mode control register (pmc1) .......................... 129 port 1 mode register (pm1) ......................................... 126 port 2 (p2) .................................................................... 131 port 3 (p3) .................................................................... 136 port 3 mode control register (pmc3) .......................... 141 port 3 mode register (pm3) ......................................... 141 port 4 (p4) .................................................................... 145 port 4 mode register (pm4) ......................................... 147 port 5 (p5) .................................................................... 151 port 5 mode register (pm5) ......................................... 153 port 6 (p6) .................................................................... 158 port 6 mode register (pm6) ......................................... 165 port 7 (p7) .................................................................... 168 port 7 mode register (pm7) ......................................... 168 prescaler mode register 0 (prm0) .................... 194, 362 prescaler mode register 1 (prm1) .................... 253, 292 prescaler mode register for serial clock (sprm) .............................................................................. 450, 469 [a] a/d conversion result register (adcr) ....................... 388 a/d converter mode register (adm) ........................... 389 asynchronous serial interface mode register (asim) ....................................................................................... 417 asynchronous serial interface mode register 2 (asim2) ....................................................................................... 417 asynchronous serial interface status register (asis) ....................................................................................... 420 asynchronous serial interface status register 2 (asis2) ....................................................................................... 420 [b] baud rate generator control register (brgc) ............. 437 baud rate generator control register 2 (brgc2) ....... 437 [c] capture register (cr02) .............................................. 191 capture register (cr12/cr12w) ................................ 251 capture register (cr22/cr22w) ................................ 290 capture/compare control register 0 (crc0) ............... 195 capture/compare control register 1 (crc1) ............... 254 capture/compare control register 2 (crc2) ............... 293 capture/compare register (cr11/cr11w) ................. 250 capture/compare register (cr21/cr21w) ................. 289 clock output mode register (clom) ........................... 491 clocked serial interface mode register (csim) . 449, 466 clocked serial interface mode register 1 (csim1) ..... 430 clocked serial interface mode register 2 (csim2) ..... 430 compare register (cr00, cr01) ................................. 191 compare register (cr10, cr10w) ............................. 250 compare register (cr20, cr20w) ............................. 289 compare register (cr30, cr30w) ............................. 360 [d] d/a conversion value setting register 0 (dacs0) ...... 407 d/a conversion value setting register 1 (dacs1) ...... 407 d/a converter mode register (dam) ........................... 407 [e] external interrupt mode register 0 (intm0) ................ 495 external interrupt mode register 1 (intm1) ................ 495 appendix d register index 736 user? manual u11316ej4v1ud program status word (pswl) ............................... 84, 516 programmable wait control register 1 (pwc1) ........... 589 programmable wait control register 2 (pwc2) ........... 589 pull-up resistor option register (puo) .................................... 118, 129, 134, 144, 150, 156, 167 pwm control register (pwmc) .................................... 379 pwm modulo register 0 (pwm0) ................................ 380 pwm modulo register 1 (pwm1) ................................ 380 pwm prescaler register (pwpr) ................................ 380 [r] real-time output port control register (rtpc) ............ 175 receive buffer (rxb) ................................................... 416 receive buffer 2 (rxb2) .............................................. 416 refresh area specification register (rfa) .................. 603 refresh mode register (rfm) ...................................... 602 [s] sampling clock selection register (scs0) .................. 497 serial shift register (sio) .................................... 448, 465 serial shift register 1 (sio1) ........................................ 429 serial shift register 2 (sio2) ........................................ 429 slave address register (sva) ............................. 465, 470 standby control register (stbc) ........................ 106, 612 [t] timer control register 0 (tmc0) ......................... 193, 361 timer control register 1 (tmc1) ......................... 252, 291 timer output control register (toc) ................... 196, 295 timer register 0 (tm0) ................................................. 191 timer register 1 (tm1/tm1w) ..................................... 250 timer register 2 (tm2/tm2w) ..................................... 289 timer register 3 (tm3/tm3w) ..................................... 360 transmit shift register (txs) ....................................... 416 transmit shift register 2 (txs2) .................................. 416 [w] watchdog timer mode register (wdm) .............. 374, 515 appendix d register index 737 user? manual u11316ej4v1ud d.2 register index (register symbol) [a] adcr: a/d conversion result register ........................ 388 adic: interrupt control register ................................... 510 adm: a/d converter mode register ............................. 389 asim: asynchronous serial interface mode register ....................................................................................... 417 asim2: asynchronous serial interface mode register 2 ....................................................................................... 417 asis: asynchronous serial interface status register ....................................................................................... 420 asis2: asynchronous serial interface status register 2 ....................................................................................... 420 [b] brgc: baud rate generator control register .............. 437 brgc2: baud rate generator control register 2 ......... 437 [c] cic00: interrupt control register .................................. 509 cic01: interrupt control register .................................. 509 cic10: interrupt control register .................................. 509 cic11: interrupt control register .................................. 509 cic20: interrupt control register .................................. 509 cic21: interrupt control register .................................. 509 cic30: interrupt control register .................................. 509 clom: clock output mode register ............................. 491 cr00: compare register .............................................. 191 cr01: compare register .............................................. 191 cr02: capture register ................................................ 191 cr10/cr10w: compare register ................................ 250 cr11/cr11w: capture/compare register .................. 250 cr12/cr12w: capture register .................................. 251 cr20/cr20w: compare register ................................ 289 cr21/cr21w: capture/compare register .................. 289 cr22/cr22w: capture register .................................. 290 cr30/cr30w: compare register ................................ 360 crc0: capture/compare control register 0 ................ 195 crc1: capture/compare control register 1 ................ 254 crc2: capture/compare control register 2 ................ 293 csiic: interrupt control register .................................. 511 csiic1: interrupt control register ................................ 511 csiic2: interrupt control register ................................ 511 csim: clocked serial interface mode register ... 449, 466 csim1: clocked serial interface mode register 1 ...... 430 csim2: clocked serial interface mode register 2 ...... 430 [d] dacs0: d/a conversion value setting register 0 ....... 407 dacs1: d/a conversion value setting register 1 ....... 407 dam: d/a converter mode register ............................. 407 [h] hldm: hold mode register .......................................... 607 [i] iicc: i2c bus control register ............................. 451, 466 imc: interrupt mode control register ........................... 514 ims: internal memory size switching register ............... 83 intm0: external interrupt mode register 0 ................. 495 intm1: external interrupt mode register 1 ................. 495 ispr: in-service priority register ................................. 496 [m] mk0h: interrupt mask register h ................................ 512 mk0l: interrupt mask register l .................................. 512 mk1l: interrupt mask register 1l ................................ 512 mm: memory extension mode register .............. 575, 588 [o] ospc: one-shot pulse output control register ........... 197 osts: oscillation stabilization time specification register .............................................................................. 107, 614 [p] p0: port 0 ..................................................................... 115 p0h: port 0 buffer register h ....................................... 176 p0l: port 0 buffer register l ........................................ 176 p1: port 1 ..................................................................... 120 p2: port 2 ..................................................................... 131 p3: port 3 ..................................................................... 136 p4: port 4 ..................................................................... 145 p5: port 5 ..................................................................... 151 p6: port 6 ..................................................................... 158 p7: port 7 ..................................................................... 168 pic0: interrupt control register .................................... 509 pic1: interrupt control register .................................... 509 pic2: interrupt control register .................................... 509 pic3: interrupt control register .................................... 509 pic4: interrupt control register .................................... 510 pic5: interrupt control register .................................... 510 pm0: port 0 mode register .......................................... 116 pm1: port 1 mode register .......................................... 126 appendix d register index 738 user? manual u11316ej4v1ud pm3: port 3 mode register .......................................... 141 pm4: port 4 mode register .......................................... 147 pm5: port 5 mode register .......................................... 153 pm6: port 6 mode register .......................................... 165 pm7: port 7 mode register .......................................... 168 pmc1: port 1 mode control register ........................... 129 pmc3: port 3 mode control register ........................... 141 prm0: prescaler mode register 0 ...................... 194, 362 prm1: prescaler mode register 1 ...................... 253, 292 pswl: program status word ................................ 84, 516 puo: pull-up resistor option register .................................... 118, 129, 134, 144, 150, 156, 167 pwc1: programmable wait control register 1 ............ 589 pwc2: programmable wait control register 2 ............ 589 pwm0: pwm modulo register 0 .................................. 380 pwm1: pwm modulo register 1 .................................. 380 pwmc: pwm control register ..................................... 379 pwpr: pwm prescaler register .................................. 380 [r] rfa: refresh area specification register .................... 603 rfm: refresh mode register ....................................... 602 rtpc: real-time output port control register ............. 175 rxb: receive buffer .................................................... 416 rxb2: receive buffer 2 ............................................... 416 [s] scs0: sampling clock selection register .................... 497 seric: interrupt control register ................................. 510 seric2: interrupt control register ............................... 511 sio: serial shift register ..................................... 448, 465 sio1: serial shift register 1 ......................................... 429 sio2: serial shift register 2 ......................................... 429 spcic: interrupt control register ................................. 511 sprm: prescaler mode register for serial clock .............................................................................. 450, 469 sric: interrupt control register ................................... 510 sric2: interrupt control register ................................. 511 stbc: standby control register .......................... 106, 612 stic: interrupt control register .................................... 511 stic2: interrupt control register .................................. 511 sva: slave address register .............................. 465, 470 [t] tm0: timer register 0 .................................................. 191 tm1/tm1w: timer register 1 ...................................... 250 tm2/tm2w: timer register 2 ...................................... 289 tm3/tm3w: timer register 3 ...................................... 360 tmc0: timer control register 0 .......................... 193, 361 tmc1: timer control register 1 .......................... 252, 291 toc: timer output control register .................... 196, 295 txs: transmit shift register ......................................... 416 txs2: transmit shift register 2 ................................... 416 [w] wdm: watchdog timer mode register ................ 374, 515 739 user? manual u11316ej4v1ud appendix e revision history the history of revisions hitherto made is shown as follows. (1/3) edition revisions chapter second addition of description on pd784031 and 784031y general addition of 80-pin plastic qfp (14 14 mm, 1.4 mm thick) addition of description on pd784908 subseries and 78f4943 subseries to chapter 1 general 78k/iv series product development diagram division of description on v dd and v ss pins into following two: chapter 2 pin functions ? dd v dd0 : positive power supply pin of ports v dd1 : positive power supply pin of function blocks other than ports ? ss v ss0 : gnd pin of ports v ss1 : gnd pin of function blocks other than ports addition of note on internal memory size switching register (ims) chapter 3 cpu architecture 8.5 external event counter function in chapter 8 chapter 8 timer/counter 0 timer/counter 0 correction of tm0 timing of figure 8-10 timer/counter 0 external event count timing 9.5 external event counter function in chapter 9 chapter 9 timer/counter 1 timer/counter 1 correction of tm1 timing of figure 9-10 timer/counter 1 external event count timing 10.5 external event counter function in chapter 10 chapter 10 timer/counter timer/counter 2 2 correction of tm2 timing of figure 10-11 timer/counter 2 external event count timing low-speed conversion (f clk = 16 mhz) chapter 14 a/d converter 240/f clk (15 s) 180/f clk (11.25 s) addition of notes on switching of msb/lsb first chapter 17 asynchronous change of table 17-4 example of brgc settings when baud rate serial interface/3-wire generator is used serial i/o unification of clo pin to clkout pin chapter 20 clock output function addition of notes of external wait function chapter 23 local bus change of figure 23-10 programmable wait control register (pwc1, interface function pwc2) format addition of notes on releasing standby mode chapter 24 standby addition of figure 24-5 operation after halt mode release function addition of figure 24-6 operation after stop mode release addition of figure 24-9 operation after idle mode release addition of appendix e general index appendix e general index appendix e revision history 740 user? manual u11316ej4v1ud (2/3) edition revisions chapter third change in 78k/iv series product development diagram chapter 1 general ? addition of table 3-6 limits of reading timer register chapter 3 cpu architecture ? addition of table 8-5 limits of reading timer register chapter 8 timer/counter 0 ? addition of table 9-4 limits of reading timer register chapter 9 timer/counter ? addition of figures 9-5 and 9-20 example of occurrence of unnecessary interrupt requests from compare register , and caution ? addition of table 10-5 limits of reading timer register chapter 10 timer/counter 2 ? addition of figures 10-5 and 10-22 example of occurrence of unnecessary interrupt requests from compare register , and caution ? addition of table 11-2 limits of reading timer register chapter 11 timer 3 ? change from "if the stop mode or idle mode is entered as the result of an chapter 12 watchdog timer inadvertent program loop" to "if the stop mode, halt mode, or idle mode is entered as the result of an inadvertent program loop" in (2) <5> in 12.4.1 general cautions on use of watchdog timer ? change of figure 14-11 hardware start select mode a/d conversion chapter 14 a/d converter operation ? addition of notes on disabling reception completion interrupt in case of reception chapter 17 asynchronous error and how to calculate wait time serial interface/3-wire serial i/o ? change and addition of ?he watchdog timer must not be used to release the chapter 24 standby standby mode (stop or idle mode?to ?he watchdog timer must not be used function to release the standby mode (stop, halt, or idle mode ? deletion of watchdog timer of "non-maskable interrupt requests (nmi pin input and watchdog timer)" ? addition of figure b-4 drawing of tgk-080sdw appendix b development tool fourth addition of the following special grade products to the target products throughout ? pd784031gc(a)-3b9, 784035gc(a)- -3b9, 784036gc(a)- -3b9 deletion of the following packages ? pd784031gc-3b9, 784031gk-be9, 784035gc- -3b9, 784035gk- - be9, 784036gc- -3b9, 784036gk- -be9, 784037gc- -3b9, 784037gk- -be9, 784038gc- -3b9, 784038gk- -be9, 78p4038gc- 3b9, 78p4038gc- -3b9, 78p4038gc- -8bt, 78p4038gk-be9, 78p4038gk- -be9, 78p4038kk-t ? pd784031ygc-3b9, 784031ygk-be9, 784035ygc- -3b9, 784035ygk- -be9, 784036ygc- -3b9, 784036ygk- -be9, 784037ygc- -3b9, 784037ygk- -be9, 784038ygc- -3b9, 784038ygk- -be9, 78p4038ygc-3b9, 78p4038ygc- -3b9, 78p4038ygc- -8bt, 78p4038ygk-be9, 78p4038ygk- -be9, 78p4038ykk-t addition of the following packages ? pd784031gk-9eu, 784035gk- -9eu, 784036gk- -9eu, 784037gk- -9eu, 784038gk- -9eu, 78p4038gk-9eu\ ? pd784031ygk-9eu, 784035ygk- -9eu, 784036ygk- -9eu, 784037ygk- -9eu, 784038ygk-xxx-9eu, 78p4038ygk-9eu appendix e revision history 741 user? manual u11316ej4v1ud (3/3) edition revisions chapter fourth ? update of 78k/iv series product development diagram chapter 1 general ? addition and deletion of products in 1.2 ordering information and quality grades ? addition of 1.7 differences between standard-grade products and special-grade products addition of caution on compare register cr00 match interrupt to 8.9 cautions chapter 8 timer/counter 0 addition of caution on compare register cr10 match interrupt to 9.8 cautions chapter 9 timer/counter 1 addition of caution on compare register cr20 match interrupt to 1 0.10 cautions chapter 10 timer/counter 2 modification of description in figure 14-3 a/d converter mode register (adm) chapter 14 a/d converter format addition of caution on successive reception in 3-wire serial i/o mode to chapter 17 asynchronous 17.5 cautions serial interface/3-wire serial i/o ? modification of figure 18-6 3-wire serial i/o mode timing chapter 18 3-wire/2-wire ? 18.6 cautions serial i/o mode ? addition of caution on transmit data write in 3-wire serial i/o mode ? addition of caution on serial clock count operation in 3-wire serial i/o mode ? addition of caution on serial clock output in 3-wire serial i/o mode ? addition of caution on successive reception in 3-wire serial i/o mode addition of description to 21.2 edge detection for pins p20, p25 and chapter 21 edge p26 detection function addition of chapter chapter 28 electrical specifications addition of chapter chapter 29 package drawings addition of chapter chapter 30 recommended soldering conditions addition of description in table a-1 differences with pd784026 subseries appendix a differences with pd784026 subseries modification of description appendix b development tools modification of description appendix c embedded software |
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